JPS6129148B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to complementary insulated gate field effect transistors.

In recent years, the density of integrated circuits has increased, but
The accompanying increase in power consumption causes a rise in temperature, resulting in problems such as decreased reliability and deterioration of characteristics. This has created a demand for lower power consumption in integrated circuits. In this regard, complementary insulated gate field effect transistors (hereinafter referred to as complementary insulated gate field effect transistors)
MISFET (abbreviated as MISFET) has low power consumption, and is superior to conventional single-channel MISFET in terms of noise immunity and speed, in addition to low power consumption.

FIG. 1 shows the basic circuit configuration of a complementary MISFET. Here, 1 is the input signal terminal, 2
are output signal terminals, 3 and 4 are terminals that apply voltage to drive the circuit, 5, 6, and 7 are the gate, source, and drain of the P channel MISFET, respectively, and 8, 9, and 10 are the n channel
These are the gate, source, and drain of the MISFET.

FIG. 2 shows an example of a conventional structure in which the basic circuit shown in FIG. 1 is integrated into an integrated circuit. Here, 11 is an input terminal. 12, 13, and 14 are aluminum electrodes made by vapor deposition or the like; 15, 18 are aluminum gates or gates made of polycrystalline silicon; 16, 17 are P-type diffusion layers; 19,
20 is an n-type diffusion layer, 21 is an isolation region (generally called a P-well) formed by a P-type diffusion layer, 22 is a gate oxide film, 23 is a field insulating film, and 24 is an n-type substrate.

However, the complementary MISFET configured in this way
In order to form two mutually opposing channels in a semiconductor substrate, specifically, a P-channel and an N-channel MISFET, one
MISFETs had to be formed inside an isolation region (called a well) formed by a diffusion layer having a conductivity different from that of the semiconductor substrate. Furthermore, it was necessary to connect the gate electrodes of these two MISFETs with vapor-deposited wiring or the like.

Therefore, the area occupied in the integrated circuit is larger than that of a single channel MISFET, which is disadvantageous in terms of increasing packaging density.

The object of the invention is to eliminate the above-mentioned disadvantages by providing a complementary structure consisting of a single gate and without the need for isolation regions.
The purpose of this invention is to provide a new structure for MITFETs to enable increased packing density in integrated circuits.

In order to achieve the above object, in the present invention, either a P-channel MISFET or an N-channel MISFET is formed on a semiconductor substrate in the same manner as before, and a layer is formed on the source or drain region of one of the MISFETs. , a MISFET with the opposite channel to that MISFET is formed vertically protruding from the substrate, and consists of these two channels.
It is configured to integrate the MITFET gate. That is, conventionally, both P-channel MISFET and N-channel MISFET were formed planarly on a semiconductor substrate, but in the present invention, by forming them three-dimensionally, there is no need for an isolation region, and the gate can also be removed. Since it is a single device, there is no need for wiring or the like, which has the advantage of reducing the area occupied on the semiconductor substrate.

The details of the present invention will be explained below with reference to the drawings.

FIG. 3 shows one embodiment of a complementary MISFET with a single gate topology according to the present invention.
Reference numeral 25 denotes a gate electrode made of aluminum, polycrystalline silicon, or the like, and is an input signal terminal corresponding to the gates 15 and 18 in FIG. 2 integrated into one. 26 is an electrode made of aluminum or the like, and is an output signal terminal corresponding to 12 in FIG. Reference numerals 27 and 28 are electrodes similarly made of aluminum or the like, and correspond to 13 and 14 in FIG.

29, 30, 31 are n-channel MISFETs
These are source, drain, and channel regions, respectively, and are n-type, n-type, and p-type regions, respectively, and correspond to 19, 20, and 21 in FIG. 32,3
Reference numerals 3 denote the source and drain of a P-channel MISFET, which are formed of P-type regions and correspond to 16 and 17 in FIG. Furthermore, 34 is a gate oxide film, 35 is a field insulating film, and 36 is an n-type substrate. With such a configuration, a complementary MISFET can be formed without forming an isolation region. The complementary MISFET according to the present invention is not limited to the embodiment shown in FIG. 3, but can also be modified and implemented as shown in FIG. 4. Here, in FIG. 4, parts corresponding to those in FIG. 3 are indicated by the same reference numerals. This embodiment is characterized in that the drain 30 of the n-channel MISFET is formed within the source region 33 of the p-channel MISFET, and the same effect as the embodiment of FIG. 3 can be obtained.

Although the electrode 26 is in contact with both layers 30 and 33, it may be in contact with either one. Furthermore, the positional relationship between the P-channel MISFET and the n-channel MISFET may be reversed.

Next, an example of a method for manufacturing a complementary MISFET according to the present invention will be described.

First, as shown in FIG. 5a, the n-type substrate 37
First, two P-type diffusion layers 38 are formed spaced apart from each other by a thermal diffusion method or the like, and an n-type diffusion layer 39 is further diffused into one of them by a similar method. And board 3
A P-type semiconductor layer 40 is formed on 7 by an epitaxial growth method or the like, and an n-type semiconductor layer 41 is further formed thereon by an epitaxial growth method or a thermal diffusion method.

Next, as shown in FIG. 5b, the layers 40 and 41 are partially oxidized by patterning using a glass mask or the like to form a field insulating film 42, and after separating the field region and the element region, further patterning is performed. Vertical shape due to anisotropic etching etc.
Form part 5 of the MISFET into the shape shown in the figure.

Next, as shown in FIG. 5c, the gate oxide film 4
3, and a gate 44 made of polycrystalline silicon or the like is formed thereon. Then, an insulating film 45 is formed over the entire structure for insulation.

Then, as shown in FIG. 4, a contact hole is opened, and an electrode made of aluminum or the like is deposited and patterned to finish.

Note that this manufacturing process is just an example, and the third
Any process may be used as long as the element can be formed into a structure as shown in FIGS. For example, the device region may be first separated using a field insulating film, and then the vertical transistor portion may be formed by epitaxial growth or the like.

As detailed above, in the complementary MISFET with a single gate three-dimensional structure according to the present invention, one MISFET is formed vertically, so the space on the semiconductor substrate can be effectively used, and furthermore, an isolation region is not required. The gate can be shared, and the area occupied on the semiconductor substrate can be reduced. Furthermore, the manufacturing process is also easier compared to conventional structures. Therefore, the present invention is extremely effective in integrated circuit devices.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic circuit of a complementary MISFET, FIG. 2 is a sectional view showing a conventional structure in which the circuit of FIG. 1 is integrated, and FIGS. 3 and 4 are:
FIGS. 5a to 5c are structural diagrams showing one embodiment of a complementary MISFET according to the present invention, and process cross-sectional views showing an example of a method for manufacturing a complementary MISFET according to the present invention. 36... Substrate, 32, 33... Source/drain, 29, 30... Source/drain, 34...
Gate oxide film, 25...gate electrode.

Claims (1)

[Claims] 1. An insulated gate field effect transistor of one conductivity type formed on a semiconductor substrate, and an insulated gate electric field of an opposite conductivity type connected complementary to this transistor and protruding from the source or drain region of the transistor of the semiconductor substrate. 1. A complementary insulated gate field effect transistor, characterized in that the gate electrodes of the insulated gate field effect transistors of one conductivity type and the opposite conductivity type are integrally formed in common.