JPS6146042A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6146042A JPS6146042A JP59167477A JP16747784A JPS6146042A JP S6146042 A JPS6146042 A JP S6146042A JP 59167477 A JP59167477 A JP 59167477A JP 16747784 A JP16747784 A JP 16747784A JP S6146042 A JPS6146042 A JP S6146042A
- Authority
- JP
- Japan
- Prior art keywords
- vertical groove
- channel transistor
- well
- integration
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 abstract description 17
- 238000002955 isolation Methods 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 229920005591 polysilicon Polymers 0.000 abstract description 7
- 230000010354 integration Effects 0.000 abstract description 5
- 238000001020 plasma etching Methods 0.000 abstract 1
- 238000000926 separation method Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体装置における素子分離構造に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an element isolation structure in a semiconductor device.
（従来の技術）
本発明は、半導体装置全般に適用できるもので必るが、
本発明の特徴である、異なる導電型の拡散層の分離及び
深い拡散層の分離を同時に要求される相補型電界効果ト
ランジスタ（以下ＣＭＯ８ＦＥＴ という）を例として
、従来技術と比較して説明する。(Prior Art) Although the present invention is applicable to semiconductor devices in general,
A description will be given of a complementary field effect transistor (hereinafter referred to as CMO8FET) which requires simultaneous separation of diffusion layers of different conductivity types and separation of a deep diffusion layer, which is a feature of the present invention, by comparing it with the prior art.
０ＭＯ８ＦＥＴにおいては、Ｎチャンネルトランジスタ
とＰチャンネルトランジスタとを同時に有することから
、２種のトランジスタを分離するため、半導体基板と逆
の導電型のいわゆるフェル領域と呼ばれる深い拡散層を
必要とする。一方ＮチャンネルトランジスタとＰチャン
ネルトランジスタのゲート電極には同じ信号が加わるた
め両者は近接して配置されることが多い。Since the 0MO8FET has an N-channel transistor and a P-channel transistor at the same time, it requires a deep diffusion layer called a so-called Fell region, which has a conductivity type opposite to that of the semiconductor substrate, in order to separate the two types of transistors. On the other hand, since the same signal is applied to the gate electrodes of the N-channel transistor and the P-channel transistor, they are often placed close to each other.
第２図は従来技術による０ＭＯ８ＦＥＴの例であり、
＃半導体基板ｔｌｃＰ型の深い拡散層（Ｐウェル）２に
よｐＮチャンネル領域を分離し、素子分離には選択酸化
による厚い酸化膜１１１用い、ゲート電極としてはポリ
シリコンを用いている。Figure 2 is an example of a 0MO8FET according to the prior art,
#Semiconductor substrate tlc A pN channel region is isolated by a P-type deep diffusion layer (P well) 2, a thick oxide film 111 by selective oxidation is used for element isolation, and polysilicon is used as a gate electrode.
一般にフィールド酸化膜の厚さは１μｍ前後であるが、
素子分離をより完全にするためＮチャンネル領域にはＰ
＋チャンネルストッパー３．Ｐテヤンネル領域にはＮ＋
チャンネルストッパー４を入れている。またＰウェル２
の深さは５μｍ前後あるため、Ｐウェル２の横方向拡散
も５μｍ程度となシ、前述のチャンネルストッパー３の
形成の必要性から、ＰチャンネルトランジスタとＮチャ
ンネルトランジスタの間隔は７０μｍ以上必要であシ、
集積回路においては、高集積化の防げとなってい友。Generally, the thickness of the field oxide film is around 1 μm,
In order to achieve more complete element isolation, P is added to the N channel region.
+ Channel stopper 3. N+ in the P-teyannel region
Channel stopper 4 is installed. Also P well 2
Since the depth of the P-well 2 is approximately 5 μm, the lateral diffusion of the P-well 2 is also approximately 5 μm.Due to the necessity of forming the channel stopper 3 mentioned above, the interval between the P-channel transistor and the N-channel transistor must be at least 70 μm. C,
In integrated circuits, it is a barrier to higher integration.
（発明が解決しようとする問題点）
本発明の目的は集積度の高い集積回路を得ることにある
。(Problems to be Solved by the Invention) An object of the present invention is to obtain an integrated circuit with a high degree of integration.
（問題点を解決するための手段）
本発明によれば、−導電型半導体基板と、この半導体基
板に形成された一方の導電型の半導体素子と、半導体基
板に形成された他の導電型領域と、この他の導を型傾劣
に形成された他方の導電型の半導体素子と、他の導電型
領域の側面外周部に設けられた溝領域とを含む半導体装
置を得る。(Means for Solving the Problems) According to the present invention, - a conductivity type semiconductor substrate, a semiconductor element of one conductivity type formed on the semiconductor substrate, and a region of the other conductivity type formed on the semiconductor substrate; A semiconductor device is obtained which includes a semiconductor element of the other conductivity type in which the other conductor is formed with a pattern gradient, and a groove region provided on the outer periphery of the side surface of the other conductivity type region.
（実施例） 次に、本発明を図面全参照してよシ詳細に説明する。(Example) Next, the present invention will be described in detail with reference to all the drawings.
第り図は、Ｎ型基板、Ｐウェル方式の０Ｍ０８ＦＥＴに
おける本発明の実施例であシ、ＬはＮ型半導体基板、２
はＰウェル、５はＮ十拡散層、６はＰ＋拡散層、７はゲ
ートポリシリコン電極、８はゲート酸化膜、９はコンタ
クトホール、ＬＯはアルミ配線、【２は縦溝、１３はポ
リシリコンである。The second figure shows an embodiment of the present invention in an N-type substrate, P-well type 0M08FET, L is an N-type semiconductor substrate, 2
is P well, 5 is N+ diffusion layer, 6 is P+ diffusion layer, 7 is gate polysilicon electrode, 8 is gate oxide film, 9 is contact hole, LO is aluminum wiring, [2 is vertical groove, 13 is polysilicon It is.
Ｐウェル１の周辺は深い縦溝Ｌ２によシ分離され、同時
にこの縦溝はＮチャンネルトランジスタにおけるソース
、ドレインのＮ＋拡散層５とＰチャンネルトランジスタ
におけるＰ＋拡散層６の分離としての役割を果たしてい
る。この縦溝Ｌ２は、リアクディプイオンエッチによシ
、幅２μｍ深さ６μｍ程度に形成した後表面を酸化し、
酸化膜で覆った後、ポリシリコンで埋められ、エッチバ
ックすることにより表面が平坦化される。後の工程は公
知のＣＭＯｆ１３ＦＥＴ製造プロセスによシ実現される
Ｏ
本発明の素子分離によると次のような長所がある０
（１）Ｐウェル２の横方向拡散を考慮する必要がない０
（２１ソース、ドレイン拡散層を溝【２で終端すること
によ、９、Ｐ”、Ｎ＋拡散層間の余裕が不要。The periphery of the P-well 1 is separated by a deep vertical groove L2, and at the same time, this vertical groove serves as a separation between the N+ diffusion layer 5 of the source and drain of the N-channel transistor and the P+ diffusion layer 6 of the P-channel transistor. . This vertical groove L2 is formed by reactive dip ion etching to a width of about 2 μm and a depth of about 6 μm, and then the surface is oxidized.
After covering with an oxide film, it is filled with polysilicon, and the surface is planarized by etching back. The subsequent steps are realized by the known CMOf13FET manufacturing process.The device isolation of the present invention has the following advantages: (1) There is no need to consider the lateral diffusion of the P well 2. By terminating the source and drain diffusion layers with the groove [2], there is no need for a margin between the 9, P'', and N+ diffusion layers.
（３） チャンネルストッパーが不要。(3) No channel stopper required.
（４１ＮチャンネルトランジスタとＰチャンネルトラン
ジスタのドレインコンタクトを連続させることができる
ため、拡散層−コンタクト間の余裕が不要。(41 Since the drain contacts of the N-channel transistor and the P-channel transistor can be made continuous, there is no need for a margin between the diffusion layer and the contact.
（発明の効果）
以上の特徴によ）、本発明においてはＰチャンネルトラ
ンジスターＮチャンネルトランジスタ間隔を従来の２０
μｍから縦溝の幅２μｍに短縮することができ、集積度
を増大したばかシでなく、ドレイン面積縮少によシ接合
容量を約３０％減少” 出来、結果として動作速度が向
上した。また、Ｐウェル側面が絶縁分離されたことによ
ｐ、０Ｍ０８ＦＥＴの特有なラッチアップ耐量について
も改善することが出来た。(Effects of the Invention) Due to the above features, the present invention has a P-channel transistor to N-channel transistor spacing of 20
The width of the vertical groove can be shortened from μm to 2μm, which not only increases the degree of integration, but also reduces the junction capacitance by approximately 30% by reducing the drain area, resulting in an increase in operating speed. By insulating and separating the side surfaces of the P well, it was also possible to improve the latch-up resistance characteristic of the P,0M08FET.
本発明の実施例はＣＭＯｉＳＦＥＴのＰウェル分離でお
るが、これはそのまｔ ７＜イボーラ集積回路の素子分
離にそのまま適用することが可能である。Although the embodiment of the present invention uses P-well isolation of CMOiSFET, it can be directly applied to element isolation of t7<Ibora integrated circuit.
第１図は本発明の一実施例を示す断面図、第２図は従来
技術における０Ｍ０８ＦＥＴの断面図である。
Ｌ・・・・・・Ｎ型クリコン基板、２・・・・・・Ｐウ
ェル、３・・・・・・Ｐ＋チャンネルストツノく−、４
・・・・・・Ｎ＋チャンネルストッパー、５・・・・・
・Ｎ＋拡散層、６・・・・・・Ｐ＋拡散層、７・・・・
・・ポリシリコンゲート電極、８・・・・・・ゲート酸
化膜、９・・・・・・コンタクトホール、【０・・・・
・・アルミニクム配線、１【・・・・・・フィールド酸
化膜、１２・・・・・・縦溝、１３・・・・・・ポリシ
リコン。FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional 0M08FET. L...N-type crystal substrate, 2...P well, 3...P+ channel stock, 4
...N+ channel stopper, 5...
・N+ diffusion layer, 6...P+ diffusion layer, 7...
... Polysilicon gate electrode, 8 ... Gate oxide film, 9 ... Contact hole, [0 ...
...Aluminum wiring, 1 [...Field oxide film, 12...Vertical groove, 13...Polysilicon.
Claims (1)
方の導電型の半導体素子と、該半導体基板に形成された
他の導電型の半導体領域と、該半導体領域に形成された
他方の導電型の半導体素子と、前記半導体領域の周辺に
接して設けられた溝とを有することを特徴とする半導体
装置。A semiconductor substrate of one conductivity type, a semiconductor element of one conductivity type formed on the semiconductor substrate, a semiconductor region of another conductivity type formed on the semiconductor substrate, and a semiconductor region of the other conductivity type formed on the semiconductor region. What is claimed is: 1. A semiconductor device comprising: a semiconductor element having a mold shape; and a groove provided in contact with the periphery of the semiconductor region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59167477A JPS6146042A (en) | 1984-08-10 | 1984-08-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59167477A JPS6146042A (en) | 1984-08-10 | 1984-08-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6146042A true JPS6146042A (en) | 1986-03-06 |
Family
ID=15850403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59167477A Pending JPS6146042A (en) | 1984-08-10 | 1984-08-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6146042A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01173741A (en) * | 1987-12-21 | 1989-07-10 | Internatl Business Mach Corp <Ibm> | Semiconductor device |
| US4939567A (en) * | 1987-12-21 | 1990-07-03 | Ibm Corporation | Trench interconnect for CMOS diffusion regions |
| US5040043A (en) * | 1988-10-12 | 1991-08-13 | Nippon Telegraph And Telephone Corporation | Power semiconductor device |
-
1984
- 1984-08-10 JP JP59167477A patent/JPS6146042A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01173741A (en) * | 1987-12-21 | 1989-07-10 | Internatl Business Mach Corp <Ibm> | Semiconductor device |
| US4939567A (en) * | 1987-12-21 | 1990-07-03 | Ibm Corporation | Trench interconnect for CMOS diffusion regions |
| US5040043A (en) * | 1988-10-12 | 1991-08-13 | Nippon Telegraph And Telephone Corporation | Power semiconductor device |
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