JP3137774B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a high-voltage lateral MOS field-effect transistor and a low-voltage control logic element are formed on the same chip, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a conventional semiconductor device including a high-voltage lateral MOS field-effect transistor and a low-voltage control logic element formed on the same chip as the high-voltage lateral MOS field-effect transistor, a large current is applied to the substrate surface. The flow between the upper drain and source causes problems such as an increase in the ON-state resistance value (hereinafter referred to as “ON resistance”) and exceeding the maximum current density of the aluminum electrode. Therefore, in order to reduce the resistance value at the aluminum electrode portion or increase the allowable current value, a method of increasing the aluminum thickness of the aluminum electrode may be considered. However, when the aluminum thickness of the high voltage lateral MOS field effect transistor is increased due to the limitation of the low voltage control logic element pattern, there is a disadvantage that the integration degree of the low voltage control logic element portion is reduced.

Therefore, a semiconductor device in which the aluminum electrode portion shown in FIG. 4 has an aluminum two-layer structure has been realized. 4A and 4B are cross-sectional structural views of a conventional semiconductor device. FIG. 4A shows a cross section of a pattern portion of a high-voltage lateral MOS field-effect transistor of the semiconductor device, and FIG. 4B shows a low-voltage control logic element of the semiconductor device. 2 shows a cross section of a part. In FIG. 4, reference numeral 31 denotes a high-concentration second conductivity type (N-type or P-type) drain contact region;
2 is a low-concentration second-conductivity-type drain region, 33 is a first-conductivity-type (P-type or N-type) semiconductor substrate, 34 is a channel portion, 35 is a gate oxide film, and 36 is a gate electrode made of a polycrystalline silicon film. , 37 and 43 are interlayer insulating films, 38 is a high-concentration second conductivity type source region, 39 is a first layer source aluminum electrode, 40 is a second layer source aluminum electrode, 41 is a first layer drain aluminum electrode, 42 Is a drain aluminum electrode of a second layer, 51 is a drain contact region of a P-channel MOS, 52 is a drain contact region of an N-channel MOS, 53 is a second conductivity type region for insulating the P-channel MOS from the semiconductor substrate 33, and 54 is a single layer Eye aluminum electrode 5
The surface portion 56 of the semiconductor substrate connected to 5 is a second-layer aluminum electrode.

In this conventional semiconductor device manufacturing process, after a high-voltage lateral MOS field-effect transistor and a low-voltage control logic element are formed on the same chip, a first aluminum vapor deposition, a dark room process, and etching are performed to form a first aluminum layer. The electrodes 39, 41, 55 are formed. Thereafter, an interlayer insulating film 43 is formed by vapor deposition of an interlayer insulating film, a dark room process, and etching, and then second-layer aluminum electrodes 40, 42, and 56 are formed by a second layer of aluminum vapor deposition, a dark room process, and etching. I was

[0005]

However, according to the conventional structure in which the aluminum electrode portion has a two-layer structure as shown in FIG. 4, two aluminum electrodes 39, 41 and 55 are formed two times after the formation. A dark room process is required, and two dark room processes are added as compared with a single-layer aluminum electrode structure, which has the disadvantage that the manufacturing process becomes complicated.

An object of the present invention is to reduce the on-resistance of a high-voltage lateral MOS field-effect transistor and to increase the maximum current density of an aluminum electrode, and to simplify a manufacturing process and a semiconductor device. Is to provide a way.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: an aluminum electrode in a region of a high-voltage lateral MOS field-effect transistor; and an aluminum electrode connected to a surface of a semiconductor substrate in a region of a low-voltage control logic element. The first layer of aluminum and the second layer of aluminum directly laminated on the first layer of aluminum, and the aluminum wiring in the region of the low voltage control logic element is formed of the second layer of aluminum.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
Depositing a first layer of aluminum on the entire surface of the semiconductor substrate on which the high-voltage lateral MOS field-effect transistor and the low-voltage control logic element are formed, and coating the aluminum electrode portion in the region of the high-voltage lateral MOS field-effect transistor, A dark room process of coating an aluminum electrode portion connected to the surface of the semiconductor substrate in the region of the voltage control logic element, a process of etching the first aluminum to form a first aluminum electrode, and a process of forming the first aluminum electrode. Depositing a second layer of aluminum over the entire surface of the formed semiconductor substrate, coating the aluminum electrode portion in the region of the high voltage lateral MOS field effect transistor, and forming the aluminum electrode portion and the aluminum wiring in the region of the low voltage control logic element Dark room process to coat the part, and etching the second aluminum layer And a step of forming a Rumi electrode and the aluminum wiring.

[0009]

According to the present invention, in the region of the low-voltage control logic element, a high-voltage lateral MOS field-effect transistor is formed while the aluminum wiring other than the surface of the semiconductor substrate connected to the aluminum electrode has a single-layer aluminum structure. In the territory,
Since the aluminum electrode has an aluminum two-layer structure consisting of the first layer of aluminum and the second layer of aluminum formed directly on it, without lowering the integration degree of the low voltage control logic element part,
It is possible to increase the area of the current flow area at the aluminum electrode of the high-voltage lateral MOS field-effect transistor, thereby reducing the on-resistance and increasing the maximum current density of the aluminum electrode. At the same time, the step of forming an interlayer insulating film conventionally used for insulating the first and second aluminum electrodes can be omitted, and the manufacturing process can be simplified.

[0010]

An embodiment of the present invention will be described below with reference to the drawings. 1A and 1B are cross-sectional structural views of a semiconductor device according to an embodiment of the present invention. FIG. 1A shows a cross section of a pattern portion of a high-voltage lateral MOS field effect transistor of the semiconductor device, and FIG. 2 shows a cross section of a low voltage control logic element section. In FIG. 1, 1 is a high-concentration second conductivity type (N-type or P-type) drain contact region, 2 is a low-concentration second conductivity-type drain region, and 3 is a first conductivity type (P-type or N-type). A semiconductor substrate, 4 a channel portion, 5 a gate oxide film, 6 a gate electrode made of a polycrystalline silicon film,
7 is an interlayer insulating film, 8 is a high-concentration second conductivity type source region,
9 is a first layer source aluminum electrode, 10 is a second layer source aluminum electrode, 11 is a first layer drain aluminum electrode, 12
Is a second layer drain aluminum electrode, 21 is a P channel M
OS drain contact region, 22 is N channel M
OS drain contact region, 23 is P channel M
A second conductivity type region for insulating the OS from the semiconductor substrate 33;
Denotes a surface portion of the semiconductor substrate connected to the first-layer aluminum electrode 25, and 26 denotes a second-layer aluminum electrode.

This semiconductor device has a structure in which aluminum electrodes 9, 10,.
Aluminum electrodes 25, 26 connected to the semiconductor substrate surface 24 in the region of the low voltage control logic elements
Is formed of the first layer of aluminum and the second layer of aluminum directly laminated on the first layer of aluminum. The aluminum wiring in the region of the low-voltage control logic element (the aluminum electrode formed in a region other than the semiconductor substrate surface portion 24) 26) is made of a second layer of aluminum.

A method of manufacturing the semiconductor device thus configured will be described with reference to FIGS. 2 and 3. 2 and 3 are cross-sectional views in the order of steps showing a method of manufacturing the semiconductor device. In FIGS. 2 and 3, (a) is a cross section of a pattern portion of a high-voltage lateral MOS field-effect transistor of the semiconductor device. (B) shows a cross section of the low voltage control logic element portion of the semiconductor device.

As shown in FIGS. 2A and 2B, a high voltage lateral MOS field effect transistor and a low voltage control logic element are formed on the same chip. Next, as shown in FIG. 3, a first layer of aluminum is deposited, a dark room process is performed, and then aluminum is etched. As a result, in the region of the high-voltage lateral MOS field-effect transistor, aluminum remains on all the aluminum electrode portions, the first source aluminum electrode 9 and the first drain aluminum electrode 11 are formed, and the region of the low-voltage control logic element is formed. In the above, aluminum is left only on the semiconductor substrate surface portion 24 connected to the aluminum electrode portion, and the first aluminum electrode 25 is formed.

Then, as shown in FIG. 1, a second layer of aluminum is deposited, a dark room process is performed, and then the aluminum is etched. As a result, in the region of the high-voltage lateral MOS field-effect transistor, aluminum is left on all the aluminum electrode portions, the second source aluminum electrode 10 and the second drain aluminum electrode 12 are formed, and the low voltage control logic element is formed. Also in the region, aluminum is left in all the aluminum electrode portions and the aluminum wiring portions, and the second-layer aluminum electrode 26 is formed.

As described above, according to this embodiment, in the region of the low-voltage control logic element, the aluminum wiring (26) other than the semiconductor substrate surface portion 24 connected to the aluminum electrode 25 remains in a single-layer aluminum structure. In the region of the high voltage lateral MOS field effect transistor, the aluminum electrodes 9 and 1
Since 0, 11, and 12 have an aluminum two-layer structure including a first layer of aluminum and a second layer of aluminum directly formed thereon, a high-voltage horizontal type can be obtained without reducing the degree of integration of the low-voltage control logic element portion. It is possible to increase the current basin area at the aluminum electrode of the MOS field effect transistor,
The on-resistance can be reduced and the maximum current density of the aluminum electrode can be increased. At the same time, the step of forming an interlayer insulating film conventionally used for insulating the first and second aluminum electrodes can be omitted, and the manufacturing process can be simplified.

[0016]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, in the region of the low voltage control logic element, the aluminum wiring other than the surface of the semiconductor substrate connected to the aluminum electrode is formed of a single layer of aluminum. In the region of the high-voltage lateral MOS field-effect transistor, the aluminum electrode has an aluminum two-layer structure including the first aluminum layer and the second aluminum layer formed directly on the aluminum electrode.
It is possible to increase the current basin area at the aluminum electrode of the high-voltage lateral MOS field-effect transistor without reducing the degree of integration of the low-voltage control logic element, thereby reducing the on-resistance and the maximum current density of the aluminum electrode. Can be increased. At the same time, the step of forming an interlayer insulating film conventionally used for insulating the first and second aluminum electrodes can be omitted, and the manufacturing process can be simplified.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a semiconductor device according to one embodiment of the present invention.

FIG. 2 is a sectional structural view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 3 is a sectional structural view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 4 is a sectional structural view of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 3 semiconductor substrate 9 first layer source aluminum electrode 10 second layer source aluminum electrode 11 first layer drain aluminum electrode 12 second layer drain aluminum electrode 24 semiconductor substrate surface portion 25 first layer aluminum electrode 26 second layer aluminum electrode

Claims (2)

(57) [Claims] 1. A semiconductor device in which a high-voltage lateral MOS field-effect transistor and a low-voltage control logic element are formed on the same chip, comprising: an aluminum electrode in a region of the high-voltage lateral MOS field-effect transistor; The aluminum electrode connected to the surface of the semiconductor substrate in the region of the logic element is composed of a first layer of aluminum and a second layer of aluminum directly laminated on the first layer of aluminum, and in the region of the low voltage control logic element. A semiconductor device, wherein aluminum wiring is made of the second layer of aluminum. 2. A step of depositing a first layer of aluminum on the entire surface of a semiconductor substrate on which a high-voltage lateral MOS field-effect transistor and a low-voltage control logic element are formed; and an aluminum electrode portion in a region of the high-voltage lateral MOS field-effect transistor. A dark chamber step of coating the aluminum electrode portion connected to the surface of the semiconductor substrate in the region of the low voltage control logic element, and a step of etching the first aluminum layer to form a first aluminum electrode Depositing a second layer of aluminum on the entire surface of the semiconductor substrate on which the first aluminum electrode is formed; coating the aluminum electrode portion in the region of the high-voltage lateral MOS field-effect transistor; A dark room process of coating the aluminum electrode portion and the aluminum wiring portion in the region of the logic element; The method of manufacturing a semiconductor device including the step of forming said second layer of aluminum by etching with a second layer of the aluminum electrode and the aluminum wiring.