JPS63116470A - Manufacture of semiconductor device provided with memory transistor - Google Patents

Abstract

PURPOSE:To optimize the thicknesses of a memory transistor interlayer insulating film and of a peripheral transistor gate oxide film by a method where the memory transistor and the peripheral transistor are constructed in the respective manufacturing steps in a three-layer polycrystalline silicon process. CONSTITUTION:After the formation of an N-well 4 and field oxide film 6 on a P-type Si substrate 2, a gate oxide film 12 is formed and then boron ion implantation is accomplished. Next, a first polycrystalline silicon layer 14, an interlayer oxide film 16, and a second polycrystalline silicon layer 18 are formed, after which the layers 14, 16, and 18 are subjected to etching, with a resist pattern 20 serving as a mask, for the formation of a memory transistor gate 22. A process follows wherein ions are implanted for the control of the peripheral transistor threshold voltage, after which a second gate oxide film 24 and a third polycrystalline silicon layer 26 are formed. Etching is done for the formation of a gate 22 and peripheral transistor gates 30 and 32. Finally, a source, drain, etc., are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semiconductor device such as an EPROM or an EEPROM having a memory transistor having a two-layer polysilicon structure.

(Prior Art) In a semiconductor device including a memory transistor such as a two-layer polysilicon structure EPROM or EEPROM, after forming the floating gate electrode of the memory transistor,
The interlayer oxide film of the memory transistor and the gate oxide film of the peripheral transistor are formed of the same oxide film, and the control gate electrode of the memory transistor and the gate electrode of the peripheral transistor are formed of the same polysilicon layer.

Generally, the optimal thickness of the interlayer oxide film of the memory transistor and the optimal film thickness of the gate oxide film of the peripheral transistor are different from each other. The optimum value for the interlayer oxide film thickness of the memory transistor is determined from the relationship between write characteristics and retention characteristics. Furthermore, the optimum value for the gate oxide film thickness of the peripheral transistor is determined from the relationship between breakdown voltage and operating speed.

However, in the conventional method, the interlayer oxide film of the memory transistor and the gate oxide film of the peripheral transistor are oxide films formed in the same process.

There is a problem in that it is not possible to set each layer to an optimal film thickness.

(Purpose) An object of the present invention is to provide a method for setting the interlayer insulating film of the memory transistor and the gate oxide film of the peripheral transistor to optimal film thickness in a semiconductor device including a memory transistor with a two-layer polysilicon structure. It is something to do.

(Structure) The manufacturing method of the present invention uses a three-layer polysilicon process to form a memory transistor with a two-layer polysilicon structure and a peripheral transistor with a normal single-layer structure in separate steps.

Specifically, the manufacturing method of the present invention includes the following steps (A) to (J).

(A) Step of forming a first gate oxide film after forming the field oxide film; (B) Ion implantation step for controlling the threshold voltage of the memory transistor; (C) Step of forming the first polysilicon layer; (D) forming a resist pattern for a memory transistor, and using this resist pattern as a mask, forming the second polysilicon layer and the first polysilicon layer in this order; (D) forming a resist pattern for a memory transistor; Etching the interlayer insulating film and the first polysilicon layer to form the gate of the memory transistor.

(E) Ion implantation process for controlling the threshold voltage of peripheral transistors.

(F) Step of forming a second gate oxide film.

(G) forming a third polysilicon layer; (H) forming a resist pattern for a peripheral transistor; using this resist pattern as a mask, etching the third polysilicon layer to form the gate of the memory transistor; The process of forming.

(I) Step of forming a source region and a drain region.

(J) A step of forming a second glabellar insulating film, forming a contact hole, forming a metal wiring, and forming a passivation film.

Examples will be specifically described below.

(1) As shown in FIG. 1, an N-well 4 and a field oxide film 6 are formed on a P-type silicon substrate 2 by a conventional manufacturing process. 8 is the P+ layer of the channel stopper layer;
10 is an N+ layer which is also a channel stopper layer.

After that, a gate oxide film 12 is formed for the memory transistor.
Boron ions (B+) are implanted to control the threshold voltage of the memory transistor. Thereafter, a first polysilicon layer 14 is formed for the floating gate electrode of the memory transistor, a glabellar oxide film 16 is formed thereon, and a second polysilicon layer 14 is further formed for the control gate electrode of the memory transistor. 18
form.

A resist pattern 20 for a memory transistor is formed on the second polysilicon layer 18 by a photolithography process.
form.

(2) Using the resist pattern 20 as a mask, the second polysilicon layer 18, interlayer oxide film 16, first polysilicon layer 14, and gate oxide film 12 are etched to form a memory as shown in FIG. A gate 22 of the transistor is formed.

Thereafter, boron ions are implanted into the entire surface to control the threshold voltages of peripheral transistors.

At this time, since the gate 22 of the memory transistor has already been formed, boron ions are not implanted into the channel region of the memory transistor.

(3) As shown in FIG. 3, a gate oxide film 24 for peripheral transistors is formed.

(4) As shown in FIG. 4, a third polysilicon layer 26 is formed to form a gate of a peripheral transistor, and a resist pattern 28 for the peripheral transistor is formed by a photolithography process.

(5) Etching the third polysilicon layer 26 and gate oxide film 24 using the resist pattern 28 as a mask,
The gate 30 of the peripheral transistor as shown in FIG.
．． form 32.

Next, ion implantation is performed to form the source and drain regions of the memory transistor and peripheral transistor. Source region 34, drain region 36 of the memory transistor and source region 38 of the N-channel peripheral transistor. Group V ions are implanted into the drain region 40 to form an N+ layer, and group (IV) ions are implanted into the source region 42 and drain region 44 of the P channel peripheral transistor to form P''J'l.

(6) As shown in FIG. 6, after forming the interlayer insulating film 46, a contact hole is formed, and gold 1! U
1 (for example, an aluminum layer) and patterned to form wiring 48. Finally, a passivation film 50 is formed thereon.

(Effects) In the present invention, a memory transistor and a peripheral transistor are formed in separate steps using a three-layer polysilicon process. As a result, the polysilicon layer is formed three times, but the number of photolithography steps is the same as in the conventional case.

By forming the memory transistor and the peripheral transistor separately, the interlayer insulating film of the memory transistor and the gate oxide film of the peripheral transistor can be arbitrarily set to optimal film thicknesses.

The present invention can also be applied to custom integrated circuits having memory transistors as op-scenes.

[Brief explanation of the drawing]

1 to 6 are cross-sectional views of a semiconductor device showing an embodiment of the present invention in the order of steps. 2...Silicon substrate, 6...Field oxide film, 12...First gate oxide film. 14...first polysilicon layer, 16...
...First interlayer insulating film, 18...Second polysilicon layer, 20...
...Resist pattern, 22... Gate of memory transistor, 24.
...Second gate oxide film, 26...Third
polysilicon layer, 28...Resist pattern, 30.32...Gate of peripheral transistor, 3
4.36, 38, 40, 42.44...source/drain, 46...second interlayer insulating film, 48...wiring, 50...・Passivation film.

Claims (1)

[Claims] (1) A method for manufacturing a semiconductor device including the following steps (A) to (J). (A) Step of forming a first gate oxide film after forming the field oxide film; (B) Ion implantation step for controlling the threshold voltage of the memory transistor; (C) Step of forming the first polysilicon layer; (D) forming a resist pattern for a memory transistor, and using this resist pattern as a mask, forming the second polysilicon layer and the first polysilicon layer in this order; (D) forming a resist pattern for a memory transistor; Step of etching the interlayer insulating film and the first polysilicon layer to form the gate of the memory transistor, (E) Ion implantation step for controlling the threshold voltage of the peripheral transistor, (F) Second gate oxide film (G) forming a third polysilicon layer; (H) forming a resist pattern for a peripheral transistor, and etching the third polysilicon layer using this resist pattern as a mask; Step of forming the gate of the memory transistor; (I) Step of forming the source region and drain region; (J) After forming the second interlayer insulating film and forming the contact hole, forming the metal wiring and forming the passivation film. The process of forming.