JPS6154669A - Mos type field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a hot carrier effect while inhibiting the lowering of mutual conductance by extending a conductor layer up to sections on low-concentration impurity layers constituting source-drain regions on a boundary section with a gate electrode. CONSTITUTION:A gate insulating film 12 and a gate electrode 13 are formed onto a P type Si substrate 1. N<-> layers 14 are shaped in regions as source-drain through the implantation of ions in low concentration. Side wall SiO2 films 21 having width d1 are formed on both side surfaces of the electrode 13. N<+> layers 16 are shaped in the source-drain regions except regions coated with the films 21 through the implantation of ions in high concentration. The films 21 are removed, and side wall SiO2 films 22 having width d2 narrower than width d1 are shaped on both side surfaces of the electrode 13. Lastly, the surfaces of the layers 16, the surfaces of layers 14A not coated with the films 22 and the surface of the electrode 13 are coated with dielectric layers 23. Accordingly, when a transistor is turned ON, currents flow on the surfaces of the layers 14A coated with the layers 23, thus obtaining a MOSFET having sufficiently low ON-resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a MOS field effect transistor, particularly a MOS field effect transistor incorporating an LDD structure for constructing a highly integrated LSI.
The present invention relates to an S-type field effect transistor and a method for manufacturing the same.

[Background of the invention]

Submicron MOS that composes highly integrated MOSLSI
Field effect transistors (MOS FETs) are so-called LDD (Light
ly doped drain) structure and water.

As shown in FIG. 1, this means that source/drain regions I and JT of a second conductivity type formed on the surface of a semiconductor substrate of a first conductivity type, for example, a P-type silicon substrate 1, are connected to a high concentration impurity region N layer 2. and a low-concentration impurity region N layer 3, with the N layer 3 disposed on the side in contact with a gate region (2) consisting of a gate insulating film 4 and a gate electrode 5. N layer 3
creates a PN-junction with the P-type silicon substrate 1, and expands the depletion layer due to the voltage applied between the drain and source not only to the P layer but also to the N layer 3. acts to weaken the electric field strength. As a result, it is possible to reduce the so-called hot carrier effect, which is the deterioration of the threshold voltage vth due to the injection of hot carriers into the gate insulating film due to a strong electric field.

However, since the N layer 3 is a low concentration impurity region, there is a drawback that when the transistor is turned on and a current flows, the gm of the stub MOSPET, which serves as a high resistance current path, decreases.

A MOS FET having such an LDD structure has conventionally been formed by a method as shown in FIG.

That is, first, an oxide film (t,
acos film) 11 is formed, and then an oxide film (SIO2 film) is formed.
and polysilicon mask tree (refract)
ory) A polycide laminated structure made of metal silicide or a conductive layer made of mask tree metal is formed, and the gate oxide film 1 is formed by etching.
2 and a gate electrode 13 are formed. Then the sauce-
An N-type impurity, for example, phosphorus, is introduced into the region to be a drain by ion implantation, and the N layer 1 of the low concentration N-type impurity region is
4 (Fig. 2(a)).

Next, 5to by LPCVD (low pressure CVD) method etc.
Two layers are deposited and RIE etched.
sidewalls S10.tonetching) are applied to both sides of the gate electrode. A film 15 is formed. Thereafter, an N-type impurity, for example, As, is ion-implanted at a high concentration to form an N layer 16 in the source and drain regions not covered by the sidewall 5tO2 film 15 (FIG. 2(b)).

Finally, by selectively depositing refractory metal, the surfaces of the source/drain regions and the gate electrode 13 that are not covered with the oxide film are covered with a conductor layer 17 made of refractory metal (see Fig. 2). (C)
).

Here, the width of the N layer 14A after forming the N layer 16 is sufficiently large (0.2 to 0.0
．． 4 μm), but since the conductor layer 1T is not formed on the surface of the N single layer 14A, the resistance itself determined by its specific resistance and width acts as the on-resistance of the MOS FET, and the larger the width, the more the conductor layer 1T is formed. Its resistance increases and reduces gtf.

That is, as long as the above-described configuration or manufacturing method is adopted, the reduction of the hot carrier effect and the prevention of gm reduction are in a contradictory relationship.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a MOS type field effect transistor and a method for manufacturing the same, which can prevent the hot carrier effect while suppressing a decrease in gm. There is a particular thing.

[Summary of the invention]

In order to achieve such an object, the MOS type field effect transistor of the present invention has a conductive layer extending over the lightly doped impurity layer constituting the source/drain region at the boundary with the gate electrode. In addition, in the manufacturing method according to the present invention, in order to obtain such a structure, after forming a high concentration impurity region using the first sidewall insulating film formed on the side surface of the gate electrode as a mask, A second narrower sidewall insulating film is formed in place of the wall insulating film, and a conductor layer is formed on the impurity region not covered by the second sidewall insulating film.

[Embodiments of the invention]

FIG. 3 is a process sectional view showing an embodiment of the present invention.

In the figure, first, an oxide film 11 for element isolation is formed on a P-type silicon substrate 1 by the usual method as in FIG. A conductive layer made of a factory metal is formed and etched to form a gate insulating film 12 and a gate electrode 13.
form. Next, a N layer 14 is formed in the regions to be used as sources and drains by ion implantation of phosphorus at a low concentration (FIG. 3(a)).

Next, a 5lo2 layer is deposited by LPCVD method etc.
IE etching is performed to form a first sidewall 5lot film 21 having a width d1 on both sides of the gate electrode. Next, when ions are implanted at a high concentration of As, an N layer 16 is formed only in the source/drain regions other than the region covered with the first sidewall s t O2 film 21 (FIG. 3(b)). Therefore, the sidewall Sin
, if the width d of the film 21 is set large, the N after the N layer 16 is formed.
The width of 14A can be further increased.

Next, after removing the first sidewall oxide film 21 by etching, 5iO
jl, RI by depositing the z layer and controlling its thickness
A second sidewall 5i02 film 22 having a width d2 narrower than dl is formed on both sides of the gate electrode using E.

Finally, the surface of the fiN layer 16 and the sidewalls 5loz are coated by selectively depositing refractory metal.
The surface of the N layer 14A that is not covered with the film 22 and the surface of the gate electrode 13 are covered with a conductive layer 23 made of refractory metal (FIG. 3(C)).

In this case, even if the width of the N'''' layer 14A is made large enough to sufficiently prevent the hot carrier effect as described above,
When the transistor is turned on, current flows through the surface of the N'''' layer 14A covered with the conductor layer 23, so the N layer 1
4A MOS with sufficiently low on-resistance, regardless of its specific resistance and width, and without deterioration of V)g□
FET can be obtained. Note that the conductor layer 23 is
The material is not limited to refractory metal, and may be made of its silicide, for example.

〔Effect of the invention〕

As explained above, according to the MOS field effect transistor of the present invention, by providing a conductor layer also on the low concentration impurity region on the gate region side of the source/drain region,
Hot carrier effects can be prevented while suppressing a decrease in gl of the transistor.

Further, according to the manufacturing method of the present invention, after forming a high concentration impurity region using the first sidewall insulating film as a mask, a conductor is formed on the impurity region using the second narrower sidewall insulating film as a mask. By forming layers,
The structure as described above can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a conventional MOS field effect transistor having an LDD structure, FIG. 2 is a process cross-sectional view thereof, and FIG. 3 is a process cross-sectional view showing an embodiment of the present invention. 1...P-type silicon substrate, 120.・, Gate S
i 02 film, 13...gate electrode, 14° 14A
...N 1 layer, 16...N+ layer, 21...-
First sidewall 81 (h film, 22 fist...second sidewall 5lo2 film, 23...conductor layer. OD

Claims (1)

[Claims] 1. A gate electrode disposed on a semiconductor substrate of a first conductivity type via a gate insulating film, and a gate electrode of a first conductivity type opposite to the first conductivity type disposed on the surface of the semiconductor substrate with the gate electrode in between. In a MOS field effect transistor having a source and a drain consisting of impurity regions of two conductivity types, the impurity region of the second conductivity type includes a high concentration impurity region disposed at a predetermined distance from the gate electrode, and a high concentration impurity region disposed at a predetermined distance from the gate electrode. consisting of a low concentration impurity region disposed at the boundary between the first semiconductor region and the gate electrode,
and a MOS comprising a sidewall insulating film that covers the side surface of the gate electrode, and a conductor layer that covers the surface of the low concentration impurity region and the surface of the high concentration impurity region that are not covered by the sidewall insulating film. type field effect transistor. 2. A step of forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film, and using this gate electrode as a mask, forming a gate electrode of a second conductivity type opposite to the first conductivity type on the surface of the peripheral semiconductor substrate.
A step of ion-implanting a conductive type impurity, a step of forming a first sidewall insulating film on the side surface of the gate electrode, and a step of forming a second conductive film on the surface of the surrounding semiconductor substrate using the first sidewall insulating film and the gate electrode as a mask. a step of ion-implanting a shaped impurity at a high concentration; a step of forming a second sidewall insulating film narrower than the first sidewall insulating film on the side surface of the gate electrode; forming a conductor layer on the second conductivity type impurity region that is not covered by the MOS field effect transistor.