JPS61160975A - Mos field effect transistor - Google Patents

Abstract

PURPOSE:To keep low the coefficient of sub-threshold current, and to reduce VT variations due to drain voltage, by a method wherein a high concentration impurity layer which inhibits the elongation of the drain voltage potential is formed immediately under a channel region at the sides of source-drain regions. CONSTITUTION:After an N-well 7 is formed by a normal process, a P-type channel region 5 is formed by ion implantation through the oxide film; then, a 100Angstrom gate oxide film 3 and a gate electrode 2 are formed. Next, N<+> layers 6 are formed immediately under the P-type channel region 5 by implanting e.g. phosphorus at 130kev and at a dosage of 1.0X10<12>/cm<2>. After deposition of SiO2, an SiO2 side wall 4 is formed by etching removal; thereafter, source- drain region 1 are formed. Then, a MOSFET is completed. Since the MOSFET thus obtained has a high concentration impurity layer 6 of reverse conductivity type to that of the channel region 5 formed immediately under the region 5 at the sides of the source-drain regions 1, the coefficient of sub-threshold current is small, and VT variations due to drain voltage can be inhibited.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a long micron buried channel type MO8 type field effect transistor that can improve the electrical characteristics in the subthreshold region that deteriorate when miniaturizing a buried channel MO8 type field effect transistor to a submicron region. MO8W field effect 57disp
(MOSFIET).

Conventional technology In the ultra-integrated circuit device so-called VLSI, 0MO8
As the technology grows in importance, p-channel MOf9FE
The miniaturization of T is progressing rapidly. However, t-polySi
When using the gate, the channel region of a p-channel MOSFET is the source.

It has the same conductivity type as the drain region. This becomes a so-called buried channel MO3FKT. Embedded channel MO8FXτ
Compared to so-called surface channel MOSFETs, in which the channel region has a conductivity type opposite to that of the source and drain regions, the device structure has a lower electric field strength near the drain and is resistant to hot electron effects. Further, a high-speed MO8FICT with little deterioration in mobility can be obtained.

Similar effects can be expected for n-channel MO3FETs by controlling the work function.

However, when embedded MOSFETs are miniaturized to the micron range, the influence of the drain voltage on the potential of the S i 02-S i interface is large, resulting in an increase in leakage current in the subthreshold region and a decrease in the drain voltage of the threshold voltage v Increase voltage dependence.

1 to deal with this, for example, IICKKTrans
actions Hectron Devices
+ ICD-31PI), 964-988 Kg
It had a structure as shown in FIG. 7, as disclosed in IT, M., CHAM et al.

That is, in the figure, 11 is the source, drain region,
12 is a gate electrode, 13 is a gate oxide film, 14 is a sidewall oxide film, 16 is a p-type channel region, 16 is an n layer, 17 is an n
Well. In this structure, the drain junction depth is made shallow, and in order to make the channel junction depth shallow, in addition to channel doping with BF2, ions of Mu8 are implanted to form a shallow channel junction depth, and the n+ layer 16 is formed. It was formed directly under the channel region 16.

Problems to be Solved by the Invention In this structure, the subthreshold current coefficient can be kept low, but the subthreshold voltage fluctuation due to the drain voltage cannot be kept low.

This is because, as shown by the curve in Figure 6, in order to obtain a shallow channel junction while keeping the subthreshold voltage vT constant, the channel doping dose must be increased and the surface concentration value must be increased. This is because the influence of drain voltage cannot be suppressed.

Therefore, the present invention suppresses the subthreshold current coefficient and suppresses the expansion of the potential due to the drain voltage, thereby reducing the fluctuation due to the drain voltage.

Means for solving the problem and technical means of the present invention for solving the problem are a part directly under the channel region and a source.

A highly concentrated impurity layer is formed on the side of the drain region to suppress potential expansion due to drain voltage.

action The effect of this technical means is as follows.

That is, an impurity layer of a conductivity type opposite to that of the channel region is formed on the sides of the source and drain regions in a part immediately below the channel region, and has a peak concentration value at a depth position intermediate between the channel doped region and the source and drain regions. This reduces the increase in surface concentration in the channel region caused by forming an impurity layer of the opposite conductivity type and shallowing the channel junction depth as in the conventional method, and also suppresses the potential growth of the drain voltage. It is. As a result, it is possible to obtain a buried channel MO8FIET in which no fluctuations due to fluctuations in drain voltage are observed as in the prior art.

EXAMPLE Hereinafter, an example of the present invention will be described based on FIGS. 1 to 7. In FIG. 1, 1 is a p-type source and drain region, 2 is a gate electrode, 3 is a gate oxide film, 4 is a sidewall oxide film, 6 is a p-type channel region of the same conductivity type as the source and drain regions, An n-type high concentration impurity layer 6 having a conductivity type opposite to that of the channel region is formed. Further, 7 is an n-well.

2 to 4 illustrate the manufacturing process of the p-type buried channel MO8FET shown in FIG. 1 and having a gate length of O, S μm. As shown in FIG. 2, after forming the n-well 7 according to the normal process, BF2 for controlling the threshold voltage vT was applied at a dose of 40 keys and a dose of 3.2 x 1o/1-1! ion implantation through the 200-layer oxide film to form a p-type channel region 6,
100 gate oxide films 3 and gate electrodes 2 are selectively formed. Next, as shown in FIG. 3, phosphorus is implanted at 130 keV and at a dose of 1.0×1 d2/C1i to form a male layer 6 directly below the p-type channel region 6. Next, as shown in FIG. 4, after depositing 5i02 by chemical vapor deposition (CVD) and removing it by etching to form SiO2 sidewalls 4,
Self-aligned source and drain regions 1 with BFz of 40
The key is formed by implantation at a dose of 3×1o/c11L. After this, 1. Although not shown in the figure, the MOSFE is
Complete T.

The MOSFET obtained in this way is curve 8 in FIG.
As shown in , even if the channel junction depth is made shallow, the impurity surface concentration in the channel region does not increase as in the conventional case (curve 9). In addition, the curve 10.11 in Figure 6 shows:
MOSFET of this example (gate length 0.5 pm)
Drain current I when drain voltage vDcar s V
D value, the drain current ID value when the drain voltage vD is -O, SV was measured by changing the gate voltage vG, but it is different from that of a conventional MOSFET (gate length 0.5 μm) measured under the same conditions. As can be seen by comparing the measurement curves 10m and 11m, in the MOSFET of this example, vT fluctuations due to drain voltage fluctuations are reduced.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention is a buried channel type MO8 field effect transistor, in which a portion directly below the channel region is doped with impurities, and a high concentration impurity of the opposite conductivity type to the channel region is doped at the sides of the drain region. Because the layer is formed, the subthreshold NR coefficient is small, and the v
T fluctuation can be suppressed.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a buried channel type MO3 field effect transistor according to an embodiment of the present invention. Figures 2 to 4 are cross-sectional views explaining the manufacturing process of the same transistor, Figure 6 is a characteristic diagram showing the relationship between the channel junction depth and impurity distribution of the same transistor in comparison with a conventional one; FIG. 7 is a characteristic diagram showing the ID-VG characteristics of the MO3 type field effect transistor of this example in comparison with the characteristics of a conventional one, and FIG. 7 is a sectional view of the conventional MO3 type field effect transistor. 1... Source, tunnel region %2... Middle gate electrode, 3... Gate oxide film, 4...
Sidewall oxide film, 5...p-type channel region, 6...
. . . n-type high concentration impurity layer, 7 . . . n-well. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
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Claims (1)

[Claims] A semiconductor substrate of one conductivity type, an insulating film selectively formed on this substrate, a channel region of a conductivity type opposite to that of the substrate formed immediately below the insulating film, and a side portion of the channel region. source and drain regions of a conductivity type opposite to that of the substrate selectively formed in a portion immediately below the channel region and on a side of the source and drain regions;
A MOS type field effect transistor characterized in that a high concentration impurity layer of one of the conductivity types is provided.