JP3415496B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, how to form a transistor having high operational reliability and high controllability is one of the important issues. In recent years, in a MIS (metal-insulating film-semiconductor) type transistor, a gate insulating film is thinly formed, and an oxide film having a thickness of 3.0 nm or less is used as the gate insulating film. The silicon oxide film is often used as a gate insulating film because of its high insulating property and ease of film formation.

In order to realize a high withstand voltage of the gate insulating film by forming the gate insulating film thick, an insulating film (high dielectric constant film) having a relative dielectric constant higher than that of the silicon oxide film is used. Sometimes used as. The technique of using the high-dielectric-constant insulating film as the gate insulating film is disclosed in JP-A-63-237578.

However, if a high dielectric constant film (for example, a tantalum oxide film) is formed directly on the silicon substrate, the drain current may be reduced during the operation of the transistor. As described above, when the drain current of the transistor becomes small, it becomes difficult to realize high speed operation of the device. In order to solve this problem, conventionally, a thin silicon oxide film is formed on a silicon substrate and a high dielectric constant film is formed on the silicon oxide film. That is, the gate insulating film is formed of two layers of a silicon oxide film and a high dielectric constant film.

As described above, a technique for forming a gate insulating film of a transistor from two layers is disclosed in Japanese Patent Laid-Open No. 58-19237.
No. 7, Japanese Patent Publication No. 7-114241, and Japanese Patent No. 2816192. In addition to the above, a technique of forming a gate insulating film of an Nch transistor from three layers is disclosed in Japanese Patent Laid-Open No. 1-309380. In the technique disclosed in JP-A-1-309380, a silicon oxide film is formed on a semiconductor substrate, a tantalum oxide film is formed on the silicon oxide film, and a silicon nitride film is formed on the tantalum oxide film. There is.

[0006]

However, the technique described above has the following problems. In the technique of forming the gate insulating film from two layers, the configuration of the gate insulating film is set in consideration of the difference in conductivity type between the N-channel type transistor (Nch transistor) and the P-channel type transistor (Pch transistor). Absent. For this reason,
When an Nch transistor and a Pch transistor are formed on the same substrate, each transistor is formed in the process shown in FIGS. 10A to 10C, for example.

First, as shown in FIG. 10A, a silicon substrate 1 on which a diffusion layer, an element isolation insulating film, and the like are formed in advance.
10 on the silicon oxide film 131 by a thermal oxidation method or the like.
a is formed. Then, CVD (Chemical Vapor Dposi)
Then, as shown in FIG. 10A, a high dielectric constant film 132a is formed on the silicon oxide film 131a. Then, a conductive film 140a is formed on the high dielectric constant film 132 by the CVD method or the like, as shown in FIG. Then, as shown in FIG. 10C, the silicon oxide film 13 is formed by photolithography, etching, or the like.
1a, the high dielectric constant film 132a, and the conductive film 140a are patterned. As a result, the silicon oxide film 131
A gate insulating film including the high dielectric constant film 132 and the gate electrode 140 is formed.

As described above, the Nch transistor and Pc
When the gate insulating film is formed without considering the difference in conductivity type from that of the h transistor, the gate insulating films of the Nch transistor and the Pch transistor formed on the same substrate have the same gate insulating film as shown in FIG. Will be configured. In the gate insulating film having the above-described structure, during the operation of the transistor, electrons easily pass through the gate insulating film for the following reason. Therefore, there is a problem that the current (gate leak current) flowing through the gate electrode increases. In particular, the Nch transistor has a larger gate leak current than the Pch transistor.

FIGS. 11A and 11B are band diagrams when the Nch transistor and the Pch transistor are operating, respectively. Specifically, the potentials of the silicon substrate 110, the silicon oxide film 131, the high dielectric constant film 132, and the gate electrode 140 are shown. Nc
In the h transistor, as shown in FIG. 11A, electrons flow through the gate insulating film from the silicon substrate 110 toward the gate electrode 140. At this time, as shown in FIG. 11A, the potential of the silicon oxide film 131 serves as a barrier. Then, the electrons pass through the silicon oxide film 131 through the tunnel effect between the silicon substrate 110 and the gate electrode 140.

On the other hand, in the Pch transistor, as shown in FIG.
As shown in (b), electrons flow in the gate insulating film from the gate electrode 140 toward the silicon substrate 110. At this time, as shown in FIG. 11B, the silicon oxide film 13
1 and the potential of the high dielectric constant film 132 serve as a barrier.
Then, the electrons are transferred from the gate electrode 140 to the silicon substrate 1
Up to 10, the silicon oxide film 131 and the high dielectric constant film 132 are transmitted by the tunnel effect.

As described above, the distance through which electrons are transmitted by the Nch transistor due to the tunnel effect is shorter than the transmission distance by the Pch transistor. That is, the probability of electron transmission (tunnel) in the Nch transistor is higher than that in the Pch transistor. Therefore, Nc
The magnitude of the gate leakage current is different between the h transistor and the Pch transistor,
There is a problem that it is difficult to control the operation of the transistors with the same accuracy. Further, the Nch transistor has a problem that the gate leakage current is large and the power consumption efficiency is low.

Also in the technique disclosed in Japanese Patent Application Laid-Open No. 1-309380, similarly to the above, the structure of the gate insulating film is not set in consideration of the difference in conductivity type between the Nch transistor and the Pch transistor. Therefore, similarly to the above, there is a problem that it is difficult to control the operations of the Nch transistor and the Pch transistor with the same accuracy, because the magnitudes of the gate leakage currents differ between the Nch transistor and the Pch transistor. Therefore, an object of the present invention is to provide a semiconductor device that can efficiently consume power. Another object of the present invention is to provide a semiconductor device that can be controlled with substantially the same accuracy regardless of the conductivity type of the transistor. Another object of the present invention is to provide a method for manufacturing a semiconductor device capable of reducing a gate leak current flowing through a gate electrode of a transistor.

[0013]

In order to achieve the above object, a semiconductor device according to a first aspect of the present invention comprises a semiconductor substrate and a first substrate formed in a predetermined region on the semiconductor substrate .
A gate insulating film and a first gate insulating film formed on the first insulating film;
An N-channel type transistor including a first gate electrode and a first gate electrode formed in a predetermined region on the semiconductor substrate.
And a second gate insulating film and formed on the second gate insulating film.
And a second gate electrode, and a P-channel type transistor
And a first gate insulating film,
A first dielectric constant film formed in a predetermined region on the semiconductor substrate and having a predetermined dielectric constant; and a dielectric constant lower than the first dielectric constant film formed on the first dielectric constant film. Second
And a dielectric constant film, and the second gate insulating film is
Is formed in a predetermined region on the semiconductor substrate and has a predetermined dielectric constant
A third dielectric constant film having a refractive index and formed on the third dielectric constant film
And a fourth dielectric constant higher than the third dielectric constant film.
A dielectric film, Ru consists, characterized in that. According to this invention, the gate insulating film of the N-channel transistor is composed of two layers, the first dielectric constant film having a high relative dielectric constant is provided on the semiconductor substrate side, and the second dielectric constant film having a low relative dielectric constant is formed. By forming it on the gate electrode side, the gate leak current flowing through the gate electrode can be made smaller than in the conventional case.

[0014]

At least one of the first dielectric constant film and the fourth dielectric constant film may have a relative dielectric constant of 7.0 or more. The first dielectric constant film and the fourth dielectric constant film may be formed of the same material, and the second dielectric constant film and the third dielectric constant film may be formed of the same material.
The first gate electrode of the N-channel transistor further includes a fifth dielectric constant film having a relative dielectric constant lower than that of the first dielectric constant film between the semiconductor substrate and the first dielectric constant film. Good. The thickness of the fifth dielectric constant film is 1.5 nm.
It may be the following. The semiconductor substrate may be a silicon substrate, and the fifth dielectric constant film may be a silicon oxide film.

A semiconductor device according to a second aspect of the present invention is a semiconductor substrate, a first gate insulating film formed in a predetermined region on the semiconductor substrate, and a first gate insulating film formed on the first gate insulating film. A first conductivity type transistor including one gate electrode, a second gate insulating film formed in a predetermined region on the semiconductor substrate, and a second gate electrode formed on the second gate insulating film. , it is composed of a second conductivity type transistors including said first conductivity type tiger
The transistor is an N-channel type transistor,
1 gate insulating film is formed on the semiconductor substrate and has a predetermined thickness.
Dielectric constant film having a relative dielectric constant of, and the first dielectric constant film
Formed on top of the first dielectric constant film and has a lower dielectric constant than the first dielectric constant film.
And a second dielectric constant film for
The transistor is a P-channel type transistor, and
The second gate insulating film is formed on the semiconductor substrate,
A third dielectric constant film having a constant relative dielectric constant, and the third dielectric constant
Is formed on the film and has a higher relative dielectric constant than the third dielectric film.
A first dielectric constant film having a fourth dielectric constant film, and the first gate dielectric film and the second dielectric film have a distance by which electrons are transmitted through the first gate dielectric film by a tunnel effect during operation of a transistor. It is characterized in that a potential barrier is formed so that the distance through which it passes through the second gate insulating film is substantially equal. According to the present invention, since the distance through which the first gate insulating film penetrates and the distance through which the second gate insulating film penetrates are substantially equal to each other, the gate leakage current flowing through the gate electrode does not depend on the conductivity type of the transistor. Are substantially equal to each other, and the first and second conductivity type transistors can be controlled with the same accuracy.

[0017]

In a method of manufacturing a semiconductor device according to a third aspect of the present invention, a first dielectric constant film having a predetermined relative dielectric constant is formed on a semiconductor substrate in a region (PchTr formation region) where a P channel type transistor is formed. Forming a first dielectric constant film and forming a region (N
a second dielectric constant film forming step of forming a second dielectric constant film having a relative dielectric constant higher than that of the first dielectric constant film on the semiconductor substrate in the chTr formation region) and on the first dielectric constant film; N
a third dielectric constant film forming step of forming a third dielectric constant film having a relative dielectric constant lower than that of the second dielectric constant film on the second dielectric constant film of the chTr forming region; A conductive film forming step of forming a conductive film on the third dielectric constant film and the second dielectric constant film in the PchTr formation region, the first dielectric constant film, the second dielectric constant film, and the third dielectric film. And a patterning step of patterning the conductive film.

The second dielectric constant film forming step may include a step of forming an insulating film having a relative dielectric constant of 7.0 or more as the second dielectric constant film. The third dielectric film forming step may comprise the step of forming the third dielectric layer having a first dielectric constant film and the actual quality to the same dielectric constant. In the second dielectric constant film forming step, a fourth dielectric constant film forming step of forming a fourth dielectric constant film having a relative dielectric constant lower than that of the second dielectric constant film on the semiconductor substrate in the NchTr forming region. And after the fourth dielectric constant film forming step, the second dielectric constant film is formed.
A step of forming a dielectric constant film may be provided. The fourth dielectric constant film forming step may include a step of forming the fourth dielectric constant film having a thickness of 1.5 nm or less. The fourth dielectric constant film forming step may include a step of forming a silicon oxide film as the fourth dielectric constant film on the silicon semiconductor substrate.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a sectional view showing a configuration of a semiconductor device in which a gate electrode is formed by the manufacturing method according to the first embodiment. 1 (b) and FIG.
FIG. 1C is a diagram showing the configuration of the gate electrode shown in FIG. In the semiconductor device, for example, as shown in FIG. 1A, a semiconductor substrate 10 in which an N-channel type transistor (Nch Tr) and a P-channel type transistor (Pch Tr) are the same.
Is formed in.

The semiconductor substrate 10 is, for example, a p-type silicon substrate, and has a p-type diffusion layer and an n-type diffusion layer formed in a predetermined region. The Nch transistor and the Pch transistor are, for example, LOCOS (Local Oxidation of Sil).
They are separated by the element isolation insulating film 20 formed on the surface of the semiconductor substrate 10 by the icon method or the like. Nc
In each of the h transistor and the Pch transistor, the gate insulating film 30 is formed in a predetermined region on the semiconductor substrate 10, and the gate electrode 40 is formed on the gate insulating film 30.

Gate insulating film 30 of Nch transistor
Is formed of two layers as shown in FIG. Specifically, an insulating film (low dielectric constant film) 31 having a relatively low relative dielectric constant ε is formed on the gate electrode 40 side, and an insulating film (high dielectric constant film) having a relatively high relative dielectric constant ε is formed on the substrate side. 32 is formed. The low dielectric constant film 31 is, for example, a silicon oxide (SiO ₂ ) film having a thickness of about 1.5 nm, and the high dielectric constant film 32 is, for example, tantalum oxide (Ta ₂ O) having a thickness of about 6.0 nm. ₅ ) Membrane. The gate insulating film 30 of the Pch transistor is formed of two layers as shown in FIG. Specifically, the high dielectric constant film 32 is formed on the gate electrode 40 side, and the low dielectric constant film 31 is formed on the substrate side. That is, the structure of the gate insulating film 30 is reversed between the Pch transistor and the Nch transistor.

Next, a method of manufacturing the semiconductor device having the above structure will be described. 2A to 2F are cross-sectional views showing respective manufacturing steps of the semiconductor device. 2A to 2F, the drawings are simplified as much as possible for easy understanding. In the semiconductor substrate 10, a diffusion layer is previously formed in a predetermined region by an ion implantation method or the like, and an element isolation insulating film 20 is formed by a LOCOS method or the like. Further, the semiconductor substrate 10 has been previously subjected to heat treatment, peeling treatment, cleaning treatment, etc. necessary for forming a diffusion layer and an element isolation insulating film 20.

First, the semiconductor substrate 10 is subjected to heat treatment at 650 ° C. for 5 minutes in a dry oxygen atmosphere, for example, in a resistance heating type vertical diffusion furnace. As a result, as shown in FIG. 2A, the thermal oxide film 31a having a film thickness of about 1.5 nm, which becomes the low dielectric constant film 31 of the Pch transistor, is formed on the semiconductor substrate 1.
Form on 0. Next, the photoresist 1 is applied onto the thermal oxide film 31a, and by an exposure technique or the like, as shown in FIG.
The photoresist 1 is patterned so as to expose the Tr formation region). Then, as shown in FIG. 2B, the thermal oxide film 31a in the NchTr formation region is removed by, for example, an etching technique using an HF solution diluted with water.

Next, after removing the photoresist 1 and cleaning the surface, as shown in FIG. 2C, a tantalum oxide film 32a having a thickness of about 6.0 nm, which is a second insulating film, is formed. To do. This tantalum oxide film 32a is formed by, for example, mixing liquid pentaethoxytantalum and oxygen gas in a low pressure CVD (Chemical Vapor Deposition) furnace,
mTorr, 450 ° C. At this point, the tantalum oxide film 32a is in an amorphous state and not yet crystallized.

After forming the tantalum oxide film 32a, as shown in FIG.
As shown in (c), the third layer is formed on the tantalum oxide film 32a.
As an insulating film of HTO (High Tem
silicon oxide film 31 called a perature oxidation film
b is formed. The HTO film (silicon oxide film 31b) is
For example, it is formed in a low pressure CVD furnace. Specifically, Si
H _Four(Monosilane) and N_Two800 ° C. using O gas,
The HTO film is formed by heat treatment for 2 minutes. In addition,
This heat treatment forms a thin silicon oxide film 31b.
Both characteristics of the tantalum oxide film 32a formed in the previous step
It is done to make good. That is, by the above heat treatment
Oxygen, which tends to be insufficient in the low pressure CVD method, is oxidized by tantalum.
Amorphous tantalum oxide film supplied into the film
32a can be crystallized.

Next, a photoresist 2 is applied on the silicon oxide film 31b, and by an exposure technique or the like, as shown in FIG. 2D, a region (Pc) for forming a Pch transistor is formed.
Photoresist 2 so that the hTr formation region) is exposed.
Pattern. Then, as shown in FIG. 2D, the silicon oxide film 31b in the PchTr formation region is removed by an etching technique or the like. The removal of the silicon oxide film 31b is performed under the condition that the etching rate of the tantalum oxide film 32a is sufficiently slower than the etching rate of the silicon oxide film 31b.

After that, the photoresist 2 is peeled off and, if necessary, a cleaning process is performed, and then a material (for example, titanium nitride (TiN) or tungsten (W)) to be the gate electrode 40 is removed as shown in FIG. As shown in, the conductive film 40a is formed by depositing on the silicon oxide film 31b and the tantalum oxide film 32a. Then, as shown in FIG. 2F, the conductive film 40a, the silicon oxide film 31b, the tantalum oxide film 32a, and the thermal oxide film 31a are patterned by photolithography technique, etching technique, or the like to form the gate insulating film 30 and The gate electrode 40 is formed.

As described above, the semiconductor device (Nch transistor and Pch transistor) shown in FIG. 1 is completed. In the Nch transistor formed as described above, for example, as shown in FIG.
0 and the source are grounded. And + to the drain
A drain voltage Vd of 1.2 (V) and a gate voltage Vg of +1.5 (V) are applied to the gate electrode 40.

In the Pch transistor, the semiconductor substrate 10 and the source are grounded as shown in FIG. 3B, for example. Then, a drain voltage Vd of -1.2 (V) is applied to the drain, and a gate voltage Vg of -1.5 (V) is applied to the gate electrode 40. When the voltage is applied as described above, the Nch transistor and the Pch transistor operate. However, when the voltage is applied as described above, in the Nch transistor, electrons flow through the gate insulating film 30 from the semiconductor substrate 10 toward the gate electrode 40. On the other hand, in the Pch transistor, electrons flow through the gate insulating film 30 from the gate electrode 40 toward the semiconductor substrate 10. Note that FIG. 3A and FIG.
In (b), the direction of electron flow is indicated by an arrow.

The electron flow will be described below with reference to band diagrams. 4A and 4B respectively show N
It is a band diagram when the above-mentioned voltage is applied to each part of a ch transistor and a Pch transistor. Specifically, the semiconductor substrate 10, the gate insulating film 30, and
The potential of the gate electrode 40 is shown respectively.
As described above, in the Nch transistor, electrons flow in the gate insulating film 30 from the semiconductor substrate 10 toward the gate electrode 40. At this time, as shown in FIG. 4A, potential barriers of the high dielectric constant film 32 and the low dielectric constant film 31 exist between the semiconductor substrate 10 and the gate electrode 40. That is, the electrons are high dielectric constant film 32 and low dielectric constant film 31 between the semiconductor substrate 10 and the gate electrode 40.
Must pass through the potential barrier of by the tunnel effect.

In addition, in the Pch transistor, electrons move from the gate electrode 40 to the semiconductor substrate 1 in the gate insulating film 30.
It flows toward 0. Also in this case, as shown in FIG. 4B, potential barriers of the low dielectric constant film 31 and the high dielectric constant film 32 exist between the gate electrode 40 and the semiconductor substrate 10. That is, the electrons are high dielectric constant film 32 and low dielectric constant film 31 between the gate insulating film 40 and the semiconductor substrate 10.
Must pass through the potential barrier of by the tunnel effect.

As described above, by changing the structure of the gate insulating film 30 between the Nch transistor and the Pch transistor, the electron transmission distance becomes substantially equal between the Nch transistor and the Pch transistor.
Thereby, the operations of the Nch transistor and the Pch transistor can be stably controlled with the same accuracy.
Further, in the Nch transistor, electrons are generated in the gate insulating film 3
The potential barrier at the time of flowing 0 can be increased. That is, the probability of electron transmission (tunnel) can be reduced by changing the configuration of the gate insulating film 30 between the Nch transistor and the Pch transistor. That is, the current flowing through the gate electrode 40 (gate leak current)
Can be made smaller than before.

FIG. 5 shows a gate voltage V of an Nch transistor to which the present invention is applied and a conventional transistor.
It is a result of examining the gate leakage current Ig characteristic of the gate insulating film by applying g. As shown in FIG. 5, in the transistor to which the present invention is applied, the gate leakage current Ig in the low current region is smaller than that of the conventional transistor by two digits or more. From this, it is shown that the probability of electron transmission is reduced by configuring the gate insulating film 30 as described above.

In the region where the gate voltage Vg is 2.5 (V) or more, the magnitude of the gate leakage current Ig is almost the same between the conventional transistor and the transistor to which the present invention is applied. However, in a highly integrated device or the like in which the present invention is used, since the magnitude of the voltage applied to each part of the transistor is about 1.8 V at the maximum,
There is no particular problem. Further, in FIG. 5, the result for the Nch transistor is shown, but for the Pch transistor,
The electron transmission probability is as small as that of the Nch transistor.

Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 6A is a cross-sectional view showing a semiconductor device in which a gate electrode is formed by the manufacturing method according to the second embodiment. 6 (b) and 6 (c) are shown in FIG.
It is a figure which shows the structure of the gate electrode shown to (a). As shown in FIG. 6A, the semiconductor device has substantially the same configuration as the semiconductor device shown in the first embodiment. However, the structure of the gate insulating film 30 is different from that of the first embodiment.

Gate insulating film 30 of Nch transistor
Is composed of three layers, as shown in FIG. Specifically, in order from the gate electrode 40 side, a first insulating film (first low dielectric constant film) 33 having a relatively low relative dielectric constant ε,
Insulating film (high dielectric constant film) 34 having a relatively high relative permittivity ε, second insulating film (second low dielectric constant film) having a relatively low relative permittivity ε
35 is formed. The first low dielectric constant film 33 is
For example, silicon oxide (SiO ₂ ) with a thickness of about 1.5 nm
The high dielectric constant film 34 is a film and has a film thickness of, for example, about 6.0 n.
It is a tantalum oxide (Ta ₂ O ₅ ) film of m. Also, the second
The low dielectric constant film 35 is a silicon oxide (SiO ₂ ) film, and the film thickness thereof is the first low dielectric constant film 33 or the high dielectric constant film 36.
Thinner than that of the first low dielectric constant film 33.
It is half the thickness.

On the other hand, the gate insulating film 30 of the Pch transistor has substantially the same structure as that of the first embodiment, as shown in FIG. 6 (c). That is, the gate insulating film 30 of the Pch transistor is formed of two layers, and the gate electrode 4
The high-dielectric-constant film 34 is formed on the 0 side, and the relative dielectric constant ε is set on the substrate side.
The third insulating film (third low dielectric constant film) 36 having a relatively low temperature is formed. The third low dielectric constant film 36 is, for example, a silicon oxide (SiO ₂ ) film having a film thickness of 2.0 to 2.3 nm.

Next, a method of manufacturing the semiconductor device having the above structure will be described. 7A to 7F are cross-sectional views showing each manufacturing process of the semiconductor device. 7A to 7F, the drawings are simplified as much as possible for easy understanding. In the semiconductor substrate 10, a diffusion layer is previously formed in a predetermined region by an ion implantation method or the like, and an element isolation insulating film 20 is formed by a LOCOS method or the like. Further, the semiconductor substrate 10 has been previously subjected to heat treatment, peeling treatment, cleaning treatment, etc. necessary for forming a diffusion layer and an element isolation insulating film 20.

First, similarly to the first embodiment,
The thickness of the first insulating film on the semiconductor substrate 10 is about 1.5.
nm thermal oxide film 36a is formed. Then, similarly to the first embodiment, as shown in FIG.
The thermal oxide film 36a in the Tr formation region is removed. Then, the semiconductor substrate 10 is subjected to heat treatment at 650 ° C. for 2 minutes in a dry oxygen atmosphere in, for example, a resistance heating vertical diffusion furnace. As a result, as shown in FIG. 7B, the thin silicon oxide film 3 is formed on the semiconductor substrate 10 and the thermal oxide film 36a.
5a is formed. In the Pch transistor, the thermal oxide film 36a and the silicon oxide film 35a become the third low dielectric constant film 36.

Then, similarly to the first embodiment,
As shown in FIG. 7C, on the silicon oxide film 35a,
A tantalum oxide film 34a having a thickness of about 6.0 nm and a silicon oxide film 33a having a thickness of about 1.5 nm are formed in this order. After that, the photoresist 2 is applied on the silicon oxide film 33a, and the photoresist 2 is patterned by an exposure technique or the like so as to expose the PchTr formation region as shown in FIG. 7D.

Then, as shown in FIG.
As shown in (d), the silicon oxide film 33a in the PchTr formation region is removed. The removal of the silicon oxide film 33a is performed under the condition that the etching rate of the tantalum oxide film 34a is sufficiently slower than the etching rate of the silicon oxide film 33a. After that, the photoresist 2 is peeled off, and a cleaning process is performed if necessary. Then, as shown in FIG. 7E, the silicon oxide film 33a and the tantalum oxide film 34a are processed in the same manner as in the first embodiment. A conductive film 40a is formed on top.

Then, as shown in FIG. 7F, the conductive film 40a, the silicon oxide film 33a, and the tantalum oxide film 34 are formed by the photolithography technique or the etching technique.
The gate insulating film 30 and the gate electrode 40 are formed by patterning a, the silicon oxide film 35a, and the thermal oxide film 36a. As described above, the semiconductor device in the state shown in FIG. 6 (Nch transistor and Pch transistor)
To complete.

By forming the gate insulating film 30 with the above structure, the drain current of the Nch transistor during operation can be increased. This is an interface level formed at the interface between the semiconductor substrate 10 and the second low dielectric constant film 35 by forming a thin silicon oxide film (second low dielectric constant film) 35 on the silicon substrate (semiconductor substrate) 10. Is reduced. That is, the second low dielectric constant film (silicon oxide film) 3 is formed on the semiconductor substrate (silicon substrate) 10 side.
When 5 does not exist, there are many interface states between the semiconductor substrate 10 and the second low dielectric constant film 35, and it is difficult for the drain current to flow.

FIG. 8 shows the results of examining how the interface state changes depending on whether the second low dielectric constant film 35 is present in the gate insulating film 30 or not.
As shown in FIG. 8, the interface state when the second low dielectric constant film 35 is present in the gate insulating film 30 is smaller than when it is not present. From this, it was shown that by forming the gate insulating film 30 with three layers as described above, the drain current can be increased with the same applied voltage as compared with the case of forming it with two layers. That is, by forming the gate insulating film 30 of the Nch transistor from three layers, high speed operation of the device can be realized.

The silicon oxide film (second low dielectric constant film) 35 is formed on the silicon substrate (semiconductor substrate) 10 as described above.
Since it is formed on the side, the gate leakage current flowing through the gate electrode 40 is larger than that in the first embodiment. But,
As described above, the interface state between the gate insulating film 30 and the semiconductor substrate 10 can be reduced, and the magnitude of the gate leakage current is sufficiently smaller than that of the conventional one.

In the gate insulating film 30, if each insulating film is formed so that the relative permittivity is in the order shown above, the film forming conditions, the film forming apparatus, the material of the insulating film, etc. Other than the above may be used. For example, a thermal oxide film (silicon oxide film) 3
In the formation of 1a and 36a, the thermal oxide films 31a and 36a may be formed by subjecting the semiconductor substrate 10 to heat treatment at 800 ° C. for 10 seconds in a dry oxygen atmosphere in a rapid thermal processing furnace. Further, in forming the tantalum oxide films 32 and 34, a CVD method using TaCl ₅ or TaF ₅ may be used, or a sputtering method using Ta as a target may be used.

Further, in forming the silicon oxide films 31a and 33a, the HTO method or the deposition type oxide film growth method may be used. When a silicon oxide film (ε = 3.9) is used as the low dielectric constant insulating film, the same effect as above can be obtained by using a material having a relative dielectric constant of 7.0 or higher for the high dielectric constant insulating film. Can be obtained. An example of such a high dielectric constant insulating film is a silicon nitride film. The silicon nitride film is formed of SiH ₄ (or SiH ₂
CVD using Cl ₂ or SiCl ₄ ) gas and NH ₃ gas
Formed by the method.

The thin second low dielectric constant film 35 formed on the semiconductor substrate (silicon substrate) 10 side may be an oxynitride film containing nitrogen. Also in this case, as described above, good interface characteristics with the substrate, that is, low interface states can be obtained. In the second embodiment, in the Nch transistor, the thicknesses of the first low dielectric constant film 33 and the high dielectric constant film 34 are adjusted by the thickness of the second low dielectric constant film 35 to adjust the gate insulating film. The thickness of 30 may be substantially the same as that of the first embodiment.

In the first and second embodiments, in order to further suppress the gate leak current flowing through the gate electrode 40, the high dielectric constant films 32 and 34 are insulating films having a relative dielectric constant larger than that of the tantalum oxide film. May be used. For example, T
iO ₂ , BST (Ba, Sr, Ti, and an insulator containing O as a basic element), PZT (Pb, Zr, Ti, and
Insulator containing O as a main element) or aluminum oxide (Al ₂
An insulating film formed of O ₃ ) or the like may be used.

By using the above insulating film as the high dielectric constant film, the gate insulating film 30 can be made thick without deteriorating the electrical characteristics of the transistor. Further, by forming the gate insulating film 30 thick, the electron transmission probability can be made smaller than that in the above-described embodiment. For example, tantalum oxide film (ε =
When a BST film (ε = about 200) is used as the high dielectric constant film 32 instead of (about 25 to 45), the band diagram is
It becomes as shown in FIG. FIG. 9B is a band diagram of the Nch transistor shown in the first embodiment (see FIG.
It is similar to (a)) and is shown for comparison. Figure 9
As shown in (a), by making the BST film thick and making the gate insulating film 30 thick, the electron transmission distance becomes long. That is, the electron transmission probability is reduced, and the gate leak current flowing through the gate electrode 40 can be further reduced.

Also in the Pch transistor, the gate insulating film 30 can be formed thick by using the high dielectric constant insulating film as described above, and the leak current can be further reduced. The number of insulating films forming the gate insulating film 30 may be other than the above. However, as described above, the material and thickness of the insulating film must be set so that the potential barrier is formed between the semiconductor substrate 10 and the gate electrode 40 and the electron transmission probability is sufficiently reduced.

[0053]

As is apparent from the above description, according to the present invention, the distance through which electrons pass through the gate insulating film of the N-channel transistor can be made longer than before. As a result, the gate leak current flowing through the gate electrode can be made smaller than in the conventional case. Further, according to the present invention, the structure of the gate insulating film can be changed depending on the conductivity type of the transistor. Accordingly, the distances that electrons pass through the gate insulating film can be substantially equalized regardless of the conductivity type of the transistor. That is, the N-channel transistor and the P-channel transistor can be controlled with the same accuracy.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view showing each manufacturing process of the semiconductor device shown in FIG.

FIG. 3 is a diagram showing a voltage applied during operation of a transistor and a flow of electrons passing through a gate insulating film.

FIG. 4A is a band diagram of a gate insulating film forming an N-channel transistor. (B) is a band diagram of the gate insulating film which comprises a P-channel type transistor.

FIG. 5 is a diagram showing a difference between a current flowing through a gate electrode of a transistor to which the present invention is applied and a current flowing through a gate electrode of a conventional transistor.

FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment.

FIG. 7 is a cross-sectional view showing each manufacturing step of the semiconductor device shown in FIG.

FIG. 8 is a diagram showing a difference in interface state existing between a silicon substrate and a gate insulating film depending on the presence or absence of a thin silicon oxide film formed directly on the silicon substrate.

FIG. 9 is a band diagram showing a difference in electron transmission distance when an insulating film having a higher relative dielectric constant is used as a gate insulating film of an N-channel type transistor and the film thickness is increased.

FIG. 10 is a cross-sectional view showing each manufacturing process of a conventional semiconductor device.

FIG. 11 is a band diagram of a gate insulating film forming a conventional transistor.

[Explanation of symbols]

10 Semiconductor substrate 20 Insulation film for element isolation 30 Gate insulating film 31 Low dielectric constant film 31a Thermal oxide film 31b Silicon oxide film 32 High dielectric constant film 32a tantalum oxide film 33 First low dielectric constant film 33a Silicon oxide film 34 High dielectric constant film 34a tantalum oxide film 35 Second low dielectric constant film 35a Silicon oxide film 36 Third low dielectric constant film 36a thermal oxide film 40a conductive film 40 gate electrode

Front page continued (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336 H01L 27/06 H01L 27/08 H01L 27/088 H01L 27/092

Claims (13)

(57) [Claims] 1. A semiconductor substrate, Formed in a predetermined region on the semiconductor substrateFirstNo gate
Limbus and theFirstFormed on the gate insulating filmFirstGame
N-channel transistor composed of
When,A second gate is formed in a predetermined area on the semiconductor substrate.
An edge film and a second gate formed on the second gate insulating film.
P-channel transistor composed of
When, Consists of The aboveFirstThe gate insulating film is Is formed in a predetermined region on the semiconductor substrate and has a predetermined dielectric constant
A first dielectric constant film having a refractive index, Formed on the first dielectric constant film, and
A second dielectric constant film having a low relative dielectric constant, and, The second gate insulating film is Is formed in a predetermined region on the semiconductor substrate and has a predetermined dielectric constant
A third dielectric constant film having a refractive index, Formed on the third dielectric constant film, and
And a fourth dielectric constant film having a high relative dielectric constant.
The A semiconductor device characterized by the above. Wherein at least said one of the first dielectric constant film and the fourth dielectric constant film, the semiconductor device according to claim 1, characterized in that, with a 7.0 or more dielectric constant . 3. The first dielectric constant film and the fourth dielectric constant film are made of the same material, and the second dielectric constant film and the third dielectric constant film are made of the same material. The semiconductor device according to claim 1 or 2 , wherein: 4. A fifth dielectric constant between the semiconductor substrate and the first dielectric constant film, wherein the first gate electrode of the N-channel type transistor has a relative dielectric constant lower than that of the first dielectric constant film. further comprising a film, a semiconductor device according to any one of claims 1 to 3, characterized in that. 5. The semiconductor device according to claim 4 , wherein the fifth dielectric constant film has a thickness of 1.5 nm or less. Wherein said semiconductor substrate is a silicon substrate, the fifth dielectric constant film is a silicon oxide film, a semiconductor device according to claim 4 or 5, characterized in that. 7. A first substrate including a semiconductor substrate, a first gate insulating film formed in a predetermined region on the semiconductor substrate, and a first gate electrode formed on the first gate insulating film. A second conductivity type transistor including a conductivity type transistor, a second gate insulating film formed in a predetermined region on the semiconductor substrate, and a second gate electrode formed on the second gate insulating film. And the first conductivity type transistor is an N-channel type transistor.
A static, the first gate insulating film, is formed on the semiconductor substrate
And a first dielectric constant film having a predetermined relative dielectric constant and the first dielectric constant film.
Is formed on the dielectric constant film and has a lower dielectric constant than the first dielectric constant film.
A second dielectric constant film having a dielectric constant, and the second conductivity type transistor is a P-channel type transistor.
And a second gate insulating film formed on the semiconductor substrate.
And a third dielectric constant film having a predetermined dielectric constant, and the third dielectric constant film.
It is formed on the dielectric constant film and has a higher dielectric constant than the third dielectric constant film.
And a fourth dielectric constant film having a dielectric constant, wherein the first gate insulating film and the second gate insulating film are formed by electrons tunneling during operation of the transistor.
A semiconductor device, wherein a potential barrier is formed such that a distance passing through the first gate insulating film and a distance passing through the second gate insulating film are substantially equal to each other. 8. A first dielectric constant film forming step of forming a first dielectric constant film having a predetermined relative dielectric constant on a semiconductor substrate in a region for forming a P channel type transistor (PchTr forming region), and an N channel. Type transistor forming region (NchTr
Forming region) on the semiconductor substrate and on the first dielectric constant film,
A second dielectric constant film forming step of forming a second dielectric constant film having a relative dielectric constant higher than that of the first dielectric constant film, and the second dielectric constant film on the second dielectric constant film in the NchTr forming region. A third dielectric constant film forming step of forming a third dielectric constant film having a relative dielectric constant lower than that of the film, and the second dielectric constant film on the third dielectric constant film in the NchTr forming region and in the PchTr forming region. A conductive film forming step of forming a conductive film thereon; and a patterning step of patterning the first dielectric constant film, the second dielectric constant film, the third dielectric constant film, and the conductive film. A method for manufacturing a semiconductor device, comprising: Wherein said second dielectric film forming step includes a step of forming an insulating film having a dielectric constant of 7.0 or more as the second dielectric constant film, it to claim 8, wherein A method for manufacturing a semiconductor device as described above. 10. The third dielectric constant film forming step comprises:
The method of manufacturing a semiconductor device according to claim 8 or 9 comprising the step of forming the third dielectric constant film having a dielectric constant film and the actual quality to the same relative dielectric constant, characterized in that. 11. The fourth dielectric constant film forming step comprises: forming a fourth dielectric constant film having a relative dielectric constant lower than that of the second dielectric constant film on the semiconductor substrate in the NchTr forming region; comprising a dielectric film forming step, after the fourth dielectric film forming step comprises a step of forming the second dielectric constant film, according to any one of claims 8 to 10, characterized in that Manufacturing method of semiconductor device. 12. The semiconductor device according to claim 11 , wherein the fourth dielectric constant film forming step includes a step of forming the fourth dielectric constant film having a thickness of 1.5 nm or less. Production method. Wherein said fourth dielectric film forming step, the semiconductor substrate of silicon, according to claim 11 or 12 comprising forming a silicon oxide film as the fourth dielectric layer, characterized in that A method of manufacturing a semiconductor device according to item 1.