JPS6342173A - Manufacture of insulating gate type semiconductor device - Google Patents
Manufacture of insulating gate type semiconductor deviceInfo
- Publication number
- JPS6342173A JPS6342173A JP18575486A JP18575486A JPS6342173A JP S6342173 A JPS6342173 A JP S6342173A JP 18575486 A JP18575486 A JP 18575486A JP 18575486 A JP18575486 A JP 18575486A JP S6342173 A JPS6342173 A JP S6342173A
- Authority
- JP
- Japan
- Prior art keywords
- titanium nitride
- film
- gate
- nitride film
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000001020 plasma etching Methods 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 5
- 238000000992 sputter etching Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 abstract description 11
- 239000004020 conductor Substances 0.000 abstract description 10
- 230000006866 deterioration Effects 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 230000008569 process Effects 0.000 description 13
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- 229910018503 SF6 Inorganic materials 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 5
- 229960000909 sulfur hexafluoride Drugs 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000005755 formation reaction Methods 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- UNRFQJSWBQGLDR-UHFFFAOYSA-N methane trihydrofluoride Chemical compound C.F.F.F UNRFQJSWBQGLDR-UHFFFAOYSA-N 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
絶縁ゲートの形成に際して、ゲート絶縁膜上に窒化チタ
ン膜を形成した後ゲート電極用導電体層を形成し、該窒
化チタン膜をエッチングス）７パとして該導電体層のパ
ターンニングを行ってゲート電極を形成し、しかる後ゲ
ート電極の周辺に表出している用済みの窒化チタン膜を
除去する工程を含み、ゲート電極パターンニングに際し
てゲート近傍の基板面のダメージを防止し、素子性能の
劣化を防止する。[Detailed Description of the Invention] [Summary] When forming an insulated gate, a titanium nitride film is formed on the gate insulating film, a conductor layer for the gate electrode is formed, and the titanium nitride film is etched as a 7-layer film. The process includes patterning the conductor layer to form a gate electrode, and then removing the used titanium nitride film exposed around the gate electrode. This prevents damage to the device and prevents deterioration of device performance.
本発明は絶縁ゲート型半導体装置の製造方法の改良に係
り、特に薄いゲート絶縁膜を存する絶縁ゲートの形成方
法の改良に関する。The present invention relates to an improvement in a method for manufacturing an insulated gate type semiconductor device, and particularly to an improvement in a method for forming an insulated gate having a thin gate insulating film.
ＬＳＩ等高集積化される絶縁ゲート型半導体装置におい
ては、伝達コンダクタンスを高めて高速化を図るために
、ゲート絶縁膜が次第に薄くなる傾向にある。In insulated gate semiconductor devices that are highly integrated, such as LSIs, gate insulating films tend to become thinner and thinner in order to increase transfer conductance and achieve higher speeds.
一方、ゲート絶縁膜はゲート電極のパターンニングに際
してのりアクティブイオンエツチングのストッパとして
も機能するが、ゲート絶縁膜が極度に薄くなった場合、
該ゲート絶縁膜がストッパ機能を失って、ゲート電極の
パターンユング時にゲート近傍の基板面がダメージ等を
受け、素子性能が劣化する傾向を生ずる。On the other hand, the gate insulating film also functions as a stopper for active ion etching when patterning the gate electrode, but if the gate insulating film becomes extremely thin,
The gate insulating film loses its stopper function, and the substrate surface near the gate is damaged when the gate electrode is patterned, resulting in a tendency for device performance to deteriorate.
そこで基板面にダメージ等を与えることのない絶縁ゲー
トの形成方法が要望される。Therefore, there is a need for a method of forming an insulated gate that does not cause damage to the substrate surface.
近時、ＬＳＩ等においては高速化を図るために、配線抵
抗が減少できる高融点金属ゲートやポリサイドゲートが
用いられ、且つゲート絶縁膜の厚さが１００人程人程薄
く形成されるようになって来ている。Recently, in order to increase the speed of LSI etc., high-melting point metal gates and polycide gates that can reduce wiring resistance are being used, and the thickness of the gate insulating film has been made thinner by about 100 people. It's becoming.
かかる伏況において、従来絶縁ゲートを形成する際、以
下に第３図（ａ）〜（ｂｌを参照し例えばタングステン
（Ｗ）ゲートに付いて説明するような方法が用いられて
いた。Under such circumstances, conventionally, when forming an insulated gate, a method as described below with reference to FIGS. 3(a) to 3(bl), for example, for a tungsten (W) gate has been used.
第３図（ａｌ参照
即ち、先ずフィールド酸化膜２によって分離表出された
シリコン（Ｓｉ）基板１上に熱酸化により厚さ１００人
程人程ゲート二酸化シリコン（ＳｉＯｚ）膜３を形成し
た後、該基板上にスパッタリング法により厚さ２０００
人程度０Ｗ層５を形成する。Referring to FIG. 3 (al), first, a gate silicon dioxide (SiOz) film 3 with a thickness of about 100 layers is formed by thermal oxidation on a silicon (Si) substrate 1 isolated and exposed by a field oxide film 2. A thickness of 2000 mm was deposited on the substrate by sputtering.
A 0W layer 5 is formed.
第３図（ｂｌ参照
次いで上記Ｗ層５上にゲートパターンに対応するレート
パターン７を形成し、該レートパターン〃をマスクにし
、弗素系のエツチングガス例えば６弗化硫黄（ＳＦ６）
を用いてリアクティブイオンエツチング（ＲＩＥ）処理
を行う。この際パターンニングを完全にするために、エ
ツチングレートの面内分布や、ＷＪＷ５の厚さのばらつ
きを考慮して１０〜２０％程度のオーバエツチングがか
けられる。そして該選択エツチング処理により、ゲート
５ｉ０２膜３上にＷゲート電極１０５を形成する方法で
ある。FIG. 3 (see BL) Next, a rate pattern 7 corresponding to the gate pattern is formed on the W layer 5, and using the rate pattern as a mask, a fluorine-based etching gas such as sulfur hexafluoride (SF6) is used.
A reactive ion etching (RIE) process is performed using. At this time, in order to complete the patterning, overetching of about 10 to 20% is applied, taking into consideration the in-plane distribution of etching rate and the variation in the thickness of the WJW5. Then, by the selective etching process, a W gate electrode 105 is formed on the gate 5i02 film 3.
しかし上記従来方法においては、Ｗと５ｉＯ１とのエツ
チングレート比が６対１程度にしかとれないので、ゲー
ト５ｉ０２膜３が上記のように１００人程人程薄くなる
と、上記オーバエツチングに際してゲート５ｉ（ｈ膜３
完全に除去されて基板面がエツチングされる場所が生ず
る。However, in the conventional method described above, the etching rate ratio between W and 5iO1 is only about 6:1, so when the gate 5i02 film 3 becomes thinner by about 100 layers as described above, the gate 5i ( h membrane 3
There are locations where the substrate surface is completely removed and etched.
そのため、その場所の基板面がエツチングガスイオンの
衝撃を直に受けてダメージを受けたり、又該基板面にエ
ツチングガスのイオンが注入されたりして、その領域に
形成されるソース・ドレイよ
ン領域に接合耐圧低下や暗電流を生じ、これによって該
絶縁ゲート型半導体装置の性能や製造歩留りが低下する
という問題を生ずる。As a result, the substrate surface at that location may be damaged by direct impact from the etching gas ions, or the etching gas ions may be implanted into the substrate surface, resulting in source/drain formations being formed in that region. A reduction in junction breakdown voltage and a dark current occur in the region, resulting in a problem that the performance and manufacturing yield of the insulated gate semiconductor device are reduced.
本発明が解決しようとするのは、上記のように従来の方
法によれば、ゲート絶縁膜が極度に薄くなると、ゲート
電極パターンニングに際してのオーバエツチングを含ん
だ選択エツチングにおいて、ゲート絶縁膜がエツチング
ストッパの役目を完全に果たしきれなくなり、基板面に
形成されるダメージやガスイオンの注入によって、ソー
ス・ドレインの接合耐圧低下や暗電流を生じ、素子性能
や製造歩留りが低下するという問題である。The problem to be solved by the present invention is that, as described above, according to the conventional method, when the gate insulating film becomes extremely thin, the gate insulating film is etched during selective etching including overetching during gate electrode patterning. The problem is that the stopper cannot completely fulfill its role, and damage formed on the substrate surface and gas ion implantation cause a decrease in source-drain junction breakdown voltage and dark current, resulting in a decrease in device performance and manufacturing yield.
Ｃ問題点を解決するための手段〕
上記問題点は、絶縁ゲートの形成に際して、半導体基板
（１）上にゲート絶縁膜（３）を形成する工程と、該ゲ
ート絶縁膜（３）上に窒化チタン膜（４）を形成する工
程と、該窒化チタン膜（４）上にゲート電極の材料であ
る導電体層（５）を形成する工程と、該導電体層（５）
に対して優位な選択性を有するリアクティブイオンエツ
チング方法により該導電体層（５）の選択エツチングを
行って該導電体層（５）よりなるゲート電極パターン（
１０５）を形成する工程と、窒化チタンに対して優位な
選択性を有するリアクティブイオンエツチング方法によ
り該ゲート電極パターン（１０５）の周辺に表出してい
る窒化チタン膜（４）を除去する工程とを含む本発明に
よる絶縁ゲート型半導体装置の製造方法によって解決さ
れる。Means for Solving Problem C] The above problem is caused by the step of forming a gate insulating film (3) on the semiconductor substrate (1) and the step of forming a nitriding film on the gate insulating film (3) when forming an insulated gate. a step of forming a titanium film (4); a step of forming a conductor layer (5), which is a material for a gate electrode, on the titanium nitride film (4); and a step of forming a conductor layer (5), which is a material for a gate electrode.
The conductor layer (5) is selectively etched by a reactive ion etching method that has superior selectivity to
105), and a step of removing the titanium nitride film (4) exposed around the gate electrode pattern (105) using a reactive ion etching method that has superior selectivity to titanium nitride. The problem is solved by a method of manufacturing an insulated gate semiconductor device according to the present invention, which includes the following.
即ち本発明は、絶縁ゲートの形成に際してゲート絶縁膜
上に、ゲート電極のパターンニングに用いる弗素系のエ
ツチングガスに対して極度に低いエツチングレートを有
し、且つゲート電極の下部に残留した際に誘電体層の働
きをしないような高電導性を有する窒化チタン膜を形成
した後、該窒化チタン膜上にゲート電極用導電体層を形
成し、該窒化チタン膜をエツチングストッパとして該導
電体層のリアクティブイオンエツチング法によるパター
ンニングを行ってゲート電極を形成し、しかる後ゲート
電極の周辺に表出している用済みの窒化チタン膜を除去
し、ゲート絶縁膜上に窒化チタン膜を介してゲート電極
が配設された絶縁ゲートを形成する方法である。That is, the present invention has an extremely low etching rate with respect to a fluorine-based etching gas used for patterning a gate electrode on a gate insulating film when forming an insulated gate, and when remaining under the gate electrode. After forming a highly conductive titanium nitride film that does not function as a dielectric layer, a conductive layer for a gate electrode is formed on the titanium nitride film, and the conductive layer is used as an etching stopper. A gate electrode is formed by patterning using a reactive ion etching method, and then the used titanium nitride film exposed around the gate electrode is removed, and a titanium nitride film is formed on the gate insulating film via the titanium nitride film. This is a method of forming an insulated gate provided with a gate electrode.
そして本発明によれば、ゲート電極をパターンニングす
る際のりアクティブイオンエツチング処理において、上
記オーバエツチングを含んでパターンニングが完了する
まで、エツチングレートの極度に低い上記窒化チタン膜
によって完全に基板面をカバーして基板面のダメージ及
びガスイオン注入をなくし、これによってソース・ドレ
インの接合耐圧劣化や暗電流を防止する。According to the present invention, in the active ion etching process when patterning the gate electrode, the substrate surface is completely covered with the titanium nitride film having an extremely low etching rate until the patterning, including the overetching, is completed. Covering prevents damage to the substrate surface and gas ion implantation, thereby preventing source/drain junction breakdown voltage deterioration and dark current.
以下本発明を、図示実施例により具体的に説明する。 The present invention will be specifically explained below with reference to illustrated embodiments.
第１図（ａｌ〜（８１は本発明をＷ電極を有する絶縁ゲ
ート型半導体装置の製造に適用した第１の実施例の工程
断面図で、第２図（ａｌ〜（げ）はポリサイド電極を有
する絶縁ゲート型半導体装置の製造に適用した第２の実
施例の工程断面図である。Figure 1 (al ~ (81) is a process cross-sectional view of the first embodiment in which the present invention is applied to the manufacture of an insulated gate type semiconductor device having W electrodes, and Figure 2 (al ~ (81) is a process cross-sectional view of the first embodiment in which the present invention is applied to the manufacture of an insulated gate type semiconductor device having a W electrode. FIG. 4 is a process cross-sectional view of a second embodiment applied to manufacturing an insulated gate type semiconductor device having the structure shown in FIG.
全図を通じ同一対象物は同一符合で示す。Identical objects are indicated by the same reference numerals throughout the figures.
第１図（ａｌ参照
本発明を適用してＷ電極を有する絶縁ゲート型半導体装
置を形成するに際しては、通常の方法により例えばｐ型
Ｓｉ基Ｆｉ１の表面に、チャネルストッパ（図示せず）
を下部に有するフィールド酸化膜２を形成し、該シリコ
ン基板１の素子形成領域ＯＡを分離表出せしめる。When forming an insulated gate semiconductor device having a W electrode by applying the present invention to FIG.
A field oxide film 2 having a lower part of the field oxide film 2 is formed to separate and expose the element forming area OA of the silicon substrate 1.
次いで通常とおり熱酸化法により、上記素子形成領域０
４面に厚さ例えば１００人のゲートＳｉＯ□膜３を形成
する。Next, the above element formation area 0 is formed by thermal oxidation as usual.
A gate SiO□ film 3 having a thickness of, for example, 100 layers is formed on the four sides.
第１図（ｂｌ参照
次いで上記基板上にスパッタリング法により厚さ３００
人程０の窒化チタン（ＴｉＮ）膜４を形成し、次いで咳
ＴｉＮ膜４上にスパッタリング法により厚さ２０００人
程度０Ｗ層５を形成し、次いで該Ｗ膜５上に化学気相成
長（ＣＶＤ）法により厚さ１０００人程度０燐珪酸ガラ
ス（ＰＳＧ）膜６を形成する。FIG. 1 (see BL) Next, the above substrate was coated with a thickness of 300 mm by sputtering method.
A titanium nitride (TiN) film 4 with a thickness of 0 is formed, and then a 0W layer 5 with a thickness of approximately 2000 is formed on the TiN film 4 by sputtering, and then on the W film 5 by chemical vapor deposition (CVD). ) method to form a phosphosilicate glass (PSG) film 6 with a thickness of approximately 1000 mm.
第１図（Ｃ）参照
次いで通常のフォトプロセスにより上記ｐｓａ 膜６上
にゲートパターンに対応する形状のレジストパターン７
を形成した後、該レジストパターン７をマスクにし、５
０％４弗化炭素（ｃｐｓ）と５０％３弗化メタン（ＣＨ
Ｆ□）の混合ガスを用いてＰＳＧ膜６を、６弗化硫黄（
ＳＦ６）を用いてＷ層５を、リアクティブイオンエツチ
ング（Ｉ？ＩＥ）処理により続けてパターンニングする
。なおこの際、エツチングレートの面内分布、ＰＳＧ＠
６及びＷ層５の厚さの面内ばらつきを考慮して１０〜２
０％程度（Ｗ層のエツチング厚さに換算して２００〜４
００人程度）のオーバエツチングを行う。Referring to FIG. 1(C), a resist pattern 7 having a shape corresponding to the gate pattern is then formed on the PSA film 6 by a normal photo process.
After forming 5, use the resist pattern 7 as a mask and
0% carbon tetrafluoride (cps) and 50% methane trifluoride (CH
The PSG film 6 was coated using a mixed gas of sulfur hexafluoride (F□).
The W layer 5 is subsequently patterned using reactive ion etching (I?IE) using SF6). At this time, the in-plane distribution of etching rate, PSG@
6 and 10 to 2 considering in-plane variations in the thickness of the W layer 5.
Approximately 0% (converted to the etching thickness of the W layer: 200 to 4
00 people).
そしてこの際、ＴｉＮ膜４はエツチングストッパとして
機能するが、上記ＳＦ４等の弗素系ガスに対する該Ｔｉ
Ｎ膜４のエツチングレートは殆ど０に近いので、前記オ
ーバエツチング程度で該ＴｉＮ膜４が除去されてストッ
パ機能を失うことは絶対にない。At this time, the TiN film 4 functions as an etching stopper, but the TiN film 4 functions as an etching stopper.
Since the etching rate of the N film 4 is almost 0, the TiN film 4 is never removed by the above-mentioned overetching and will never lose its stopper function.
第１図（ｄ＋参照
次いで上記レジストパターン７をマスクにし、塩素系の
ガス例えば４塩化炭素（ＣＣ１＊）をエツチングガスに
用いるＲＩＥ処理により表出しているＴｉＮ膜４を選択
的に除去し、ゲートＳｉＯ□膜３上に下部にＴｉＮ層４
を介在し、上部にＰＳＧ膜６を有するするＷゲート電極
１０５を形成する。なお該ＣＣ１゜等の塩素系のガスに
よるＴｉＮとＳｉＯ□とのエツチングレートの比は５：
工程度であるので、１０〜２０％のオ−バエソチングで
ゲート５ｉ０２膜３が失われてシリコン基板１面が表出
されることはない。従って基板面にダメージやガスイオ
ン注入領域が形成されることはない。FIG. 1 (see d+) Next, using the resist pattern 7 as a mask, the exposed TiN film 4 is selectively removed by an RIE process using a chlorine gas such as carbon tetrachloride (CC1*) as an etching gas, and the exposed TiN film 4 is selectively removed. A TiN layer 4 is formed below on the SiO□ film 3.
A W gate electrode 105 having a PSG film 6 thereon is formed therebetween. The etching rate ratio of TiN and SiO□ using a chlorine-based gas such as CC1° is 5:
Since this is a process step, the gate 5i02 film 3 will not be lost and the silicon substrate 1 will not be exposed even with 10 to 20% over-etching. Therefore, no damage or gas ion implantation region is formed on the substrate surface.
第１図（ｅ）参照
次いでレジストパターン７を除去した後、上記ゲート電
極４に整合して素子形成領域ＯＡに例えば砒素（Ａｓ”
）を高濃度にイオン注入し、所要の活性化処理を行って
ｎ＋型ソース領域８及びドレイン９を形成する。なおこ
こでＰＳＧ膜６はゲート電極１０５構成するｗｌのチャ
ネリング減少を阻止するイオンのマスク膜となる。Referring to FIG. 1(e), after removing the resist pattern 7, for example, arsenic (As") is applied to the element forming area OA in alignment with the gate electrode 4.
) is ion-implanted at a high concentration and a necessary activation process is performed to form an n+ type source region 8 and drain 9. Here, the PSG film 6 serves as an ion mask film that prevents the channeling of wl forming the gate electrode 105 from decreasing.
以後図示しないが、絶縁膜の形成、絶縁膜へのコンタク
ト窓の形成、ソース・ドレイン配線の形成等がなされて
Ｗゲートを有する絶縁ゲート型半導体装置が完成する。Although not shown in the drawings, an insulating gate semiconductor device having a W gate is completed by forming an insulating film, forming a contact window to the insulating film, forming source/drain wiring, etc.
なお上記ゲート電極の下部にＴｉＮ膜の介在する構造に
おいて、闇値電圧（Ｖｔｈ）はＴｉＮの仕事関数に依存
するので、これに基づいてチャネルドーズ量を加減し、
これによってｖｔｈ値を制御する。In the structure in which a TiN film is interposed below the gate electrode, the dark voltage (Vth) depends on the work function of TiN, so the channel dose is adjusted based on this.
This controls the vth value.
次いでポリサイド電極を有する第２の実施例について説
明する。Next, a second embodiment having a polycide electrode will be described.
第２図（ａｌ参照
第１図（ａｌに示すようにゲート５ｉ０２膜３の形成を
終わったシリコン基板１上に、スパッタリング法により
例えば５００人程０のＴｉＮ膜４を形成し、次いで咳Ｔ
ｉＮ膜４上にＣＶＤ法により厚さ２０００人程度０ポリ
Ｓｉ層１０を形成し、次いで該ポリＳｉ層１０上にスパ
ッタリング法により厚さ２０００人程度０ポタンシリサ
イド（ＴｉＳｉｚ）層１１を形成する。As shown in FIG. 2 (al), on the silicon substrate 1 on which the gate 5i02 film 3 has been formed, for example, a TiN film 4 of about 500 layers is formed by a sputtering method, and then
A poly-Si layer 10 having a thickness of about 2,000 layers is formed on the iN film 4 by a CVD method, and then a polysilicide (TiSiz) layer 11 having a thickness of about 2,000 layers is formed on the poly-Si layer 10 by a sputtering method.
第２図（ｂ）参照
次いで第１の実施例同様、レジストパターン７をマスク
にし、ＳＦ６によるリアクティブイオンエツチング処理
によりＴｉＳｉｚ層１１、ポリＳｉ層１０を順次パター
ンニングする。この際前述したようにＴｉＮ膜４は殆ど
エツチングされない。Referring to FIG. 2(b), as in the first embodiment, the TiSiz layer 11 and the poly-Si layer 10 are sequentially patterned by reactive ion etching using SF6 using the resist pattern 7 as a mask. At this time, as mentioned above, the TiN film 4 is hardly etched.
第２図（訪）参照
次いで第１の実施例の第１図（ｄ）と同様に表出するＴ
ｉＮ膜４を除去し、ゲーｈｓｉＯ□膜３上に、下部にＴ
ｉＮ膜４が介在するポリＳｉ層１０とＴｉＳｉｚ層１１
との積層ゲート即ちＴｔＮを含むポリサイド電極１１１
を形成する。Referring to FIG. 2 (visited), T is then expressed in the same way as FIG.
The iN film 4 is removed, and a T layer is formed on the bottom of the gate hsiO□ film 3.
PolySi layer 10 and TiSiz layer 11 with iN film 4 interposed therebetween
A polycide electrode 111 containing a stacked gate, that is, TtN.
form.
第２図（ｄ）参照
次いでポリサイドゲート１１１をマスクにしてＡｓ”の
イオン注入を行ってｎ′″型ソース領域８及びドレイン
９を形成する。Referring to FIG. 2(d), next, using the polycide gate 111 as a mask, As" ions are implanted to form an n'" type source region 8 and drain 9.
そして以後図示しない絶縁膜の形成、コンタクト窓の形
成、ソース・ドレイン配線の形成等がなされてＴｉＮを
含むポリサイド電極を有する絶縁ゲート型半導体装置が
完成する。After that, an insulating film (not shown) is formed, a contact window is formed, source/drain wiring is formed, etc., and an insulated gate type semiconductor device having a polycide electrode containing TiN is completed.
以上実施例に示したように本発明の方法においては、ゲ
ート材料となる導電体に比べて極度にエツチングレート
の低いＴｉＮ膜をゲート絶縁膜とゲート電極層との間に
介在せしめることにより、ゲート電極層をゲート状にパ
ターンニングする際のオーバエツチングにより基板面が
エツチングされるのを防止する。As shown in the embodiments above, in the method of the present invention, a TiN film having an extremely low etching rate compared to the conductor serving as the gate material is interposed between the gate insulating film and the gate electrode layer. To prevent the substrate surface from being etched due to overetching when patterning the electrode layer into a gate shape.
従ってゲート近傍の基板面がエツチングのダメージ及び
ガス・イオンの注入を受けることがなくなり、該領域に
形成されるソース・ドレイン領域の接合耐圧低下や、暗
電流が防止される。Therefore, the substrate surface in the vicinity of the gate is not damaged by etching or gas ion implantation, and a decrease in the junction breakdown voltage and dark current of the source/drain regions formed in this region are prevented.
なお本発明の方法は上記実施例に限らず、多結晶シリコ
ンをゲート電極に用いる絶縁ゲート型半導体装置にも勿
論有効に適用される。Note that the method of the present invention is not limited to the above-mentioned embodiments, but can of course be effectively applied to insulated gate type semiconductor devices using polycrystalline silicon for the gate electrode.
以上説明のように本発明によれば、高集積化され且つ高
速化されてゲート絶縁膜が極度に薄く形成される絶縁ゲ
ート型半導体装置を製造する際のゲート電極のパターン
ニングに際して、ゲート近傍の基板面がエツチングガス
のイオンによりダメージを受ける２ことがなくなってｌ
ソース・ドレインの接合耐圧の劣化や暗電流の増大が防
止される。従って絶縁ゲート型半導体装置の性能及び製
造歩留りの向上が図れる。As described above, according to the present invention, when patterning a gate electrode when manufacturing an insulated gate type semiconductor device that is highly integrated and operates at high speed and has an extremely thin gate insulating film, it is possible to The substrate surface is no longer damaged by etching gas ions2.
Deterioration of source/drain junction breakdown voltage and increase in dark current are prevented. Therefore, the performance and manufacturing yield of the insulated gate semiconductor device can be improved.
第１図は本発明の第１の実施例の工程断面図、第２図は
本発明の第２の実施例の工程断面図、第３図は従来方法
の工程断面図である。
図において、
１はｐ型Ｓｉ基板、
２はフィールド酸化膜、
３はゲート５ｉｎ２膜、
４はＴｉＮ膜、
５はＷ層、
６はＰＳＧ膜、
７はレジストパターン、
８はｎ１型ソース領域、
９はｎ“型ドレイン領域、
１０はポリＳｉ層、
１１はＴｉＳｉ２層、
ＤＡは素子形成領域
を示す。
↓ ↓ １ ↓ ↓〜Ｓ７”６ＲＩＥＬ Ｌ
Ｌ Ｌ ） ！ ｒｓ’迩従永方法の工程
跡面馨
草３ 図FIG. 1 is a cross-sectional view of the process of the first embodiment of the present invention, FIG. 2 is a cross-sectional view of the process of the second embodiment of the present invention, and FIG. 3 is a cross-sectional view of the process of the conventional method. In the figure, 1 is a p-type Si substrate, 2 is a field oxide film, 3 is a gate 5in2 film, 4 is a TiN film, 5 is a W layer, 6 is a PSG film, 7 is a resist pattern, 8 is an n1-type source region, 9 indicates an n" type drain region, 10 indicates a poly-Si layer, 11 indicates a TiSi2 layer, and DA indicates an element formation area. ↓ ↓ 1 ↓ ↓〜S7"6RIEL L
LL)! Figure 3 of the process trace of the rs' Tokonei method
Claims (1)
程と、 該ゲート絶縁膜（３）上に窒化チタン膜（４）を形成す
る工程と、 該窒化チタン膜（４）上にゲート電極の材料である導電
体層（５）を形成する工程と、 該導電体層（５）に対して優位な選択性を有するリアク
ティブイオンエッチング方法により該導電体層（５）の
選択エッチングを行って該導電体（５）層よりなるゲー
ト電極パターン（１０５）を形成する工程と、 窒化チタン（４）に対して優位な選択性を有するリアク
ティブイオンエッチング方法により該ゲート電極パター
ン（１０５）の周辺に表出している窒化チタン膜（４）
を除去する工程とを含むことを特徴とする絶縁ゲート型
半導体装置の製造方法。[Claims] When forming an insulated gate, there are the steps of forming a gate insulating film (3) on a semiconductor substrate (1), and forming a titanium nitride film (4) on the gate insulating film (3). A step of forming a conductive layer (5), which is a material for a gate electrode, on the titanium nitride film (4), and a reactive ion etching method having superior selectivity to the conductive layer (5). selectively etching the conductive layer (5) to form a gate electrode pattern (105) made of the conductive layer (5); Titanium nitride film (4) exposed around the gate electrode pattern (105) by active ion etching method
1. A method of manufacturing an insulated gate semiconductor device, comprising the step of removing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18575486A JPS6342173A (en) | 1986-08-07 | 1986-08-07 | Manufacture of insulating gate type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18575486A JPS6342173A (en) | 1986-08-07 | 1986-08-07 | Manufacture of insulating gate type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6342173A true JPS6342173A (en) | 1988-02-23 |
Family
ID=16176280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18575486A Pending JPS6342173A (en) | 1986-08-07 | 1986-08-07 | Manufacture of insulating gate type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6342173A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5599725A (en) * | 1992-06-18 | 1997-02-04 | International Business Machines Corporation | Method for fabricating a MOS transistor with two-layer inverse-T tungsten gate structure |
| US5783478A (en) * | 1992-12-11 | 1998-07-21 | Intel Corporation | Method of frabricating a MOS transistor having a composite gate electrode |
| US6432776B1 (en) | 1999-08-23 | 2002-08-13 | Nec Corporation | Method of manufacturing semiconductor device |
| JP2004247414A (en) * | 2003-02-12 | 2004-09-02 | Sharp Corp | Transistor and its manufacturing method, and liquid crystal display device using the same |
-
1986
- 1986-08-07 JP JP18575486A patent/JPS6342173A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5599725A (en) * | 1992-06-18 | 1997-02-04 | International Business Machines Corporation | Method for fabricating a MOS transistor with two-layer inverse-T tungsten gate structure |
| US5783478A (en) * | 1992-12-11 | 1998-07-21 | Intel Corporation | Method of frabricating a MOS transistor having a composite gate electrode |
| US6432776B1 (en) | 1999-08-23 | 2002-08-13 | Nec Corporation | Method of manufacturing semiconductor device |
| JP2004247414A (en) * | 2003-02-12 | 2004-09-02 | Sharp Corp | Transistor and its manufacturing method, and liquid crystal display device using the same |
| JP4599603B2 (en) * | 2003-02-12 | 2010-12-15 | シャープ株式会社 | Method for manufacturing transistor |
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