JPH065852A - Mosfet and manufacture thereof - Google Patents
Mosfet and manufacture thereofInfo
- Publication number
- JPH065852A JPH065852A JP16500092A JP16500092A JPH065852A JP H065852 A JPH065852 A JP H065852A JP 16500092 A JP16500092 A JP 16500092A JP 16500092 A JP16500092 A JP 16500092A JP H065852 A JPH065852 A JP H065852A
- Authority
- JP
- Japan
- Prior art keywords
- film
- refractory metal
- metal film
- gate
- gate oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000000206 photolithography Methods 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 239000003870 refractory metal Substances 0.000 claims description 38
- 239000010410 layer Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000002344 surface layer Substances 0.000 claims description 2
- 238000001459 lithography Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 15
- 239000002184 metal Substances 0.000 abstract description 15
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052721 tungsten Inorganic materials 0.000 abstract description 13
- 239000010937 tungsten Substances 0.000 abstract description 13
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 11
- 238000002844 melting Methods 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 5
- 230000008018 melting Effects 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ゲート電極に高融点金
属を有するＭＯＳＦＥＴ及びその製造方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET having a gate electrode containing a refractory metal and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
例えば、以下に示すようなものがあった。図２はかかる
従来のＭＯＳＦＥＴの製造工程断面図である。なお、こ
のようなＭＯＳＦＥＴの製造方法は、現在ではＬＤＤ構
造などに広く応用され、その一例として、詳しくはＩＥ
ＤＭ’８３ Ｐ．３９２〜３９５に示されている。2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there were the following. FIG. 2 is a cross-sectional view of manufacturing steps of such a conventional MOSFET. It should be noted that such a method of manufacturing a MOSFET is now widely applied to LDD structures and the like.
DM'83 P.M. 392-395.
【０００３】まず、図２（ａ）に示すように、通常の選
択酸化法（ＬＯＣＯＳ法）により、シリコン単結晶半導
体基板（以下、基板という）１にフィールド酸化膜２を
形成し、アクティブ領域１１とフィールド領域１２を分
離する。次に、図２（ｂ）に示すように、トランジスタ
のゲート酸化膜３、及びゲート電極４を全面に形成した
後、ホトリソグラフィ技術によりパターニングを行い、
ゲート電極４を形成する。First, as shown in FIG. 2A, a field oxide film 2 is formed on a silicon single crystal semiconductor substrate (hereinafter referred to as a substrate) 1 by an ordinary selective oxidation method (LOCOS method), and an active region 11 is formed. And the field area 12 are separated. Next, as shown in FIG. 2B, after forming the gate oxide film 3 and the gate electrode 4 of the transistor on the entire surface, patterning is performed by the photolithography technique,
The gate electrode 4 is formed.
【０００４】次に、図２（ｃ）に示すように、ゲート電
極４をマスクとして、例えば、Ｎチャンネルトランジス
タの場合では、ヒ素の不純物をイオン注入することによ
り、基板１のソース／ドレイン形成領域の全体に自己整
合的に高濃度の不純物拡散層５を形成するようにしてい
る。Next, as shown in FIG. 2C, using the gate electrode 4 as a mask, for example, in the case of an N-channel transistor, arsenic impurities are ion-implanted to form source / drain formation regions of the substrate 1. The high-concentration impurity diffusion layer 5 is formed in a self-aligning manner over the entire area.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記し
た従来のＭＯＳＦＥＴでは、ゲート電極として使用する
材料によって以下のような問題点があった。まず、電極
材料として多結晶シリコン膜を使用した場合は、金属材
料に比べて比抵抗が高く、信号遅延が顕在化してくる。
また、低抵抗化のために多結晶シリコン膜上にタングス
テンやモリブデンのような高融点金属を形成するポリサ
イド構造を使用した場合でも、金属材料単体の場合に比
べて、数ケタも比抵抗が大きく、かつ表面チャネル型デ
バイスを実現する異極性ゲート電極方式をとろうとする
とプロセスが複雑になる。However, the above-mentioned conventional MOSFET has the following problems depending on the material used as the gate electrode. First, when a polycrystalline silicon film is used as the electrode material, the specific resistance is higher than that of the metal material, and the signal delay becomes apparent.
Even when a polycide structure in which a refractory metal such as tungsten or molybdenum is formed on the polycrystalline silicon film to reduce the resistance, the specific resistance is several orders of magnitude higher than that of the metal material alone. In addition, the process becomes complicated if a different polarity gate electrode method for realizing a surface channel device is adopted.
【０００６】更に進んで、高融点金属そのものをゲート
電極として用いる試みもなされているが、タングステン
などでは膜応力の大きいことによるゲート耐圧やホット
キャリア劣化現象が発生するなど、技術的に満足できる
ものは得られなかった。本発明は、以上述べたような問
題点を解決するために、表面チャネル型デバイスを実現
し、かつ、電極の配線抵抗が低く、しかも、ゲート耐圧
劣化等が抑制されるＭＯＳ特性を安定化することができ
るＭＯＳＦＥＴ及びその製造方法を提供することを目的
とする。Further attempts have been made to use a refractory metal itself as a gate electrode, but it is technically satisfactory that, for example, tungsten causes a gate breakdown voltage and a hot carrier deterioration phenomenon due to a large film stress. Was not obtained. In order to solve the above-mentioned problems, the present invention realizes a surface channel type device and stabilizes MOS characteristics in which the wiring resistance of electrodes is low and gate breakdown voltage deterioration is suppressed. It is an object of the present invention to provide a MOSFET that can be manufactured and a method for manufacturing the same.
【０００７】[0007]
【課題を解決するための手段】本発明は、上記目的を達
成するために、ＭＯＳＦＥＴにおいて、半導体基板と、
この半導体基板の表層に形成されたソース及びドレイン
領域と、このソース及びドレイン領域間の前記半導体基
板上に形成されたゲート酸化膜と、このゲート酸化膜上
に形成された第１の高融点金属膜と、この第１の高融点
金属膜上に形成され、かつ該第１の高融点金属膜とは相
反する応力をもつ第２の高融点金属膜とを設けるように
したものである。In order to achieve the above object, the present invention provides a MOSFET, a semiconductor substrate, and
Source and drain regions formed on the surface layer of the semiconductor substrate, a gate oxide film formed on the semiconductor substrate between the source and drain regions, and a first refractory metal formed on the gate oxide film. A film and a second refractory metal film formed on the first refractory metal film and having a stress opposite to that of the first refractory metal film are provided.
【０００８】また、ＭＯＳＦＥＴの製造方法において、
第１導電型の半導体基板あるいは半導体層のゲート形成
領域上にゲート酸化膜を形成し、このゲート酸化膜上に
第１の高融点金属膜を形成し、この第１の高融点金属膜
上に該第１の高融点金属膜とは相反する応力をもつ第２
の高融点金属膜を形成し、ホトリソグラフィ技術により
パターニングを行い、前記第１の高融点金属膜と前記第
２の高融点金属膜によりゲート電極を形成するようにし
たものである。In the method of manufacturing the MOSFET,
A gate oxide film is formed on a gate formation region of a semiconductor substrate of the first conductivity type or a semiconductor layer, a first refractory metal film is formed on the gate oxide film, and a first refractory metal film is formed on the first refractory metal film. The second refractory metal film having a stress opposite to that of the first refractory metal film
Of the high melting point metal film, and patterning is performed by photolithography technique to form a gate electrode by the first high melting point metal film and the second high melting point metal film.
【０００９】更に、第１導電型の半導体基板あるいは半
導体層のゲート形成領域上にゲート酸化膜を形成し、こ
のゲート酸化膜上に第１の高融点金属膜を形成し、この
第１の高融点金属膜上に該第１の高融点金属膜とは相反
する応力をもつ第２の高融点金属膜を形成し、この第２
の高融点金属膜上に反射防止膜を形成し、ホトリソグラ
フィ技術によりパターニングを行い、前記第１の高融点
金属膜、前記第２の高融点金属膜及び反射防止膜により
ゲート電極を形成するようにしたものである。Further, a gate oxide film is formed on the gate formation region of the semiconductor substrate of the first conductivity type or the semiconductor layer, and a first refractory metal film is formed on the gate oxide film. A second refractory metal film having a stress opposite to that of the first refractory metal film is formed on the melting point metal film.
An antireflection film is formed on the refractory metal film, and patterned by photolithography to form a gate electrode by the first refractory metal film, the second refractory metal film and the antireflection film. It is the one.
【００１０】[0010]
【作用】本発明によれば、ゲート電極材料として、高融
点金属を使用するとともに、その下部にパッド・メタル
として、更にもう一種類の別な相反する応力をもつ高融
点金属を併用する。したがって、ゲート酸化膜にかかる
応力が緩和され、ゲート耐圧やホットキャリアの劣化を
抑制することができる。According to the present invention, a refractory metal is used as the gate electrode material, and another kind of refractory metal having different stresses is also used as a pad metal thereunder. Therefore, the stress applied to the gate oxide film is relieved, and the gate breakdown voltage and hot carrier deterioration can be suppressed.
【００１１】しかも、ポリサイド構造ではなく、金属材
料のみでゲート電極を構成できるため、配線抵抗を低く
することができるだけでなく、表面チャネル型デバイス
の製造に対してもプロセスが簡単になる。Moreover, since the gate electrode can be formed only of a metal material instead of the polycide structure, not only the wiring resistance can be lowered, but also the process for manufacturing the surface channel type device is simplified.
【００１２】[0012]
【実施例】以下、本発明の実施例について図を参照しで
がら詳細に説明する。図１は本発明の実施例を示す半導
体装置の製造工程断面図である。まず、図１（ａ）に示
すように、シリコン単結晶半導体基板（以下、基板とい
う）１０１上に、図示しないがシリコン窒化膜を耐酸化
マスクとして用いる通常の選択酸化法（ＬＯＣＯＳ法）
により、フィールド酸化膜１０２（例えば、５０００
Å）を形成し、アクティブ領域７１とフィールド領域７
０を分離する。Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device manufacturing process showing an embodiment of the present invention. First, as shown in FIG. 1A, a normal selective oxidation method (LOCOS method) using a silicon nitride film (not shown) as an oxidation-resistant mask on a silicon single crystal semiconductor substrate (hereinafter referred to as a substrate) 101 is used.
Causes the field oxide film 102 (for example, 5000
Å) forming the active area 71 and the field area 7
Separate 0.
【００１３】次いで、アクティブ領域７１の基板１０１
上の表面に、熱酸化によってゲート酸化膜１０３（例え
ば、１００〜２００Å）を形成し、更にその上を含む全
面に、例えば圧縮応力をもつ窒化チタン膜１０４（５０
０〜１０００Å）をスパッタ法により形成する。次い
で、その上を含む全面に、例えば引張り応力をもつタン
グステン膜１０５（１０００〜２０００Å）をスパッタ
法あるいはＣＶＤ（化学的気相成長）法を用いて形成し
た後、更にその上を含む全面にＣＶＤ法により、酸化膜
１０６（例えば、５００Å）を形成する。Next, the substrate 101 in the active area 71
A gate oxide film 103 (for example, 100 to 200Å) is formed on the upper surface by thermal oxidation, and a titanium nitride film 104 (50 having a compressive stress) is formed on the entire surface including the gate oxide film 103.
0 to 1000Å) is formed by the sputtering method. Then, a tungsten film 105 (1000 to 2000 Å) having a tensile stress is formed on the entire surface including the upper portion by a sputtering method or a CVD (chemical vapor deposition) method, and then the entire surface including the upper portion is subjected to CVD. The oxide film 106 (for example, 500 Å) is formed by the method.
【００１４】次に、図１（ｂ）に示すように、ホトリソ
グラフィ技術により、図示しないがホトレジストをマス
クとして酸化膜１０６、タングステン膜１０５、窒化チ
タン膜１０４、ゲート酸化膜１０３をエッチングし、ゲ
ート電極１０７を形成する。レジスト除去後、図１
（ｃ）に示すように、酸化膜１０６をマスクとして、例
えばＮチャンネルトランジスタの場合、ヒ素などの不純
物をイオン注入法を用いて基板１０１に注入することに
より、基板１０１のソース／ドレイン形成領域中、ゲー
ト電極１０７に隣接する部分に自己整合的に高濃度不純
物拡散層１０８を形成する。ここで、酸化膜１０６はイ
オン注入時のマスクとなっているとともに、タングステ
ン膜１０５の反射率を低減する働きをしている。Next, as shown in FIG. 1B, the oxide film 106, the tungsten film 105, the titanium nitride film 104, and the gate oxide film 103 are etched by a photolithography technique using a photoresist (not shown) as a mask to etch the gate. The electrode 107 is formed. Figure 1 after removing the resist
As shown in (c), in the case of an N-channel transistor using the oxide film 106 as a mask, impurities such as arsenic are implanted into the substrate 101 by an ion implantation method, so that the source / drain formation region of the substrate 101 is formed. The high-concentration impurity diffusion layer 108 is formed in a self-aligned manner in a portion adjacent to the gate electrode 107. Here, the oxide film 106 serves as a mask during ion implantation and also serves to reduce the reflectance of the tungsten film 105.
【００１５】その後は、図示はしていないが、中間絶縁
膜、配線用金属パターン及び保護用絶縁膜を公知の技術
により形成し、各種構造のＭＯＳＦＥＴを完成させる。
図３は本発明の他の実施例を示す半導体装置の製造工程
断面図である。なお、前記した実施例と同様の部分につ
いては、同じ番号を付してその説明を省略する。Thereafter, although not shown, an intermediate insulating film, a wiring metal pattern and a protective insulating film are formed by a known technique to complete MOSFETs of various structures.
3A to 3D are cross-sectional views of manufacturing steps of a semiconductor device showing another embodiment of the present invention. The same parts as those in the above-described embodiment are designated by the same reference numerals and the description thereof will be omitted.
【００１６】まず、図３（ａ）に示すように、前記実施
例と同様に、基板１０１上にフィールド酸化膜１０２を
形成し、アクティブ領域７１とフィールド領域７０を分
離する。次に、アクティブ領域７１の基板１０１上の表
面に、熱酸化によってゲート酸化膜１０３を形成し、更
にその上を含む全面に、例えば圧縮応力をもつ窒化チタ
ン膜１０４をスパッタ法により形成する。First, as shown in FIG. 3A, a field oxide film 102 is formed on a substrate 101 to separate an active region 71 and a field region 70, as in the above-described embodiment. Next, a gate oxide film 103 is formed on the surface of the substrate 101 in the active region 71 by thermal oxidation, and a titanium nitride film 104 having, for example, compressive stress is formed by sputtering on the entire surface including the gate oxide film 103.
【００１７】次いで、更にその上を含む全面に、例えば
引張り応力をもつタングステン膜１０５をスパッタ法、
あるいはＣＶＤ（化学的気相成長）法を用いて形成す
る。更に、そのタングステン膜１０５上には全面にＣＶ
Ｄ法により、反射防止金属（ＡＲＭ：アンチ・リフレク
ト・メタル）膜２０１（例えば、窒化チタン膜）を形成
する。Then, a tungsten film 105 having a tensile stress, for example, is sputtered on the entire surface including the above,
Alternatively, it is formed by using a CVD (chemical vapor deposition) method. Further, CV is entirely formed on the tungsten film 105.
An antireflection metal (ARM: anti-reflect metal) film 201 (for example, a titanium nitride film) is formed by the D method.
【００１８】次に、図３（ｂ）に示すように、ホトリソ
グラフィ技術により、図示しないがホトレジストをマス
クとして反射防止金属膜２０１、タングステン膜１０
５、窒化チタン膜１０４、ゲート酸化膜１０３をエッチ
ングし、ゲート電極２０２を形成する。レジスト除去
後、図３（ｃ）に示すように、反射防止金属膜２０１を
マスクとして、例えばＮチャンネルトランジスタの場
合、ヒ素などの不純物をイオン注入法を用いて基板１０
１に注入することにより、基板１０１のソース／ドレイ
ン形成領域中、ゲート電極２０２に隣接する部分に自己
整合的に高濃度不純物拡散層１０８を形成する。ここ
で、反射防止金属膜２０１はイオン注入時のマスクとな
っているとともに、タングステン膜１０５の反射率を低
減する働きをしている。Next, as shown in FIG. 3B, the anti-reflection metal film 201 and the tungsten film 10 are formed by a photolithography technique using a photoresist (not shown) as a mask.
5, the titanium nitride film 104 and the gate oxide film 103 are etched to form a gate electrode 202. After removing the resist, as shown in FIG. 3C, using the antireflection metal film 201 as a mask, for example, in the case of an N-channel transistor, an impurity such as arsenic is used by ion implantation to form the substrate 10.
1 to form a high-concentration impurity diffusion layer 108 in a self-aligned manner in a region adjacent to the gate electrode 202 in the source / drain formation region of the substrate 101. Here, the antireflection metal film 201 serves as a mask during ion implantation and also serves to reduce the reflectance of the tungsten film 105.
【００１９】その後は、図示はしていないが、中間絶縁
膜、配線用金属パターン及び保護用絶縁膜を公知の技術
により形成し、各種構造のＭＯＳＦＥＴを完成させる。
なお、この実施例では、基板１０１に素子を形成するよ
うにしたが、この基板１０１上に半導体層を成長させ
て、その半導体層上に同様に素子を形成させるようにし
ても良いし、上記材料、寸法、形状、配置関係、数値的
条件またはその他の条件は、本発明の目的の範囲内で任
意に適宜な設計の変更及び変形を行うことができること
は言うまでもない。After that, although not shown, an intermediate insulating film, a metal pattern for wiring and a protective insulating film are formed by known techniques to complete MOSFETs of various structures.
Although the element is formed on the substrate 101 in this embodiment, a semiconductor layer may be grown on the substrate 101 and the element may be similarly formed on the semiconductor layer. It goes without saying that materials, dimensions, shapes, arrangement relationships, numerical conditions and other conditions can be arbitrarily modified and modified within the scope of the object of the present invention.
【００２０】[0020]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、ゲート電極材料として、引張り応力をもつタン
グステンと、圧縮応力をもつ窒化チタンを併用している
ため、ゲート酸化膜にかかる応力が緩和され、ゲート耐
圧やホットキャリアの劣化を抑制することができる。As described in detail above, according to the present invention, since tungsten having tensile stress and titanium nitride having compressive stress are used together as the gate electrode material, the gate oxide film is affected. Stress is relieved, and gate breakdown voltage and hot carrier deterioration can be suppressed.
【００２１】しかも、ポリサイド構造ではなく、金属材
料のみでゲート電極を構成できるため、配線抵抗を低く
することができるだけでなく、表面チャネル型デバイス
の製造に対してもプロセスが簡単になる。Moreover, since the gate electrode can be formed only of a metal material instead of the polycide structure, not only the wiring resistance can be lowered, but also the process for manufacturing the surface channel type device is simplified.
【図１】本発明の実施例を示す半導体装置の製造工程断
面図である。FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device showing an embodiment of the present invention.
【図２】従来の半導体装置の製造工程断面図である。FIG. 2 is a sectional view of a conventional semiconductor device manufacturing process.
【図３】本発明の他の実施例を示す半導体装置の製造工
程断面図である。FIG. 3 is a cross-sectional view of a manufacturing process of a semiconductor device showing another embodiment of the present invention.
７０ アクティブ領域 ７１ フィールド領域 １０１ シリコン単結晶半導体基板 １０２ フィールド酸化膜 １０３ ゲート酸化膜 １０４ 窒化チタン膜 １０５ タングステン膜 １０６ 酸化膜 １０７，２０２ ゲート電極 １０８ 高濃度不純物拡散層 ２０１ 反射防止（ＡＲＭ：アンチ・リフレクト・メ
タル）膜70 Active Region 71 Field Region 101 Silicon Single Crystal Semiconductor Substrate 102 Field Oxide Film 103 Gate Oxide Film 104 Titanium Nitride Film 105 Tungsten Film 106 Oxide Film 107, 202 Gate Electrode 108 High Concentration Impurity Diffusion Layer 201 Antireflection (ARM: Anti Reflect・ Metal) film
Claims (3)
イン領域と、 （ｃ）該ソース及びドレイン領域間の前記半導体基板上
に形成されたゲート酸化膜と、 （ｄ）該ゲート酸化膜上に形成された第１の高融点金属
膜と、 （ｅ）該第１の高融点金属膜上に形成され、かつ該第１
の高融点金属膜とは相反する応力をもつ第２の高融点金
属膜とを具備することを特徴とするＭＯＳＦＥＴ。1. A semiconductor substrate comprising: (a) a semiconductor substrate; (b) a source and drain region formed on a surface layer of the semiconductor substrate; and (c) a gate oxide formed on the semiconductor substrate between the source and drain regions. A film, (d) a first refractory metal film formed on the gate oxide film, (e) a first refractory metal film formed on the first refractory metal film, and
MOSFET having a second refractory metal film having a stress opposite to that of the refractory metal film of FIG.
導体層のゲート形成領域上にゲート酸化膜を形成する工
程と、 （ｂ）該ゲート酸化膜上に第１の高融点金属膜を形成す
る工程と、 （ｃ）該第１の高融点金属膜上に該第１の高融点金属膜
とは相反する応力をもつ第２の高融点金属膜を形成する
工程と、 （ｄ）ホトリソグラフィ技術によりパターニングを行
い、前記第１の高融点金属膜と前記第２の高融点金属膜
によりゲート電極を形成する工程を施すことを特徴とす
るＭＯＳＦＥＴの製造方法。2. A step of: (a) forming a gate oxide film on a gate formation region of a first conductivity type semiconductor substrate or semiconductor layer; and (b) forming a first refractory metal film on the gate oxide film. Forming step, (c) forming a second refractory metal film having stress opposite to that of the first refractory metal film on the first refractory metal film, and (d) photo A method for manufacturing a MOSFET, which comprises performing patterning by a lithography technique and performing a step of forming a gate electrode with the first refractory metal film and the second refractory metal film.
導体層のゲート形成領域上にゲート酸化膜を形成する工
程と、 （ｂ）該ゲート酸化膜上に第１の高融点金属膜を形成す
る工程と、 （ｃ）該第１の高融点金属膜上に該第１の高融点金属膜
とは相反する応力をもつ第２の高融点金属膜を形成する
工程と、 （ｄ）該第２の高融点金属膜上に反射防止膜を形成する
工程と、 （ｅ）ホトリソグラフィ技術によりパターニングを行
い、前記第１の高融点金属膜、前記第２の高融点金属膜
及び反射防止膜によりゲート電極を形成する工程を施す
ことを特徴とするＭＯＳＦＥＴの製造方法。3. A step of forming a gate oxide film on a gate formation region of a first conductivity type semiconductor substrate or a semiconductor layer, and (b) a first refractory metal film on the gate oxide film. And (c) forming a second refractory metal film having a stress opposite to that of the first refractory metal film on the first refractory metal film, and (d) A step of forming an antireflection film on the second refractory metal film, and (e) patterning by a photolithography technique to form the first refractory metal film, the second refractory metal film and the antireflection film. A method of manufacturing a MOSFET, characterized in that the step of forming a gate electrode is carried out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16500092A JPH065852A (en) | 1992-06-23 | 1992-06-23 | Mosfet and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16500092A JPH065852A (en) | 1992-06-23 | 1992-06-23 | Mosfet and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH065852A true JPH065852A (en) | 1994-01-14 |
Family
ID=15803945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16500092A Withdrawn JPH065852A (en) | 1992-06-23 | 1992-06-23 | Mosfet and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH065852A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2757312A1 (en) * | 1996-12-16 | 1998-06-19 | Commissariat Energie Atomique | SELF-ALIGNED METAL GRID TRANSISTOR AND MANUFACTURING METHOD THEREOF |
| KR19980060616A (en) * | 1996-12-31 | 1998-10-07 | 김영환 | Gate electrode of semiconductor device |
| EP0973189A2 (en) * | 1998-07-15 | 2000-01-19 | Texas Instruments Incorporated | A method for gate-stack formation including a high-K dielectric |
| US6483151B2 (en) | 2000-01-21 | 2002-11-19 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| KR100589865B1 (en) * | 1997-03-31 | 2006-09-20 | 프리스케일 세미컨덕터, 인크. | Semiconductor device and a process for forming the device |
| US7157359B2 (en) | 2000-12-29 | 2007-01-02 | Hynix Semiconductor Inc. | Method of forming a metal gate in a semiconductor device using atomic layer deposition process |
| EP1786037A2 (en) * | 1999-04-12 | 2007-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
-
1992
- 1992-06-23 JP JP16500092A patent/JPH065852A/en not_active Withdrawn
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001506807A (en) * | 1996-12-16 | 2001-05-22 | コミツサリア タ レネルジー アトミーク | MIS transistor with self-aligned metal grid and manufacturing process thereof |
| WO1998027582A1 (en) * | 1996-12-16 | 1998-06-25 | Commissariat A L'energie Atomique | Mis transistor with self-aligned metal grid and method for making it |
| FR2757312A1 (en) * | 1996-12-16 | 1998-06-19 | Commissariat Energie Atomique | SELF-ALIGNED METAL GRID TRANSISTOR AND MANUFACTURING METHOD THEREOF |
| KR19980060616A (en) * | 1996-12-31 | 1998-10-07 | 김영환 | Gate electrode of semiconductor device |
| KR100589865B1 (en) * | 1997-03-31 | 2006-09-20 | 프리스케일 세미컨덕터, 인크. | Semiconductor device and a process for forming the device |
| EP0973189A2 (en) * | 1998-07-15 | 2000-01-19 | Texas Instruments Incorporated | A method for gate-stack formation including a high-K dielectric |
| EP0973189A3 (en) * | 1998-07-15 | 2000-12-20 | Texas Instruments Incorporated | A method for gate-stack formation including a high-K dielectric |
| EP1786037A2 (en) * | 1999-04-12 | 2007-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| EP1786037A3 (en) * | 1999-04-12 | 2012-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6483151B2 (en) | 2000-01-21 | 2002-11-19 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| KR100443475B1 (en) * | 2000-01-21 | 2004-08-09 | 닛뽄덴끼 가부시끼가이샤 | Semiconductor device and method of manufacturing the same |
| US6916695B2 (en) | 2000-01-21 | 2005-07-12 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| US7157359B2 (en) | 2000-12-29 | 2007-01-02 | Hynix Semiconductor Inc. | Method of forming a metal gate in a semiconductor device using atomic layer deposition process |
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