JPH065854A - Semiconductor device and its production - Google Patents

Abstract

PURPOSE:To suppress the contact resistance to an electrode by forming a protruding part composed of a semiconductor layer which contains impurities on at least one part of a part on which impurity diffused layer such as an MIS type transistor source and a drain is to be formed. CONSTITUTION:A semiconductor device is provided with a silicon substrate 1, a field oxide film 2, a gate silicon oxide film 3, a gate electrode polycrystalline silicon layer 4, a surface protecting silicon oxide film 5, a side wall protecting silicon oxide film 6 and an LDD structure low concentration impurity ion implanting layer 7. As for a semiconductor layer protruding part 8, the impurity composed of polycrystalline silicon layer or a single crystal silicon layer formed on the source and drain is introduced. The contact area of the semiconductor layer protruding part 8 with the source and the drain is permitted to be larger by the side wall areas of the protruding part and the diffused layer area and the diffusion resistance of the silicon substrate 1 are reduced. Thus, integration and operation speed are improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method. More specifically, the present invention relates to a diffusion layer structure of an LSI having a diffusion layer such as a source and a drain of a MIS transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, when forming a MIS transistor on a semiconductor substrate, the MI from the surface of the semiconductor substrate
It has been customary to form an impurity diffusion layer such as the source or drain of an S-type transistor.

[0003]

According to the above-mentioned prior art, there is a problem that the width of the diffusion layer is reduced along with the miniaturization of the LSI, and the contact resistance with the electrode is increased, and the circuit speed of the LSI is reduced. It was

An object of the present invention is to solve the problems of the prior art and to provide a new diffusion layer structure and a method for producing the same, which does not increase the contact resistance with the electrode even if the width of the diffusion layer is reduced. To do.

[0005]

In order to solve the above problems and to achieve the above objects, the present invention relates to a semiconductor device and a method for manufacturing the same. (1) In forming a MIS transistor on a semiconductor substrate, the above semiconductor substrate Means for forming a convex portion formed of a semiconductor layer containing an impurity in at least a part of a portion of the surface where an impurity diffusion layer such as a source or drain of the MIS transistor is to be formed, and (2) semiconductor Means for forming a semiconductor layer convex portion on a portion of the substrate surface where a diffusion layer of the MIS transistor is to be formed, and (3) MI on the semiconductor substrate surface
A semiconductor device, wherein a semiconductor layer convex portion is formed in a portion where a diffusion layer of an S-type transistor is to be formed, and the semiconductor layer convex portion is formed of a semiconductor layer containing impurities, wherein the semiconductor layer convex portion is a polycrystalline layer. Or take some means to form a single crystal layer,
And (4) a semiconductor device in which a semiconductor layer convex portion is formed on a portion of the surface of the semiconductor substrate where a diffusion layer of the MIS transistor is to be formed, and the semiconductor layer convex portion is formed of a semiconductor layer containing impurities. A means for forming and forming an electrode made of silicide, nitride, metal or alloy on the surface of the semiconductor layer convex portion is taken.

[0006]

Embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a sectional view of a main part of a MOS transistor showing an embodiment of the present invention. In the figure, reference numeral 1 denotes a silicon substrate, on which a silicon gate MOS type transistor is provided, and convex portions 8 made of a semiconductor layer are provided on the source and drain portions. 2 is a field silicon oxide film, 3 is a gate silicon oxide film, 4
Is a polycrystalline silicon layer for a gate electrode, 5 is a surface protective silicon oxide film, 6 is a sidewall protective silicon oxide film, 7 is a low-concentration impurity ion implantation layer having an L _DD structure, and 8 is a polycrystalline film formed in the source and drain portions. It is a semiconductor layer convex portion into which impurities are introduced, which is made of a silicon layer or a single crystal silicon layer. The semiconductor layer convex portion 8 may be formed not only on the substrate surface but also on the surface of the silicon oxide films 2, 6 and 5.

The semiconductor layer convex portions provided on the source and drain portions of this MOS transistor are regions provided on the main portion of the impurity diffusion regions such as the source and drain of the silicon substrate 1. Therefore, the contact area is larger than the conventional contact area having no convex portion of this kind of semiconductor layer by the convex side wall area. The area of the diffusion layer in the silicon substrate 1 can be reduced by the area, and
The diffusion layer resistance can be made small.

Next, the manufacturing method of the MOS LSI according to the present invention will be described in the order of steps.

(A) LOCOS is formed on the surface of the silicon substrate 1.
Forming a thick field silicon oxide film 2 by the method, and the oxidation resistant silicon nitride film which was previously formed in the element active region and remained by photoetching, and the silicon oxide film formed as a buffer layer under the silicon nitride film. The film is removed by dry etching or chemical etching.

(A) The surface of the silicon substrate 1 on which a MOS transistor is to be formed is thermally oxidized to form a gate silicon oxide film 3 of about 15 nm. Then, a polycrystalline silicon layer 4 for a gate electrode having a thickness of about 400 nm is formed by the CVD method, and a gate electrode is formed by photoetching.

(C) Polycrystalline silicon layer 4 for gate electrode
Then, the surface of the silicon substrate 1 is thermally oxidized to form a surface protective silicon oxide film 5 of about 100 nm. Then, CVD
A silicon oxide film of about 500 nm is formed by the method.
This is removed by dry etching, leaving the side wall protective silicon oxide film 6 and the surface protective silicon oxide film 5.

Next, the low-concentration impurity ion-implanted layer 7
To form an L _DD structure.

(D) By selective growth using the field silicon oxide film 2, the side wall protective silicon oxide film 6, the surface protective silicon oxide film 5, etc. as a mask, a CVD method and an epitaxial method are applied to a source region and a drain region, etc., which are conventionally diffusion layers. The semiconductor film is partially formed by the method, or the semiconductor film is formed on the entire surface by the CVD method and the epitaxial method and photoetched to form a square, inverted U-shaped or trapezoidal semiconductor layer convex portion. It is desirable that the height of the convex portion is 1 to 2 times or more the minimum width of the diffusion region. As the semiconductor layer convex portion 8, a polycrystalline silicon film or a single crystal silicon film is formed at least on the surface of the diffusion layer region by a CVD method or an epitaxial method, and impurities are introduced into the formed semiconductor layer in advance or by ion implantation or the like. Then, diffusion regions such as a source and a drain are formed.

FIG. 2 is a MOS showing another embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a transistor of the shape.

In the figure, reference numeral 11 denotes a silicon substrate on which a silicon gate MOS type transistor is provided, and semiconductor layer convex portions 18 are provided on the source and drain portions. 12 is a field silicon oxide film, 13 is a gate silicon oxide film, 14 is a polycrystalline silicon layer for gate electrodes, 15 is a surface protective silicon oxide film, 1
6 is a sidewall protection silicon oxide film, 17 is a low-concentration impurity ion-implanted layer, 18 is a semiconductor in which impurities such as a polycrystalline silicon layer or a single crystal silicon layer formed on the surface of the diffusion region are introduced into the source and drain portions. It is a layer convex portion. A conductive layer 19 made of a titanium nitride film, a silicide film, a metal film or an alloy film is formed on the surface of the semiconductor layer convex portion 18. The semiconductor layer convex portion 18 and the conductive layer 19 are formed not only on the surface of the groove portion but also on the silicon oxide film 1.
It may be formed to extend to the surfaces of 2, 16 and 15.

The convex portions provided on the source and drain portions of this MOS transistor are regions provided on the main portion of the impurity diffusion region such as the source and drain of the silicon substrate 11. Therefore, its contact area is
Since the protrusion side wall area is larger than the conventional contact area having no protrusions of this kind, in order to obtain the same contact area, the diffusion layer in the silicon substrate 11 corresponding to the protrusion side wall area is obtained. The region can be made small and the diffusion layer resistance can be made even smaller.

As described above, the LSI of the MOS transistor according to the present invention can be formed by diverting the manufacturing process for forming the silicon gate MOS transistor with the L _DD structure. In addition, when providing a convex portion on the silicon substrate 1 or 11 in the diffusion region, ion convexity or plasma etching is performed to form a convex portion whose side wall surface is substantially perpendicular to the convex surface. It can be formed high. Therefore, it is possible to easily provide a convex portion having a large side wall area in a small area of the silicon substrate 1 or 11. Therefore, a diffusion layer having a desired resistance value can be provided on the silicon substrate 1 or 11 with a small area. Therefore, L incorporating this type of diffusion layer
SI is fast and highly integrated.

Although the above-described embodiments of the present invention are LSIs having silicon gate MOS type transistors as main elements, the present invention can be applied to various semiconductor devices having bipolar transistors or MIS type transistors as main elements.

[0020]

According to the present invention, a diffusion layer having a desired low resistance value can be provided on a silicon substrate with a small area. Therefore, an LSI incorporating this type of diffusion layer has high speed and high integration. There is an effect that can be achieved.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of a MOS transistor showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view of an essential part of a MOS transistor showing another embodiment of the present invention.

[Explanation of symbols]

 1, 11 ... Semiconductor substrate 2, 12 ... Field silicon oxide film 3, 13 ... Gate silicon oxide film 4, 14 ... Polysilicon layer for gate electrode 5, 15 ... Surface protection oxidation Silicon film 6, 16 ... Side wall protection silicon oxide film 7, 17 ... Low-concentration impurity ion implantation layer 8, 18 ... Semiconductor layer convex portion 19 ... Conductive layer

Claims (4)

[Claims] 1. When forming a MIS transistor on a semiconductor substrate, impurities are contained in at least a portion of a portion of the surface of the semiconductor substrate where an impurity diffusion layer such as a source or drain of the MIS transistor is to be formed. A semiconductor device having a convex portion formed of a semiconductor layer. 2. A method of manufacturing a semiconductor device, wherein a semiconductor layer protrusion is formed on a portion of a semiconductor substrate surface where a diffusion layer of a MIS transistor is to be formed, wherein the semiconductor layer protrusion is formed by dry etching. Manufacturing method of semiconductor device. 3. A semiconductor device comprising a semiconductor layer convex portion formed on a surface of a semiconductor substrate where a diffusion layer of a MIS transistor is to be formed, the semiconductor layer convex portion being formed of a semiconductor layer containing impurities. A semiconductor device characterized in that the convex portion of the semiconductor layer is formed as a polycrystalline layer or a single crystal layer. 4. A semiconductor device comprising a semiconductor layer convex portion formed on a surface of a semiconductor substrate where a diffusion layer of a MIS transistor is to be formed, and the semiconductor layer convex portion is formed of a semiconductor layer containing impurities. A semiconductor device characterized in that an electrode made of a silicide, a nitride, a metal or an alloy is formed on the surface of the convex portion of the semiconductor layer.