JPH04129274A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04129274A
JPH04129274A JP2250597A JP25059790A JPH04129274A JP H04129274 A JPH04129274 A JP H04129274A JP 2250597 A JP2250597 A JP 2250597A JP 25059790 A JP25059790 A JP 25059790A JP H04129274 A JPH04129274 A JP H04129274A
Authority
JP
Japan
Prior art keywords
layer
selectively
drain
become
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2250597A
Other languages
Japanese (ja)
Inventor
Yasushi Miyajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP2250597A priority Critical patent/JPH04129274A/en
Publication of JPH04129274A publication Critical patent/JPH04129274A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent a short channel effect by forming either a source or a drain of a MOS transistor formed on a semiconductor substrate in an epitaxially selectively grown layer, thereby increasing a channel length in the case of a miniaturization of an element.
CONSTITUTION: A silicon oxide film 2 is formed on a semiconductor substrate 1, opposite conductivity type impurity ions are selectively implanted to form a diffused layer region 3 to become a source. Then, the film 2 is selectively etched, and an epitaxially selectively grown layer 6 is formed on the part. Thereafter, after the film 2 is formed by a thermal oxidation method, a polycrystalline silicon layer 7 is deposited on the entire surface, selectively etched to form an opening for forming a diffused layer region 4 to become a drain. Subsequently, with the layer 6 as a mask the opposite conductivity type impurity ions are implanted into the layer 6 to form the region 4 to become the drain. Then, the layer 7 is selectively etched to form a gate electrode 5, and a semiconductor device having a transistor in which its channel length L is increased is composed.
COPYRIGHT: (C)1992,JPO&Japio
JP2250597A 1990-09-20 1990-09-20 Semiconductor device Pending JPH04129274A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2250597A JPH04129274A (en) 1990-09-20 1990-09-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2250597A JPH04129274A (en) 1990-09-20 1990-09-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04129274A true JPH04129274A (en) 1992-04-30

Family

ID=17210250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2250597A Pending JPH04129274A (en) 1990-09-20 1990-09-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04129274A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005109479A (en) * 2003-09-29 2005-04-21 Samsung Electronics Co Ltd Transistor comprising salient drain and manufacturing method thereof
JP2009246205A (en) * 2008-03-31 2009-10-22 Furukawa Electric Co Ltd:The Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005109479A (en) * 2003-09-29 2005-04-21 Samsung Electronics Co Ltd Transistor comprising salient drain and manufacturing method thereof
JP2009246205A (en) * 2008-03-31 2009-10-22 Furukawa Electric Co Ltd:The Semiconductor device and method of manufacturing the same

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