JPH06224379A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to manufacture an n-type gate electrode and a p-type gate electrode in a self-aligned manner by the use of a specified step in the formation of gate electrodes of an n-type polysilicon and a p-type polysilicon, and by simplifying a manufacturing step. CONSTITUTION:An n-type well 2, a p-type well 3, a gate oxide film 5, a polysilicon film 6, an oxide film 7, and a silicon nitride film 8 are formed on a p-type semiconductor substrate 1. Then, a resist pattern 9 is formed so as to cover a PMOS region. This is then etched using the resist pattern 9 as a mask, so that a poly-silicon film 6 is exposed. A PSG 10 is deposited over the entire surface of this, and it is then subjected to thermal diffusion, whereby an n-type polysilicon region 11 is formed. This is then subjected to selective oxidation, so that an oxide film 12 is formed. A silicon nitride film is then removed. Boron ions are injected into this using an oxide film 12 as a mask, so that a p-type polysilicon region 13 is formed. This is then processed into a gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In order to realize a large capacity VLSI, it is necessary to develop an integrated circuit having a high degree of integration within a limited chip area. That is, in order to improve the degree of integration, it depends on how the elements constituting the integrated circuit can be miniaturized, and it is particularly necessary to realize a finer transistor.

Generally, in the silicon gate technology, N-type polysilicon containing a large amount of phosphorus and the like is used as a material for a gate electrode. Therefore, when a CMOS transistor is formed with an N-type polysilicon gate electrode, the work function difference between the N-type channel region and the N-type polysilicon increases in the negative direction in the PMOS transistor, so that the threshold voltage is adjusted. Therefore, it is necessary to implant impurities of the opposite type to the channel region. As a result, a very shallow PN junction is formed in the channel region of the PMOS transistor having the N-type polysilicon gate electrode, and a buried channel type transistor is obtained.

However, the buried channel type transistor is apt to cause a short channel effect, that is, it is apt to cause a problem such as lowering of threshold voltage, deterioration of subthreshold characteristics and lowering of punch-through voltage, resulting in miniaturization of the transistor. Was a big problem for me.

On the other hand, C is used as the gate electrode of P-type polysilicon.
When a MOS transistor is formed, the PMOS transistor becomes a surface channel type transistor, which is suitable for miniaturization of the transistor. However, an NMOS transistor having a P-type polysilicon gate electrode becomes a buried channel type transistor. There was a big problem with miniaturization of transistors.

Therefore, if a CMOS transistor is constituted by an NMOS transistor having an N-type polysilicon gate electrode and a PMOS transistor having a P-type polysilicon gate electrode, a surface channel CMOS transistor can be realized. Suitable for miniaturization of.

By the way, the above surface channel type CMOS
In order to form the gate electrode of the transistor, it is necessary to dope the gate electrode after doping the polysilicon that will be the gate electrode with N-type and P-type impurities. As a manufacturing method thereof, for example, after forming a polysilicon film, a window is opened in a region to be an NMOS transistor by a photolithography process, N-type impurities are ion-implanted using a resist as a mask, and after removing the resist,
Further, by a photolithography process, a window for a region to be a PMOS transistor (which usually has a negative / positive relationship with a region to be an NMOS transistor) is opened, and P-type impurities are ion-implanted using the resist as a mask. After removing the resist, there is a method of performing thermal diffusion and patterning the gate electrode to form the N-type polysilicon and P-type polysilicon gate electrodes.

There is also a method of forming a P-type polysilicon gate electrode after forming an N-type polysilicon electrode, as disclosed in JP-A-3-42869.

[0009]

As described above,
In order to form the gate electrodes of N-type polysilicon and P-type polysilicon, a photolithography process, or a method of forming a gate electrode of only N-type polysilicon or P-type polysilicon is conventionally used. The number of polysilicon film forming steps for forming the gate electrode is increased. as a result,
There are problems that the manufacturing cost becomes high and the yield decreases.

[0010]

In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device including N-channel and P-channel transistors on the same semiconductor substrate. Depositing a silicon film to serve as a gate electrode, depositing at least an oxidation resistant film on the silicon film, removing the oxidation resistant film in the first conductivity type MOS transistor formation region, and removing the silicon film. A step of introducing a first conductivity type impurity into the silicon film in the exposed region, an oxide film is selectively formed using the oxidation resistant film as a mask, and the first conductivity type MOS transistor forming region is formed. A step of leaving a silicon film, and a step of introducing a second conductivity type impurity of a conductivity type opposite to the first conductivity type into the silicon film by using the oxide film as a mask. It is due to the law.

[0011]

According to the present invention, the manufacturing process can be simplified and the gate electrodes of N-type polysilicon and P-type polysilicon can be formed, and the manufacturing cost can be reduced or the manufacturing yield can be improved. To be

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG.

First, on a P-type semiconductor substrate 1, an N well 2 and an NMO for forming a PMOS transistor whose surface concentration is controlled so as to obtain a desired threshold voltage of the transistor.
A P well 3 for forming an S transistor and a locos oxide film 4 for element isolation are formed. At this time, an N-type semiconductor substrate can be used instead of the P-type semiconductor substrate. After that, a gate oxide film 5 (100 Å) is formed by thermal oxidation, and a polysilicon film 6 for gate electrode 6 (2000) is formed.
Å), oxide film 7 (100 Å), silicon nitride film 8 (10
00Å) in order. At this time, the polysilicon film 6
May be amorphous silicon. Next, a photoresist is applied, and PM is applied by a photolithography process.
A resist pattern 9 is formed on the OS transistor formation region (FIG. 1A).

Next, using the resist pattern 9 as a mask, the oxide film 7 and the silicon nitride film 8 are exposed until the polysilicon film 6 on the NMOS transistor formation region is exposed.
Anisotropic etching is performed, the resist pattern 9 is removed after the etching, PSG 10 (phosphorus silicate glass) is deposited on the entire surface, and the exposed polysilicon film 6 is doped with N-type impurities by thermal diffusion. , N-type polysilicon region 11 is formed (FIG. 1B). In the above process, using the resist pattern 9 as a mask,
Anisotropic etching is performed until the polysilicon film 6 or the oxide film 7 is exposed, and phosphorus ions ( ³¹ P ⁺ ) are applied at 80 KeV, 5 × 10 ^{15 using the} resist pattern 9 as a mask.
Alternatively, a step of forming the N-type polysilicon region 11 by performing ion implantation at a rate of about 1 / cm ² may be used. In this case, heat treatment may be performed after the ion implantation to diffuse the ions.

Next, after the PSG 10 is removed (after removing the resist pattern 9 when phosphorus ions are implanted), selective oxidation is performed on the NMOS transistor formation region with the silicon nitride film 8 as a mask. Membrane 12
(About 500Å) is formed (FIG. 1 (c)).

Next, using the oxide film 12 as an etching stopper, the silicon nitride film 8 is removed, and using the oxide film 12 as a mask, boron ions ( ¹¹ B ⁺ ) are added at 10 KeV and 5 ×.
Ions are implanted at about 10 ¹⁵ / cm ⁻² to form a P-type polysilicon region 13 (FIG. 1D). In the above process, the silicon nitride film 8 and the oxide film 7 are removed to expose the polysilicon film 6, and then the entire surface is covered with B.
It is also possible to deposit SG (boron silicate glass) and dope P-type impurities into the exposed polysilicon film 6 by thermal diffusion to form the P-type polysilicon region 13.

Next, the oxide film 7 on the polysilicon, and
12 is removed (BSG is also removed when BSG is deposited), WSix14 (1000Å) is deposited on the entire surface by a CVD method, a photoresist is applied, and a gate electrode is patterned by a photolithography process.
Using the resist pattern 15 as a mask, the WSix 14, the N-type polysilicon region 11 and the P-type polysilicon region 13 are etched to form a gate electrode (FIG. 1).
(E)). In this process, Ti is used instead of WSix.
A metal silicon compound such as Six, MoSix, or TaSix may be used, or after a metal such as Ti is deposited,
A metal silicon compound may be formed by silicidation.

Thereafter, the source / drain regions 16 of the transistor are formed by an ion implantation method or the like (FIG. 1F) by a conventional process, an interlayer insulating film is formed, and a gate electrode,
Then, through the wiring formation process of the source and drain regions, N
A surface channel type CMOS transistor including an NMOS transistor having a type polysilicon gate electrode and a PMOS transistor having a P type polysilicon electrode can be formed.

Next, a second embodiment of the present invention will be described with reference to FIG.

First, on a P-type semiconductor substrate 21, an N well 22 for forming a PMOS transistor and a P well 23 for forming an NMOS whose surface concentration is controlled so as to obtain a desired threshold voltage of the transistor, A locos oxide film 24 for element isolation is formed. At this time, an N-type semiconductor substrate can be used instead of the P-type semiconductor substrate. After that, a gate oxide film 25 (100 Å) is formed by thermal oxidation, and a polysilicon film 26 (20
00Å), oxide film 27 (100Å), silicon nitride film 2
8 (1000Å) are deposited in this order. At this time, the polysilicon film 26 may be amorphous silicon. Next, a photoresist is applied and a resist pattern 29 is formed on the NMOS transistor formation region by a photolithography process (FIG. 2A).

Next, using the resist pattern 29 as a mask, anisotropic etching of the silicon nitride film 28 is performed until the oxide film 27 is exposed. Using the resist pattern 29 as a mask, boron ions ( ¹¹ B ⁺ ) at 10 KeV, 5x
Ions are implanted at a dose of about 10 ¹⁵ / cm ² to form a P-type polysilicon region 33 (FIG. 2B). In this case, heat treatment may be performed after the ion implantation to diffuse the ions. In the above process, using the resist pattern 29 as a mask, the oxide film 2 is formed until the polysilicon film 26 is exposed.
7 and anisotropic etching of the silicon nitride film 28 are performed, the resist pattern 29 is removed after the etching, BSG is deposited on the entire surface, and the exposed polysilicon film 26 is doped with P-type impurities by thermal diffusion. However, a step of forming the P-type polysilicon region 33 may be used.

Next, after removing the resist pattern 29 (after removing BSG when boron ions are implanted), selective oxidation is performed on the PMOS transistor formation region using the silicon nitride film 28 as a mask. Oxide film 3
2 (about 500Å) is formed (Fig. 2 (c)).

Next, the silicon nitride film 28 and the oxide film 27 are removed to expose the polysilicon film 26 on the NMOS transistor forming region, and then PSG 30 is deposited on the entire surface and exposed by thermal diffusion. Polysilicon film 26
Is doped with N-type impurities to form an N-type polysilicon region 3
1 is formed (FIG. 2D). In the above process, the silicon nitride film 28 is removed, and the oxide film 32 is used as a mask to remove phosphorus ions ( ³¹ P ⁺ ) at 20 KeV, 5 × 1.
A step of forming the N-type polysilicon region 31 by performing ion implantation at about 0 ¹⁵ / cm ⁻² may be used. In this case, heat treatment may be performed after the ion implantation to diffuse the ions.

Next, the oxide film 32 on the polysilicon and the PSG 30 are removed (when phosphorus ions are implanted, the oxide films 27 and 32 are removed), and the entire surface is WS.
ix34 (1000 Å) is deposited by a CVD method or the like, a photoresist is applied, and a gate electrode is patterned by a photolithography process. Using the resist pattern 35 as a mask, the WSix34, the N-type polysilicon region 31, and the P-type polysilicon are formed. The region 33 is etched to form a gate electrode (FIG. 2E). In this process, instead of WSix, TiSix, MoSi
x, a metal silicon compound of TaSix may be used,
Alternatively, metal such as Ti may be deposited and then silicidized to obtain a metal silicon compound.

After that, the source / drain regions 36 of the transistor are formed by an ion implantation method or the like (FIG. 2F) by a conventional process, an interlayer insulating film is formed, and a gate electrode,
Then, through the wiring formation process of the source and drain regions, N
A surface channel type CMOS transistor including an NMOS transistor having a P type polysilicon gate electrode and a PMOS transistor having a P type polysilicon gate electrode can be formed.

In the above-described first and second embodiments, the metal silicon compound is used to reduce the resistance of the gate electrode or directly connect the gate electrodes of the CMOS inverter, for example. Although effective, the gate electrode may be formed of only polysilicon without using the metal silicon compound depending on the device characteristics and purpose. Further, the sheet resistance value of only polysilicon after doping in this embodiment is about 100 to 700 Ω / port.

Further, in the polysilicon etching of the gate electrode, the etching rate of N-type polysilicon is usually faster than that of P-type polysilicon, so that the film thickness of N-type polysilicon is the film of P-type polysilicon. The thicker the thickness, the easier the etching. That is, in the polysilicon etching of the gate electrode, which is usually performed by using the thin gate oxide film as an etching stopper, the second embodiment is preferable to the second embodiment because the process margin is widened.

The present invention can be variously modified within the scope of the claims, and is not limited to the conditions (film thickness, ion species, implantation amount, etc.) in the steps shown in the above embodiments.

[0029]

As described in detail above, according to the present invention, the manufacturing process can be simplified and the N-type gate electrode and the P-type gate electrode can be formed in a self-aligned manner. As a result, the manufacturing cost can be reduced or the manufacturing yield can be improved.

Furthermore, according to the present invention, since a surface channel type CMOS transistor can be formed, it is possible to achieve high integration at a relatively low cost.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a second embodiment of the present invention.

[Explanation of symbols]

 1 P-type semiconductor substrate 2 N-well 3 P-well 4 Locos oxide film 5 Gate oxide film 6 Polysilicon film 7 Oxide film 8 Silicon nitride film 9 Resist pattern 10 PSG 11 N-type polysilicon region 12 Oxide film 13 P-type polysilicon region 14 WSix 15 resist pattern

Claims (1)

[Claims] 1. An N-channel on the same semiconductor substrate, and
In a method of manufacturing a semiconductor device including a P-channel transistor, a step of depositing a silicon film to serve as a gate electrode on a gate insulating film, and depositing at least an oxidation resistant film on the silicon film; A step of removing the oxidation resistant film in the MOS transistor formation region, a step of introducing a first conductivity type impurity into the silicon film in the removed region, and selectively using the oxidation resistant film as a mask. Forming an oxide film and leaving the silicon film in the first conductivity type MOS transistor formation region; and using the oxide film as a mask, the silicon film is provided with a second conductivity type opposite to the first conductivity type. A step of introducing a type impurity, and a method of manufacturing a semiconductor device.