JPH063809B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH063809B2 JPH063809B2 JP61180358A JP18035886A JPH063809B2 JP H063809 B2 JPH063809 B2 JP H063809B2 JP 61180358 A JP61180358 A JP 61180358A JP 18035886 A JP18035886 A JP 18035886A JP H063809 B2 JPH063809 B2 JP H063809B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- insulating film
- sio
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に放射線環境下で安定に
動作する絶縁ゲート型電界効果トランジスタを含む半導
体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an insulated gate field effect transistor that operates stably in a radiation environment.
現在、シリコン等を半導体基板材料とした半導体装置
は、絶縁ゲート型電界効果トランジスタ(以降MIS
FETと称す)を含む種類のものが非常に多い。Currently, a semiconductor device using silicon or the like as a semiconductor substrate is an insulated gate field effect transistor (hereinafter referred to as MIS).
There are a great many types including "FET").
このような半導体装置では、MIS FETは勿論素子
領域同士を絶縁分離するフィールド領域等もMIS構造
になっている場合がある。In such a semiconductor device, not only the MIS FET but also the field region or the like for insulating the element regions from each other may have the MIS structure.
従来、MIS構造の絶縁物には、半導体基板の材料がシ
リコンの場合には、半導体基板表面を熱酸化することに
より得られたシリコン酸化膜(以下単にSiO2膜と称
す)が広く用いられている。Conventionally, a silicon oxide film (hereinafter simply referred to as a SiO 2 film) obtained by thermally oxidizing the surface of a semiconductor substrate has been widely used as an insulator of a MIS structure when the material of the semiconductor substrate is silicon. There is.
これは、この方法が比較的簡単にクリーンな界面を有す
る良質の絶縁膜を得ることができ、しかもその電気的特
性も良好であるという理由による。This is because this method can relatively easily obtain a good-quality insulating film having a clean interface and has good electrical characteristics.
近年、各種人工衛星の実用化等に伴い、放射線環境下で
も安定に動作する半導体装置が要求されている。2. Description of the Related Art In recent years, with the practical use of various artificial satellites, there is a demand for semiconductor devices that operate stably even in a radiation environment.
しかし、上述した従来の半導体装置は、絶縁物として熱
酸化したSiO2膜を用いたMIS FETで構成され
ているので、放射線環境下で動作させると、その特性が
吸収線量の増大につれて劣化するという欠点がある。However, since the conventional semiconductor device described above is composed of a MIS FET using a thermally oxidized SiO 2 film as an insulator, its characteristics deteriorate as the absorbed dose increases when operated in a radiation environment. There are drawbacks.
この原因は、これまでに行なわれた各方面の研究から、
SiO2/Si構造部分の電気的特性変化に起因するこ
とがわかっており、主として、(1)SiO2膜中の正
電荷の形成、及び(2)SiO2/Si界面準位の形成
によってもたらされるとされている。The reason for this is that from the various research conducted so far,
It is known that it is caused by a change in the electrical characteristics of the SiO 2 / Si structure portion, and it is mainly caused by (1) formation of positive charges in the SiO 2 film and (2) formation of SiO 2 / Si interface states. It is supposed to be.
本発明の目的は、放射線環境下において、SiO2/S
i構造部分の電気的特性変化に起因するデバイス特性の
劣化を抑制することができる高集積度を有する半導体装
置を提供することにある。The object of the present invention is to obtain SiO 2 / S in a radiation environment.
An object of the present invention is to provide a semiconductor device having a high degree of integration that can suppress deterioration of device characteristics due to a change in electrical characteristics of an i-structure portion.
本発明の特徴は、半導体基板に形成された電界効果トラ
ンジスタを有する半導体装置において、前記電界効果ト
ランジスタのゲート絶縁膜はテトラエチルオルト珪酸を
用いて成長した酸化膜のみから構成されている半導体装
置にある。A feature of the present invention is a semiconductor device having a field effect transistor formed on a semiconductor substrate, wherein the gate insulating film of the field effect transistor is composed only of an oxide film grown using tetraethylorthosilicic acid. .
以下、本発明の実施例について図面を参照して説明す
る。Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
この実施例は、P型のシリコン基板1の上にテトラエチ
ルオルト珪酸を用いて成長した酸化膜(以降TEOS膜
と称す)3を介して、多結晶シリコン膜のゲート4が配
置され、n+拡散層のソース5とドレイン6とで構成さ
れるMIS FETを含む半導体装置を示している。In this embodiment, a gate 4 of a polycrystalline silicon film is arranged on a P-type silicon substrate 1 through an oxide film (hereinafter referred to as TEOS film) 3 grown using tetraethylorthosilicic acid, and n + diffusion is performed. 1 shows a semiconductor device including a MIS FET composed of a source 5 and a drain 6 of a layer.
第2図は本発明に関係ある技術の断面図である。FIG. 2 is a sectional view of a technique related to the present invention.
この第2図では、P型のシリコン基板1′の上にSiO
2膜の絶縁膜3″及びTEOS膜3′を設け、絶縁膜
3″とTEOS膜3′とを介してリンドープした多結晶
シリコン膜のゲート4′及び接地電極4″とを設け、更
にn+拡散層のソース5′,5″及びドレイン6′をシ
リコン基板1′表面に設けている。ここで、絶縁膜3″
とTEOS膜3′は、ソース5′,ドレイン6′及びゲ
ート4′とで構成されるMIS FETのゲート絶縁膜
でありその下のシリコン基板1′表面がチャネル領域と
なる。一方、接地電極7′は、その下の絶縁膜3a″及
びTEOS膜3a′とシリコン基板1′とでMISを構
成することによって表面電位の関係でシリコン基板1′
の表面に寄生のチャネル領域が出来ないようにして素子
分離領域を構成している。In FIG. 2, SiO is formed on the P-type silicon substrate 1 '.
Two insulating films 3 ″ and a TEOS film 3 ′ are provided, and a gate 4 ′ and a ground electrode 4 ″ of a phosphorus-doped polycrystalline silicon film are provided through the insulating film 3 ″ and the TEOS film 3 ′, and further n + Sources 5 ', 5 "and a drain 6'of the diffusion layer are provided on the surface of the silicon substrate 1'. Here, insulating film 3 "
The TEOS film 3'and the TEOS film 3'are gate insulating films of a MIS FET composed of a source 5 ', a drain 6', and a gate 4 ', and the surface of the silicon substrate 1'underneath serves as a channel region. On the other hand, the ground electrode 7'consists of the surface potential by forming an MIS with the underlying insulating film 3a "and TEOS film 3a 'and the silicon substrate 1'.
The element isolation region is formed so that no parasitic channel region is formed on the surface of the device.
上記のTEOS膜は、熱酸化SiO2膜に比べて、膜中
に含まれる再結合中心が多いため、入射した電離性放射
線によって生じた電子−正孔の再結合が促進され、酸化
膜中のトラップに捕獲される正電荷の量を大きく減らす
ことが可能となる。又、TEOS膜は従来のシラン系ガ
スを用いた気相化学成長法により堆積した酸化膜に比
べ、薄膜の成長膜厚の制御が良好であるので、熱酸化に
よらずにMIS FETのゲート絶縁膜を形成できる。Since the TEOS film has more recombination centers contained in the film than the thermally oxidized SiO 2 film, recombination of electrons and holes generated by the incident ionizing radiation is promoted, and It is possible to greatly reduce the amount of positive charges trapped in the trap. Further, the TEOS film has a better control of the growth film thickness of the thin film than the oxide film deposited by the vapor phase chemical growth method using the conventional silane-based gas, so that the gate insulation of the MIS FET can be achieved without the thermal oxidation. A film can be formed.
第3図(a)〜(f)は本発明の実施例の半導体装置の
製造方法を説明するための工程順に示した半導体チップ
の断面図である。3 (a) to 3 (f) are cross-sectional views of a semiconductor chip showing the order of steps for explaining the method for manufacturing a semiconductor device according to the embodiment of the present invention.
先ず、第3図(a)に示すように、P型のシリコン基板
1を熱酸化することにより、シリコン基板1表面にSi
O2膜の絶縁膜2aを形成し、さらに絶縁膜2bとして
窒化膜を形成する。First, as shown in FIG. 3A, the P-type silicon substrate 1 is thermally oxidized to form Si on the surface of the silicon substrate 1.
An insulating film 2a of an O 2 film is formed, and a nitride film is further formed as an insulating film 2b.
次に、第3(b)に示すように、素子領域となる部分を
覆うホトレジスト膜10を所定のパターンで形成し、通
常の反応性イオンエッチング法により、ホトレジスト膜
10をマスクとして、絶縁膜2b及び2aの窒化膜及び
SiO2膜をエッチングする。Next, as shown in FIG. 3 (b), a photoresist film 10 covering a portion to be an element region is formed in a predetermined pattern, and the insulating film 2b is masked by the ordinary reactive ion etching method using the photoresist film 10 as a mask. And 2a, the nitride film and the SiO 2 film are etched.
次に、第3図(c)に示すように、ホトレジスト膜10
を除去した後に、残存する絶縁膜2bを耐酸化マスクと
して、シリコン基板1を熱酸化し、素子分離用の絶縁膜
2となるSiO2膜を形成する。Next, as shown in FIG. 3C, the photoresist film 10
Then, the silicon substrate 1 is thermally oxidized using the remaining insulating film 2b as an anti-oxidation mask to form a SiO 2 film which will become the insulating film 2 for element isolation.
その後、絶縁膜2b及び2aの窒化膜及びSiO2膜を
除去した後、第3図(d)に示すように、基板表面上に
CVD法によりTEOS膜3を被着し、更にリンドープ
した多結晶シリコン膜4aを成長した後、ホトレジスト
膜11を所定のパターンで形成する。Then, after removing the nitride film and the SiO 2 film of the insulating films 2b and 2a, as shown in FIG. 3 (d), a TEOS film 3 is deposited on the surface of the substrate by the CVD method, and further phosphorus-doped polycrystalline After growing the silicon film 4a, the photoresist film 11 is formed in a predetermined pattern.
次に、第3図(e)に示すように、ホトレジスト膜11
をマスクとして、多結晶シリコン膜4aをエッチングし
てゲート4を形成した後、ホトレジスト膜11を除去す
る。そして、多結晶シリコン膜のゲート4及び素子分離
用の絶縁膜2をマスクとして砒素をイオン注入してn+
領域のソース5及びドレイン6をシリコン基板1の表面
に形成する。Next, as shown in FIG. 3 (e), the photoresist film 11
Using the as a mask, the polycrystalline silicon film 4a is etched to form the gate 4, and then the photoresist film 11 is removed. Then, using the gate 4 of the polycrystalline silicon film and the insulating film 2 for element isolation as a mask, arsenic is ion-implanted to n +.
The source 5 and the drain 6 of the region are formed on the surface of the silicon substrate 1.
最後に、第3図(f)に示すように、通常工程によって
絶縁膜7、ソース及びドレイン電極8a,8b並びに絶
縁膜9を形成すれば、本発明の第1の実施例のMIS
FETを含む半導体装置が得られる。Finally, as shown in FIG. 3 (f), if the insulating film 7, the source and drain electrodes 8a and 8b, and the insulating film 9 are formed by a normal process, the MIS of the first embodiment of the present invention can be obtained.
A semiconductor device including a FET can be obtained.
以上説明したように本発明は、ゲート絶縁膜をTEOS
膜のみから構成することにより、放射線環境下での電気
的特性の劣化を制御することが可能となり、従って、放
射線環境下でも高い信頼性をもつ高集積度の半導体装置
を得ることができるという効果がある。As described above, according to the present invention, the gate insulating film is formed of TEOS.
By using only a film, it is possible to control the deterioration of electrical characteristics in a radiation environment, and therefore it is possible to obtain a highly integrated semiconductor device having high reliability even in a radiation environment. There is.
第1図は本発明の実施例の断面図、第2図は本発明に関
係のある技術の断面図、第3図(a)〜(f)は本発明
の半導体装置の製造方法の一実施例を説明するための工
程順に示した半導体チップの断面図である。 1,1′…シリコン基板、2,2a,2b…絶縁膜、
3,3′,3a,3a′…TEOS膜、3″,3a″…
絶縁膜、4,4′…ゲート、4″…接地電極、4a…多
結晶シリコン膜、5,5′,5″…ソース、6,6′…
ドレイン、7,7′…絶縁膜、8a,8a′…ソース電
極、8b,8b′…ドレイン電極、9…絶縁膜、10,
11…ホトレジスト膜。FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a sectional view of a technique related to the present invention, and FIGS. 3 (a) to (f) are one embodiment of a method for manufacturing a semiconductor device of the present invention. FIG. 6 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining an example. 1, 1 '... Silicon substrate, 2, 2a, 2b ... Insulating film,
3, 3 ', 3a, 3a' ... TEOS film, 3 ", 3a" ...
Insulating film, 4, 4 '... Gate, 4 "... Ground electrode, 4a ... Polycrystalline silicon film, 5, 5', 5" ... Source, 6, 6 '...
Drain, 7, 7 '... Insulating film, 8a, 8a' ... Source electrode, 8b, 8b '... Drain electrode, 9 ... Insulating film, 10,
11 ... Photoresist film.
Claims (1)
スタを有する半導体装置において、前記電界効果トラン
ジスタのゲート絶縁膜はテトラエチルオルト珪酸を用い
て成長した酸化膜のみから構成されていることを特徴と
する半導体装置。1. A semiconductor device having a field effect transistor formed on a semiconductor substrate, wherein a gate insulating film of the field effect transistor is composed only of an oxide film grown using tetraethylorthosilicic acid. Semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61180358A JPH063809B2 (en) | 1986-07-30 | 1986-07-30 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61180358A JPH063809B2 (en) | 1986-07-30 | 1986-07-30 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6336569A JPS6336569A (en) | 1988-02-17 |
JPH063809B2 true JPH063809B2 (en) | 1994-01-12 |
Family
ID=16081845
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61180358A Expired - Lifetime JPH063809B2 (en) | 1986-07-30 | 1986-07-30 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH063809B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06105726B2 (en) * | 1989-10-13 | 1994-12-21 | 三菱電機株式会社 | Semiconductor integrated circuit device |
JP2680448B2 (en) * | 1989-11-10 | 1997-11-19 | 東芝マイクロエレクトロニクス 株式会社 | Radiation resistant semiconductor device manufacturing method |
JPH03237728A (en) * | 1990-02-14 | 1991-10-23 | Matsushita Electron Corp | Manufacture of semiconductor device |
US6593195B1 (en) * | 1999-02-01 | 2003-07-15 | Agere Systems Inc | Stable memory device that utilizes ion positioning to control state of the memory device |
JP4740290B2 (en) * | 2008-06-27 | 2011-08-03 | 日立建機株式会社 | Construction machinery |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4855675A (en) * | 1971-11-12 | 1973-08-04 |
-
1986
- 1986-07-30 JP JP61180358A patent/JPH063809B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS6336569A (en) | 1988-02-17 |
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