JPH09213785A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has a fine element isolating region which can get the shape of a flat surface, and does not cause the deterioration of element property, and its manufacturing method. SOLUTION: A gate oxide film 102 and a first gate electrode 103 are made all over the surface, and a taper groove of 80 deg. or under is provided in the element isolating region, and ions of channel stopper impurities are implanted. Then, an oxide film is accumulated, and by using chemical polishing method, it is flattened until the first gate electrode 103 is exposed, and the groove is stopped with an oxide film 106, and a second electrode 107 is made, and the first electrodes 103 and 107 are made in desired form.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device suitable for fine element isolation and a manufacturing method thereof.

[0002]

2. Description of the Related Art As a method of forming a trench in a semiconductor substrate and burying an insulating film in the trench to form an element isolation region, for example, a method described in JP-A-2-143461 is used. There is. FIG. 11 is a schematic diagram in the process of manufacturing the element isolation region.

First, as shown in FIG. 11A, the Si substrate 6
On the gate oxide film 602 and the first gate electrode 6
03 is formed on the entire surface. Next, the oxide film 6 is formed by the CVD method.
04 is formed, this is patterned by lithography and a dry etching technique, and further, dry etching is performed using the oxide film 604 as a mask to form a groove 605. After forming the oxide film 606 inside the groove 605, as shown in FIG.
As shown in (b), the channel stopper 607 is formed by ion implantation with an inclination angle. Next, after removing the oxide film 604, the thick oxide film 6 is formed by the CVD method.
No. 08 is formed, and an oxide film 608 is embedded in the groove 605 as shown in FIG. Then, the oxide film 608 is etched back by dry etching to remove the first gate electrode 6
After exposing 03, a channel impurity 609 for controlling the threshold value of the transistor is introduced by ion implantation to form a second gate electrode 610, so that the inside of the trench as shown in FIG. A semiconductor device having an element isolation region in which an insulating film is embedded can be formed.

In the conventional example, since the gate oxide film is formed on the Si substrate having few irregularities, the gate oxide film is not locally thinned due to the irregularities on the surface of the Si substrate, and the uniformity is excellent. A high quality gate oxide film can be formed. Further, by forming the groove-embedded element isolation region after forming the gate oxide film and the gate electrode, the element isolation region surface can be made higher than the Si substrate surface in the element region, as shown in FIG. 11D. Since the distance between the Si substrate edge and the gate electrode can be effectively lengthened, the influence of the electric field on the Si substrate edge is reduced when a voltage is applied to the gate electrode, and the threshold of the transistor formed in the element region is reduced. It is possible to prevent variation in value characteristics. Further, since the first gate electrode serves as a stopper when the oxide film buried in the trench is etched back to be flattened, even if the etching back is performed by dry etching, the S
Highly accurate processing is possible without damaging the i substrate.

[0005]

A problem in the conventional example is that the shape of the groove formed in the element isolation region is vertical. When the shape of the groove side surface is vertical, the groove depth is 2
When the groove width (element isolation width) is less than double, the growth rate of the CVD oxide film in the groove opening is faster than in the groove, so that there is a problem that voids are generated inside the oxide film embedded in the groove. It was If such voids are present inside the oxide film, the voids are exposed on the surface after the etching back, and an etching residue is generated during the subsequent gate electrode processing, which causes a short circuit.

Further, when impurity ion implantation for preventing the formation of channels is performed on the bottom and side surfaces of a vertical groove with an inclination angle, when the groove width becomes finer, impurities are formed on the bottom and side surfaces of the groove. Therefore, there is a problem that leakage current easily flows along the bottom surface and the side surface of the groove, which causes deterioration of transistor characteristics, junction characteristics, element isolation performance, and the like.

Still another problem is that when a groove is formed in a Si substrate and a CVD oxide film is formed on the entire surface and etched back, as shown in FIG. 11D, a wide groove (element isolation region) is not formed. That is, a step corresponding to the groove depth is generated. Such a large step makes it difficult to etch the gate electrode later when patterning it.

An object of the present invention is to provide a semiconductor device having a fine element isolation region and a manufacturing method which can obtain a flat buried shape and which does not cause deterioration of element characteristics.

[0009]

[Means for Solving the Problems] To achieve the purpose, S
A gate insulating film and a first gate electrode are sequentially formed on the entire surface of the i substrate, and the gate electrode and the gate insulating film in the element isolation region are opened. Next, a groove having an inclination of 80 degrees or less with respect to the main surface of the Si substrate in the opening is formed, an oxide film is formed on the surface of the Si substrate in the groove, and a channel stopper impurity is ionized at an inclination angle. inject. After that, an insulating film is deposited and buried in the groove, the insulating film on the gate electrode is planarized and removed by a chemical mechanical polishing method, another gate electrode is formed on the entire surface, and two gate electrodes are formed into a desired shape. To form.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

<Embodiment 1> The most basic embodiment of the present invention is shown in FIGS.
It was shown to. First, as shown in FIG. 1A, the Si substrate 1
On the surface of 01, a gate oxide film 102 having a thickness of 3 nm and a first gate electrode 103 having a thickness of 20 nm are sequentially formed on the entire surface. As the material of the first gate electrode 103, polycrystalline Si is used in this embodiment.

Next, the first gate electrode 103 and the gate oxide film 102 on the element isolation region are opened by using a known lithography technique, and then S is formed by dry etching.
Groove 10 having a depth of 200 nm and having a taper on the i substrate 101
4 is formed. Here, the taper angle of the groove 104 is formed at an angle of 80 degrees or less with respect to the main surface of the Si substrate. Next, the surface of the groove 104 is thermally oxidized to form a 10 nm thick oxide film 1 in the groove.
After forming 05, impurities for preventing channel formation are ion-implanted into the bottom surface and side surfaces of the groove 104 with an inclination angle (not shown). After that, as shown in FIG. 1B, a thick oxide film 1 is formed on the entire surface including the groove 104 by the CVD method.
06 is deposited. Here, the deposited film thickness is 1.5 times the groove depth.

Next, as shown in FIG. 1C, the oxide film 106 is flattened by chemical mechanical polishing. Subsequently, as shown in FIG. 1D, the first gate electrode 103
The entire surface of the oxide film 106 is etched by dry etching to expose the oxide film 106, and the oxide film 106 is embedded in the trench 104.
As described above, the chemical mechanical polishing method and the overall etching by the dry etching are used in combination because the first gate electrode 103, which is the base for removing the oxide film 106, is as thin as 20 nm, so that the polishing cannot secure the selectivity. This is because the etching cannot be stopped by the method.

After that, impurities for adjusting the threshold voltage of the transistor are ion-implanted through the first gate electrode 103 (not shown). Thereafter, as shown in FIG. 2A, a second gate electrode 107 is formed on the entire surface,
Further, as shown in FIG. 2B, the second gate electrode 10
The element isolation structure is completed by patterning 7 and the first gate electrode 103 into a desired shape. After the above steps, a source, a drain, a contact, and a wiring layer are formed to manufacture a MOS field effect transistor.

In the semiconductor device manufactured as described above, by filling the groove 104 with a taper of 80 degrees or less, the filling of the CVD oxide film from the bottom of the groove is completed, so that a void is generated in the oxide film. Never. Therefore,
The surface of the oxide film can be made flat when the oxide film is buried only in the groove by performing the flattening, and an etching residue does not occur when the gate electrode is formed later.

Further, by providing the groove 104 with a taper of 80 degrees or less, even when the groove width is miniaturized at the time of ion-implanting impurities for preventing channel formation to the bottom surface and the side surface of the groove. Impurities can be introduced to the side surface of the groove,
Leakage current flowing along the side surface of the groove can be reduced, and transistor characteristics, junction characteristics, and element isolation performance are not deteriorated.

Further, by using the chemical mechanical polishing method and the whole surface etching method by dry etching together for the flattening, the surface can be flattened over the whole surface of the wafer including the wide groove (element isolation region) and the stopper for the whole surface etching. Since highly selective flattening is possible with respect to the first gate electrode 103 which is, a completely flat surface can be obtained.
Therefore, as shown in FIG. 2A, the gate electrode can be easily formed later.

Further, according to the present embodiment, as shown in FIG. 2B, the surface of the oxide film 106 formed in the element isolation region is closer to the first gate electrode 10 than the surface of the Si substrate 101 in the element region.
It becomes higher by 3. As a result, the distance between the gate electrode 107 on the element isolation region and the channel end of the transistor formed in the element region can be effectively lengthened, so that the voltage is applied to the channel end when a voltage is applied to the gate electrode. The electric field can be relaxed, and fluctuations in the threshold voltage of the transistor can be suppressed.

The material of the second gate electrode 107 is not particularly limited, and may be, for example, W, Mo, C.
Any material of o, Ti, Ta, or a silicide thereof may be used.

Further, this method limits the conductivity type of the MOSFET, whether it is an nMOSFET or a pMOSFET, or a CMOS (Complementary MOS) device in which these are mixed.
It can be manufactured in exactly the same way.

<Second Embodiment> A second embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 3A, a gate oxide film 202 having a thickness of 3 nm, a first gate electrode 203 having a thickness of 20 nm, and a CVD film having a thickness of 100 nm are formed on the surface of a Si substrate 201. The oxide film 204 formed by the method is sequentially formed on the entire surface. As the material of the first gate electrode 203, polycrystalline Si was used also in this embodiment.

Then, the oxide film 204 on the element isolation region and the first gate electrode 20 are formed by using a known lithography technique.
3 and the gate oxide film 202 are opened, an oxide film with a thickness of 20 nm is formed on the entire surface by the CVD method.
As shown in (b), side spacers 205 are formed on the side surfaces of the first gate electrode 203 and the gate oxide film 202 by dry etching.

Next, as in the first embodiment, the Si substrate 201 is tapered to a depth of 20 by dry etching.
0 nm groove 206 and 10 nm thick oxide film 20 in the groove
After forming No. 7, impurities for preventing channel formation are ion-implanted into the bottom and side surfaces of the groove 206 (not shown). Thereafter, as shown in FIG. 3C, a thick oxide film 208 is deposited by the CVD method on the entire surface including the groove 206.

Next, the oxide film 20 is formed by the chemical mechanical polishing method.
8 (FIG. 4A), and then the oxide film 208 is etched back by dry etching until the first gate electrode 203 is exposed, and the oxide film 208 is etched into the groove 206.
It is embedded inside (FIG. 4 (b)). After that, impurities for adjusting the threshold value of the transistor are ion-implanted through the exposed first gate electrode 203 (not shown). Thereafter, as shown in FIG. 4C, the second gate electrode 209 is formed on the entire surface to complete the element isolation structure. After this, the gate electrode is processed into the desired shape and the MOSF
The use of ET is the same as in the first embodiment.

In this embodiment, the side spacer 20
Since the groove 206 of the Si substrate 201 is processed after forming No. 5, the gate oxide film 202 at the end of the element region is not directly damaged by the dry etching due to the processing of the groove 206, so that the gate oxide film is different from that of the first embodiment. The reliability of 202 is improved. Other effects are similar to those of the first embodiment.

<Third Embodiment> A third embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 5A, a gate oxide film 302 having a thickness of 3 nm, a first gate electrode 303 having a thickness of 20 nm, and a CVD film having a thickness of 100 nm are formed on the surface of a Si substrate 301. A nitride film 304 formed by the method is sequentially formed on the entire surface. As the material of the first gate electrode 303, polycrystalline Si was used also in this embodiment.

Subsequently, the nitride film 304 on the element isolation region and the first gate electrode 30 are formed by using a known lithography technique.
3 and the gate oxide film 302 are opened, a groove 305 having a depth of 200 nm and a thickness of 1 are formed on the Si substrate 301 by dry etching, similarly to the first embodiment.
After the 0 nm in-groove oxide film 306 is formed, impurities for preventing channel formation are ion-implanted into the bottom surface and side surfaces of the groove 305 (not shown). Thereafter, as shown in FIG. 5B, a thick oxide film 307 is deposited on the entire surface including the groove 305 by the CVD method.

Next, as shown in FIG. 5C, the nitride film 3
04 oxide film 307 is planarized by chemical mechanical polishing until the surface is exposed, and oxide film 307 is embedded in trench 305. Subsequently, after removing the nitride film 304, ion implantation (not shown) for adjusting the threshold value of the transistor is performed through the first gate electrode 303, and further, FIG.
As shown in FIG. 6A, a second gate electrode 308 is formed on the entire surface, and the second gate electrode 308 and the first gate electrode 303 are patterned into a desired shape (FIG. 6B). The structure is completed.

In this embodiment, since the nitride film 304, which is the stopper film of the chemical mechanical polishing method, is formed on the element region, it is buried in the element isolation region as compared with the first and second embodiments. The height of the oxide film 307 can be increased. Therefore, the effective distance between the gate electrodes 303 and 308 on the element isolation region and the channel end of the transistor formed in the element region can be made longer, so that the fluctuation of the threshold voltage of the transistor can be further suppressed. .

Further, in the first and second embodiments, the flattening of the oxide film to be buried in the groove is performed by using both the chemical mechanical polishing method and the entire surface etching by dry etching.
In this embodiment, since the oxide film 307 is planarized only by the chemical mechanical polishing method, the number of manufacturing steps can be reduced and the manufacturing cost can be reduced.

<Fourth Embodiment> A fourth embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 7A, a gate oxide film 402 having a thickness of 3 nm and a first gate electrode 403 having a thickness of 10 nm are sequentially formed on the entire surface of a Si substrate 401. As the material of the first gate electrode 403, a metal material such as W is used in this embodiment.

Subsequently, after opening the first gate electrode 403 and the gate oxide film 402 on the element isolation region by using a known lithography technique, the Si substrate 401 is dry-etched on the Si substrate 401 as in the first embodiment. A groove 404 having a depth of 200 nm and having a taper is formed, and the thickness is 10 n.
After forming the in-groove oxide film 405 of m, impurities for preventing channel formation are ion-implanted into the bottom surface and the side surface of the groove 404 (not shown). In order to grow an oxide film on the surface of the silicon substrate where W is exposed, a method of heat treatment in a mixed gas atmosphere of H ₂ and H ₂ O is used as described in Japanese Patent No. 47367. With this method, an oxide film can be grown on the surface of the silicon substrate while preventing the oxidation of W. After that, as shown in FIG.
A thick oxide film 406 is deposited by CVD on the entire surface including.

Next, as shown in FIG. 7C, the oxide film 406 is planarized by a chemical mechanical polishing method until the first gate electrode 403 on the element region is exposed, and the oxide film 406 is formed in the groove 404. Embed in. Then, the first gate electrode 40
Ion implantation of impurities for adjusting the threshold voltage of the transistor is performed through (3).

Then, as shown in FIG. 8A, a second gate electrode 407 is formed on the entire surface. The material of the second gate electrode 407 was the same as that of the first gate electrode 403. Subsequently, as shown in FIG. 8B, the element isolation structure is completed by patterning the second gate electrode 407 and the first gate electrode 403 into desired shapes.

In this embodiment, unlike the first to third embodiments, a metal material is used for the first gate electrode 403, so that when the oxide film 406 is flattened by the chemical mechanical polishing method. It is possible to increase the polishing rate ratio.
Even if the thickness of the gate electrode 403 is reduced, good planarization polishing can be performed. Further, by reducing the thickness of the first gate electrode 403, it is possible to reduce the step difference at the boundary of the element isolation region when processing the second and first gate electrodes 403 and 407, and thus it is easier to process the gate electrode. Can be done. Other effects are similar to those of the first embodiment.

<Fifth Embodiment> A fifth embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 9A, a resist 502 having a shape of an element region is formed on the surface of a Si substrate 501 by using a known lithography technique, and subsequently, a first implementation is performed in an element isolation region. As in the example, dry etching is used to
Groove 50 having a depth of 200 nm and having a taper on the i substrate 501
Form 3

Next, as shown in FIG. 9B, the groove 503 is formed.
An oxide film 504 is formed on the surface of, and impurities for preventing channel formation are ion-implanted into the bottom and side surfaces of the groove 503 (not shown). Then, a thick oxide film 505 is deposited on the entire surface by the CVD method.

Next, as shown in FIG. 9C, the oxide film 505 is flattened by chemical mechanical polishing until the Si substrate 501 in the element region is exposed, and the oxide film 505 is buried in the groove 503 and exposed. Polishing scratches and the like on the surface of the Si substrate 501 are removed by cleaning. Since the silicon substrate is polished faster than the oxide film during polishing, the surface of the oxide film for element isolation becomes higher than the surface of the substrate.

After that, as shown in FIG. 10A, a gate oxide film 506 having a thickness of 3 nm is formed, and a gate electrode 507 is further formed on the entire surface. Here, the gate electrode 50
Any material may be used as the material of 7. Note that ion implantation of impurities (not shown) for adjusting the threshold voltage of the transistor may be performed by any method. For example, the gate oxide film 506 may be formed by removing the sacrificial oxide film after performing the process through the sacrificial oxide film, or may be performed immediately after the gate oxide film 506 is formed. Then, as shown in FIG.
The element isolation structure is completed by patterning 07 into a desired shape.

Unlike the first to fourth embodiments, the present embodiment is a simple method of forming the gate oxide film 506 and the gate electrode 507 after burying the thick oxide film 505 in the element isolation region. Similar to the first to fourth embodiments,
The height of the surface of the oxide film 505 formed in the element isolation region can be made higher than that of the Si substrate 501 in the element region. As a result, the distance between the gate electrode 507 on the element isolation region and the channel end of the element region can be effectively lengthened, so that fluctuations in the threshold voltage of the transistor can be suppressed.

Although the present invention has been described with reference to some embodiments, some changes can be made without departing from the gist of the present invention. For example, the material of the oxide film to be embedded in the groove is not limited to the non-doped CVD film, but may be a film that can be reflowed by heat treatment such as phosphorus glass, boron glass, or BPSG, or an oxide film made of TEOS as a raw material. In addition, a film that can obtain a reflow shape during deposition may be used. The well may be formed either before or after the element isolation region is formed.

[0045]

According to the present invention, the groove for element isolation is provided with 80
CV from the bottom of the groove by giving a taper of
Since the filling of the D oxide film is completed, no void is generated in the oxide film. Therefore, the surface of the oxide film can be flattened when the oxide film is buried only in the groove by performing the flattening, and no etching residue occurs when the gate electrode is formed later.

Further, a wide groove (element isolation region) can be obtained by using only the chemical mechanical polishing method for planarization, or by using both the chemical mechanical polishing method and the entire surface etching method by dry etching.
The surface can be flattened over the entire surface of the wafer including, and the highly selective flattening can be performed with respect to the first gate electrode that is the stopper for the entire surface etching, so that a perfectly flat surface can be obtained. Therefore, it is possible to easily form the gate electrode later.

Another advantage of the groove having a taper of 80 degrees or less is that the groove width is made fine when ions are implanted into the bottom and side surfaces of the groove to prevent channel formation. However, since impurities can be introduced into the side surface of the groove, the leak current flowing along the side surface of the groove can be reduced, and deterioration of transistor characteristics, junction characteristics, and element isolation performance can be suppressed.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process showing a first embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process showing the first embodiment of the present invention.

FIG. 3 is a sectional view of a manufacturing process showing the second embodiment of the present invention.

FIG. 4 is a sectional view of a manufacturing process showing the second embodiment of the present invention.

FIG. 5 is a sectional view of a manufacturing process showing the third embodiment of the present invention.

FIG. 6 is a sectional view of a manufacturing process showing the third embodiment of the present invention.

FIG. 7 is a sectional view of a manufacturing process showing the fourth embodiment of the present invention.

FIG. 8 is a sectional view of a manufacturing process showing the fourth embodiment of the present invention.

FIG. 9 is a sectional view of a manufacturing process showing the fifth embodiment of the present invention.

FIG. 10 is a manufacturing process sectional view showing a fifth embodiment of the present invention.

FIG. 11 is a cross-sectional view of a manufacturing process of a conventional element isolation structure.

[Explanation of symbols]

101 ... Si substrate, 102 ... Gate oxide film, 103 ... First gate electrode, 104 ... Trench, 105 ... Trench oxide film, 10
6 ... Oxide film, 107 ... Second gate electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshio Honma 1-280 Higashi Koikeku, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Jiro Yugami 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory

Claims (10)

[Claims] 1. An element region in which at least one insulated gate field effect transistor is formed on a semiconductor substrate,
And a device isolation region formed of an insulating film embedded in the semiconductor substrate for electrically insulating and isolating between the transistors, the thickness of the wiring of the gate electrode on the device region,
In a semiconductor device thicker than the thickness of the gate electrode wiring on the element isolation region, the element region boundary portion of the insulating film formed in the element isolation region is 80 degrees or less with respect to the main surface of the semiconductor substrate. A semiconductor device having an inclination. 2. The semiconductor device according to claim 1, wherein the surface of the insulating film in the element isolation region is higher than the surface of the semiconductor substrate in the element region. 3. A method of manufacturing a semiconductor device, comprising: forming a plurality of insulated gate field effect transistors on a semiconductor substrate; and an element isolation region having a groove for isolating them. A step of sequentially forming a film and a first gate electrode on the entire surface and removing the gate electrode and the gate insulating film in the element isolation region to form an opening; and forming the opening in the semiconductor substrate in the opening. The step of forming a groove having an inclination of 80 degrees or less with respect to the main surface, the step of forming an oxide film on the surface of the semiconductor substrate in the groove, and the ion implantation for channel inversion prevention are performed with an inclination angle. The step of performing, the step of depositing and filling an insulating film in the groove, and the step of planarizing and removing the insulating film on the gate electrode to form the element isolation region, and then the second step.
And forming the second and first gate electrodes in desired shapes on the entire surface. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the means for removing the planarization is a combination of a chemical mechanical polishing method and a dry etching whole surface etching method. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the means for planarizing and removing uses a chemical mechanical polishing method. 6. The method of manufacturing a semiconductor device according to claim 3, wherein the first gate electrode is polycrystalline silicon having a thickness of 50 nm or less. 7. The first gate electrode is polycrystalline silicon having a thickness of 50 nm or less, and the second gate electrode is a metal silicide film or a metal via a barrier film for preventing a reaction between silicon and the metal. The method for manufacturing a semiconductor device according to claim 3, wherein 8. The metal of the second gate electrode is W, M
8. Any one of o, Co, Ti, or Ta.
A method of manufacturing a semiconductor device according to item 1. 9. The method of manufacturing a semiconductor device according to claim 3, wherein the first gate electrode is W having a thickness of 50 nm or less, and the second gate electrode is also a metal containing at least W. 10. A step of forming a gate insulating film and a first gate electrode on the entire surface of a semiconductor substrate sequentially in order to remove the gate electrode and the gate insulating film in an element isolation region to form an opening, and the opening. Forming a groove having an inclination of 80 degrees or less with respect to the main surface of the semiconductor substrate, forming an oxide film on the surface of the semiconductor substrate in the groove, and preventing channel inversion. Insulation gate type field effect after the steps of performing the ion implantation with a tilt angle, depositing and filling an insulating film in the groove, and planarizing and removing the insulating film on the gate electrode. The method of manufacturing a semiconductor device according to claim 3, wherein impurities are introduced to control the threshold value of the transistor.