JP2000188325A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming an element isolation region into such a shape that satisfactory element isolation characteristic can be obtained easily, when a fine trench element isolation region is formed. SOLUTION: On the top surface of a semiconductor silicon substrate 1, an oxide film 2 and a silicon nitride film 3 are formed. Then an opening is formed in the oxide film 2 and the silicon nitride film 3 by using a resist pattern 4, having an opening in an area corresponding to element isolation region and a groove of prescribed depth is formed in the semiconductor silicon substrate 1. Then an amorphous silicon film 5 is deposited over the entire surface, the silicon film and semiconductor substrate are oxidized, and a thermally oxidized film is formed on the sidewall of the oxide film 2 and silicon nitride film 3 and the internal wall of the groove. Then a VCD oxide film 7 is charged in the groove.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation region having a trench structure.

[0002]

2. Description of the Related Art With the recent miniaturization of elements, it is necessary to reduce the size of element isolation regions for electrically isolating elements. As the fine separation, a trench separation method in which a groove is formed in a silicon substrate and an insulating film (such as an oxide film) is embedded in the groove is known.

Hereinafter, a conventional trench isolation forming process will be described with reference to FIG.

First, after a silicon oxide film 22 and a silicon nitride film 23 are formed on a silicon substrate 21, a resist 24 is formed.
Is applied, an element isolation formation region is opened by a known photolithography technique, the silicon oxide film 22 and the silicon nitride film 23 are removed by anisotropic dry etching, and a groove 25 is formed in the silicon substrate. (FIG. 3
(A)).

Next, after removing the resist 24, the inside of the groove is thermally oxidized, and then a silicon oxide film 26 is deposited on the entire surface,
Polishing is performed by a P method or a dry etch back method until the silicon nitride film 23 is exposed (FIG. 3B).

Next, the silicon nitride film 23 is removed with hot phosphoric acid, and then the silicon oxide film 22 is removed using an HF solution. Next, when a gate oxide film 22a is formed and a polysilicon film 28 of a gate electrode material is formed, a MOS structure having a trench element isolation structure is obtained (FIG. 3C).

However, the trench isolation structure of the present structure has the following problems.

First, in FIG. 3C, when the silicon oxide film 22 is removed, the buried oxide film recedes and the element end is exposed (reference numeral 30 in FIG. 4). This is because a CVD oxide film is used for filling the element isolation trench, and the CVD oxide film has a higher etching rate with the HF solution than the thermal oxide film, so that a large recession occurs. In this structure, an electric field is concentrated at the end of the element, thereby generating a parasitic transistor and deteriorating the gate oxide film.

Japanese Patent Application Laid-Open No. 7-299 discloses this element end protection.
The technology disclosed in Japanese Patent Publication No. 71 is shown below. JP-A-7-29
In the technique disclosed in Japanese Patent Application Laid-Open No. 971/1997, the end of the element is protected by making the element isolation oxide film T-shaped. FIG. 5 is a view showing the process.

First, a thermal oxide film 1 is formed on a silicon substrate 11.
2. After forming the silicon nitride film 13, the resist 14
After the application, the element isolation formation region is opened by a known photolithography technique, and the oxide film 12 and the silicon nitride film 13 are removed by anisotropic dry etching (FIG. 5).
(A)). Next, after removing the resist 14, a CVD oxide film is deposited on the entire surface, and then the entire surface is removed by dry etching until the silicon substrate 11 is exposed to form a sidewall 15 of the CVD oxide film (FIG. 5B )).

Next, a groove is formed in the substrate by dry etching using the silicon nitride film 13 and the sidewall 15 as a mask (FIG. 5C). Next, a third CVD oxide film 17 is deposited on the entire surface to fill the groove, and then etched back by CMP or dry etching until the silicon nitride film 13 is exposed (FIG. 5D).

[0012]

In the above method, the end of the element is completely protected, so that the parasitic transistor and the oxide film deterioration due to the electric field concentration hardly occur. However, as shown in FIG. 6, it becomes difficult to create a T-type element isolation shape as the element isolation width becomes finer.

If an oxide film sidewall of 0.1 μm on one side is formed in an opening having an element isolation width of 0.25 μm, the groove width becomes 0.05 μm, making etching and embedding very difficult.

An object of the present invention is to provide a method for forming an element isolation region having a shape capable of easily obtaining good element isolation characteristics in forming a fine trench element isolation region.

[0015]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the step of forming an element isolation region on a semiconductor substrate. Forming an oxide film and an oxidation-resistant film, and opening the oxide film and the oxidation-resistant film using a resist pattern in which a region serving as an element isolation region is opened;
Forming a groove of a predetermined depth in the semiconductor substrate, depositing a silicon film on the entire surface, oxidizing the silicon film and the semiconductor substrate, and forming side walls of the oxide film and the oxidation-resistant film and inner walls of the groove; And a step of filling the trench with an insulator.

According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the step of forming an element isolation region on a semiconductor substrate. Forming an oxide film;
A step of opening the oxide film and the oxidation-resistant film using a resist pattern in which a region to be an element isolation region is opened, and forming a groove of a predetermined depth in the semiconductor substrate, and depositing a silicon film on the entire surface; Forming a sidewall made of a silicon film on the side wall of the oxide film and the oxidation-resistant film by etch-back; oxidizing the sidewall and the semiconductor substrate to form a sidewall of the oxide film and the oxidation-resistant film; The method includes a step of forming a thermal oxide film on the inner wall and a step of filling the groove with an insulator.

Further, in the method of manufacturing a semiconductor device according to the present invention, the silicon film is an amorphous silicon film. It is a manufacturing method of.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for forming a semiconductor element isolation region according to the present invention will be described in detail based on an embodiment.

First Embodiment A method for forming a semiconductor element isolation region (NMOS) using the present invention will be described.

First, a silicon oxide film 2 is formed on the surface of a silicon substrate 1 by a heat treatment at 900 ° C. in, for example, an HCl atmosphere to have a thickness of 5 to 20 nm, in this embodiment, 10 nm. 3 = 100
The thickness is deposited to about 300 nm, and in this embodiment, 200 nm. Next, after applying the resist 4, an element isolation formation region is opened by a known photolithography process, and the silicon nitride film 3 is formed by anisotropic dry etching using the resist 4 as a mask.
The silicon oxide film 2 is removed, and the silicon substrate 1 is etched to form a groove (FIG. 1A).

The depth of the groove is 100 to 1000 nm, and in this embodiment, 300 nm. In this embodiment, the groove width is 0.25 μm. Further, the step of forming a groove in the silicon substrate 1 may be performed by removing the silicon nitride film 3 and the silicon oxide film 2 and then removing the resist 4 and using the silicon nitride film 3 as a mask. However, in this case, if the selection ratio is not sufficient, the silicon nitride film 3 becomes thin, and if the uniformity during etching is poor, the remaining film of the SiN film 3 varies. Therefore, when etching the silicon substrate 1, it is desirable that a mask material such as the silicon oxide film 2 be present on the resist 4 or the silicon nitride film 3.

Next, after removing the resist 4, an amorphous silicon film 5 is deposited on the entire surface (5 to 5 by LP-CVD).
(0 nm, 10 nm in this embodiment) (FIG. 1B). Next, thermal oxidation is performed at 900 to 1150 ° C., and the amorphous silicon film 5 and the silicon substrate 1 are oxidized.
A thermal oxide film 6 having a thickness of 100 nm, in this embodiment, 30 nm is formed (FIG. 1C). Here, the silicon film to be deposited is
It may be a polysilicon film or a silicon film crystallized by heat treatment after deposition of an amorphous silicon film. But,
When the purpose is to form a fine element isolation, the thickness of the silicon film is desirably small (50 nm or less). Therefore, an amorphous silicon film having a slow deposition rate is desirably used. next,
A CVD oxide film 7 such as an HDP film or an O ₃ -TEOS film is deposited on the entire surface. In this embodiment, a 700 nm HDP film is deposited (FIG. 1D).

Next, the CVD oxide film 7 is removed by CMP until the silicon nitride film 3 is exposed (FIG. 1).
(E)). Next, the silicon nitride film 3 is removed with hot phosphoric acid, and then ions necessary for adjusting the threshold value of the transistor and forming a well are introduced into the substrate by a known implantation method to form a transistor channel formation region. To form Next, the oxide film 2 is removed with an HF solution (corresponding to 15 nm removal with a thermal oxide film in this embodiment) (FIG. 1F), and then the gate oxide film 8 (thermal oxide film 3 to 10 nm) Then 5n
m), the thickness of the polysilicon film 9 is 1 by LP-CVD.
Deposit about 100 to 400 nm, in this example, 25 nm (FIG. 1G).

After that, known gate electrode processing and impurity doping, formation of source / drain regions, deposition of an interlayer insulating film, contact, and wiring process are performed to form the NMOS Tr. Can be formed. Although the present embodiment is limited to the NMOS, the PMO is not used until the element isolation forming step (removal of the SiN film after the CMP).
The S region is formed in the same manner, and can be applied to the CMOS if the steps required for the CMOS formation are processed thereafter.

Second Embodiment A method for forming a semiconductor element isolation region (NMOS) using the present invention will be described.

First, a silicon oxide film 2 is formed on a surface of a silicon substrate 1, for example, at 900 ° C. in a HCl atmosphere at 5 to 20 nm.
In this embodiment, the silicon nitride film 3 is formed to have a thickness of 10 nm, and then a silicon nitride film 3 is deposited by LP-CVD to a thickness of 100 to 300 nm, and in this embodiment, 200 nm. Next, after the resist 4 is applied, an element isolation formation region is opened by a known photolithography process, and the silicon nitride film 3 and the silicon oxide film 2 are removed by anisotropic dry etching using the resist 4 as a mask.
Further, the silicon substrate 1 is etched to form a groove (FIG. 2A).

The depth of the groove is 100 to 1000 nm, and is 300 nm in this embodiment. In this embodiment, the groove width is 0.25 μm. In the step of forming a groove in the silicon substrate 1, after removing the silicon nitride film 3 and the silicon oxide film 2,
The resist 4 may be removed, and the silicon nitride film 3 may be used as a mask. However, in this case, there is a problem that the silicon nitride film 3 becomes thinner if there is not a sufficient selection ratio, and the remaining film of the silicon nitride film 3 varies if the uniformity during etching is poor. Therefore, when etching the silicon substrate, resist,
Alternatively, it is desirable that a mask material such as SiO _{2 be} present on the silicon nitride film 3.

Next, after the resist 4 is removed, an amorphous silicon film 5 is deposited on the entire surface (from 5 to 5 by LP-CVD).
Next, the amorphous silicon film 5 on the entire surface is etched back to form an amorphous silicon film.
A sidewall of the i-film 5 is formed (FIG. 2B). Here, the silicon film to be deposited may be a polysilicon film or a silicon film obtained by subjecting an amorphous silicon film to heat treatment after deposition and crystallized. However, when the purpose is to form a fine element isolation, it is desirable that the silicon film be thin.
0 nm or less), so that an amorphous silicon film having a lower film formation rate is more desirable.

Next, thermal oxidation is performed at 900 to 1150 ° C. to oxidize the side wall made of the amorphous silicon film 5 and the silicon substrate 1 to form a thermal oxide film 6 having a thickness of 10 to 100 nm, in this embodiment, 50 nm. (Figure 2
(C)). Next, C such as an HDP film or an O ₃ -TEOS film is used.
A VD oxide film 7 is deposited on the entire surface, and in this embodiment, an HDP film is deposited to a thickness of 700 nm (FIG. 2D).

Next, the CVD oxide film 7 is removed by CMP until the silicon nitride film 3 is exposed (FIG. 2).
(E)). Next, the silicon nitride film 3 is removed with hot phosphoric acid, and then ions necessary for adjusting the threshold value of the transistor and forming a well are introduced into the substrate by a known implantation method to form a transistor channel formation region. To form Next, the oxide film 2 is removed by an HF solution (corresponding to the removal of 15 nm by a thermal oxide film in this embodiment) (FIG. 2F), and then the gate oxide film 8 (3 to 10 nm by the thermal oxide film) is removed. 5n in the embodiment
m), polysilicon film 9 (100-
400 nm (in this example, 25 nm).
(G)).

Thereafter, an NMOS transistor can be formed by processing the known gate electrode and adding impurities, forming source / drain regions, depositing an interlayer insulating film, contacting and wiring. Note that the present embodiment is limited to the NMOS, but until the element isolation forming step (removal of the SiN film after the CMP),
The PMOS region is formed in the same manner, and can be applied to the CMOS if the processes required for the CMOS formation are processed thereafter. In the second embodiment, the number of steps of etching back the amorphous silicon film 5 is increased as compared with the first embodiment, but the amorphous silicon film 5 on the silicon nitride film 3 can be removed.
An oxide film formed before CMP (an oxide film obtained by oxidizing the amorphous silicon film 5 in the first embodiment + HDP)
Since only the HDP film is used as the film, the polishing amount of the CMP can be reduced, and there is an advantage that the thickness variation of the oxide film can be suppressed.

[0032]

As described above, according to the present invention, the thermal oxide film entirely covers the buried oxide film in the element isolation region. As a result, in the removal of the oxide film in the next step, the etching rate at the end of the element isolation region becomes equal to that of the thermal oxide film, and the retreat of the element isolation region can be suppressed.

Therefore, a thermal oxide film can be formed on the side surface of the film serving as a mask for forming a groove without significantly reducing the width of a groove for embedding an element isolation region, and H in a gate forming step can be formed.
Recession of the device isolation oxide film at the channel end due to F solution or the like can be greatly suppressed as compared with the CVD oxide film alone, and a good channel end shape can be obtained. Performance can be improved.

Further, since the silicon film is deposited on the side surfaces of the isolation trench, the recession of the channel silicon during the side wall oxidation is suppressed, so that the loss of the channel width can be suppressed.

Further, by using the present invention, the oxide film formed on the silicon nitride film before the CMP becomes thin, so that the polishing amount of the CMP can be reduced and the oxide film can be reduced. There is an advantage that thickness variations can be suppressed.

Further, by using the present invention, a thin silicon film is formed, so that miniaturization can be achieved.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a view showing a process of forming a trench element isolation region according to the first prior art;

FIG. 4 is a diagram provided for describing a problem of the first related art.

FIG. 5 is a view showing a process of forming a trench element isolation region according to a second conventional technique.

FIG. 6 is a diagram provided for describing a problem of a second related art.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 oxide film 3 silicon nitride film 4 resist 5 amorphous silicon film 6 thermal oxide film 7 CVD oxide film 8 gate oxide film 9 polysilicon film

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: forming an element isolation region on a semiconductor substrate; forming an oxide film and an oxidation-resistant film on the semiconductor substrate surface; Opening the oxide film and the oxidation-resistant film using the opened resist pattern and forming a groove of a predetermined depth in the semiconductor substrate; and depositing a silicon film on the entire surface, and removing the silicon film and the semiconductor substrate. Manufacturing a semiconductor device, comprising: a step of oxidizing to form a thermal oxide film on a side wall of the oxide film and the oxidation-resistant film and an inner wall of the groove; and a step of filling the groove with an insulator. Method. 2. A method of manufacturing a semiconductor device having a step of forming an element isolation region on a semiconductor substrate, comprising the steps of: forming an oxide film and an oxidation-resistant film on the surface of the semiconductor substrate; Opening the oxide film and the oxidation-resistant film using the opened resist pattern, forming a groove of a predetermined depth in the semiconductor substrate; and depositing a silicon film on the entire surface, and then performing etch-back.
Forming a side wall made of a silicon film on the side wall of the oxide film and the oxidation-resistant film; and oxidizing the side wall and the semiconductor substrate, and thermally oxidizing the side wall of the oxide film and the oxidation-resistant film and the inner wall of the groove. A method for manufacturing a semiconductor device, comprising: forming a film; and filling the trench with an insulator. 3. The method for manufacturing a semiconductor device according to claim 1, wherein said silicon film is an amorphous silicon film.