JPH03196672A - Cmos integrated circuit - Google Patents
Cmos integrated circuitInfo
- Publication number
- JPH03196672A JPH03196672A JP1339612A JP33961289A JPH03196672A JP H03196672 A JPH03196672 A JP H03196672A JP 1339612 A JP1339612 A JP 1339612A JP 33961289 A JP33961289 A JP 33961289A JP H03196672 A JPH03196672 A JP H03196672A
- Authority
- JP
- Japan
- Prior art keywords
- channel mosfet
- oxide film
- gate electrode
- drain
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 230000007257 malfunction Effects 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＣＭＯＳ集積回路に関し、特に３次元デバイス
と称する２層構造のＣＭＯＳ集積回路に間するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS integrated circuit, and particularly to a two-layer CMOS integrated circuit called a three-dimensional device.
従来技術によるＮウェル方式のＣＭＯＳ集積回路につい
て、第３図（ａ）の平面図と、そのＡＢ断面図である第
３図（ｂ）とを参照して説明する。An N-well type CMOS integrated circuit according to the prior art will be described with reference to the plan view of FIG. 3(a) and FIG. 3(b), which is an AB sectional view thereof.
Ｐ型シリコン基板１の表面にＬＯＣＯ３法による絶縁分
離用のフィールド酸化膜２が形成され、Ｎウェル３、ゲ
ート酸化膜４、ポリシリコンからなるゲート電極５が形
成されている。A field oxide film 2 for insulation isolation is formed on the surface of a P-type silicon substrate 1 by the LOCO3 method, and an N well 3, a gate oxide film 4, and a gate electrode 5 made of polysilicon are formed.
Ｐ型シリコン基板１の上にはＮチャネルＭＯＳＦＥＴ用
のＮ＋型ソース−ドレイン６が、ＮウェルにはＰチャネ
ルＭＯ３ＦＥＴ用のＰ１型ソース−ドレイン７が形成さ
れている。An N+ type source-drain 6 for an N-channel MOSFET is formed on a P-type silicon substrate 1, and a P1-type source-drain 7 for a P-channel MO3FET is formed in the N well.
全面に堆積されたＰＳＧ膜８の開口に埋め込まれたタン
グステン１１を通してアルミニウム配線１２が形成され
、それぞれのゲート電極５ａと５ｂとが接続されてイン
バータ、ＮＡＮＤ、ＮＯＲとなる基本回路を構成してい
る。Aluminum wiring 12 is formed through tungsten 11 embedded in the opening of the PSG film 8 deposited on the entire surface, and the respective gate electrodes 5a and 5b are connected to form a basic circuit that becomes an inverter, NAND, and NOR. .
従来技術によるＣＭＯＳ集積回路においては、Ｎチャネ
ルＭＯ８ＦＥＴとＰチャネルＭＯ３ＦＥＴとを同一平面
内に形成しているため、チップ面積が大きくなり、集積
度を上げるのが難しい。In a conventional CMOS integrated circuit, an N-channel MO8FET and a P-channel MO3FET are formed in the same plane, which increases the chip area and makes it difficult to increase the degree of integration.
またゲート電極の配線を第３図（ａ）のように直線で引
き伸ばすと、ＮチャネルＭＯ８ＦＥＴのゲート抵抗が大
きくなり、動作速度が遅くなる。Furthermore, if the gate electrode wiring is stretched in a straight line as shown in FIG. 3(a), the gate resistance of the N-channel MO8FET increases and the operation speed becomes slower.
さらに平面配置のＣＭＯ３集積回路では、ＰＮＰＮ構造
が避けられないので、ラッチアップ現象による誤動作が
生じる恐れがある。Furthermore, since a PNPN structure is unavoidable in a planar CMO3 integrated circuit, malfunctions may occur due to a latch-up phenomenon.
本発明のＣＭＯ３集積回路は、半導体基板表面に形成さ
れた第１のＭＯＳＦＥＴの上に堆積された、島状または
環状の半導体層に第１のＭＯＳＦＥＴとゲート電極を共
有する第２のＭＯＳＦＥＴが形成され、第１のＭＯＳＦ
ＥＴのソース−トレインと配線との接続部には前記半導
体層が堆積されていないものである。In the CMO3 integrated circuit of the present invention, a second MOSFET sharing a gate electrode with the first MOSFET is formed in an island-shaped or ring-shaped semiconductor layer deposited on a first MOSFET formed on the surface of a semiconductor substrate. and the first MOSF
The semiconductor layer is not deposited at the connection portion between the source-train of the ET and the wiring.
本発明の第１の実施例について、第１図（ａ）の平面図
、そのＡ−Ｂ断面図である第１図（ｂ）とＣ−Ｄ断面図
である第１図（ｃ）とを参照して説明する。Regarding the first embodiment of the present invention, the plan view of FIG. 1(a), FIG. 1(b) which is a cross-sectional view of FIG. 1(a), and FIG. 1(c) which is a cross-sectional view of FIG. Refer to and explain.
はじめに不純物濃度Ｉ Ｘ １０１５ｃｍ−’のＰ型シ
リコン基板１に、ＬＯＣＯ３法により厚さ０．６〜０．
８μｍのフィールド酸化膜２を形成してから、厚さ１０
〜３０ｎｍのゲート酸化膜４を形成し、厚さ０．４μｍ
のゲート電極５を形成する。First, a P-type silicon substrate 1 with an impurity concentration I x 1015 cm-' is coated with a thickness of 0.6 to 0.0 cm by the LOCO3 method.
After forming a field oxide film 2 of 8 μm, a thickness of 10 μm is formed.
Form a gate oxide film 4 of ~30 nm and a thickness of 0.4 μm
A gate electrode 5 is formed.
つぎに砒素イオンを加速エネルギー７０ｋｅ■、注入量
（ドース）１×１０１５〜１×１０１６ｃｍ −２注入
してゲート電ｆ！５とセルファラインとなったＮ′型ソ
ース−ドレイン６を形成してＮチャネルＭＯ３ＦＥＴが
完成する。Next, arsenic ions are implanted at an acceleration energy of 70 ke■ and an implantation amount (dose) of 1 x 1015 to 1 x 1016 cm-2, and the gate voltage is f! 5 and an N' type source-drain 6 which becomes a self-line, and an N-channel MO3FET is completed.
つぎにシリカフィルムなどの有機シリコン化合物を塗布
し、熱処理によって酸化膜（Ｓ ｉ ０２ ）８に変化
させてリフロー平坦化する。Next, an organic silicon compound such as a silica film is coated, and it is changed into an oxide film (S i 02 ) 8 by heat treatment, and then flattened by reflow.
この場合５ｉ０２の厚さは、ゲート電極５の外側で０．
８μｍ以上が必要である。In this case, the thickness of 5i02 outside the gate electrode 5 is 0.
A thickness of 8 μm or more is required.
つぎにＲＩＥ法によりポリシリコン電極５が露出するま
でエッチバックしてがら、熱酸化により表面に厚さＩＯ
〜３０ｎｍのゲート酸化膜４を形成する。Next, while etching back until the polysilicon electrode 5 is exposed using the RIE method, a thickness of IO is formed on the surface by thermal oxidation.
A gate oxide film 4 of ~30 nm is formed.
この上にＭＢＥ （分子線エピタキシャル）法により、
厚さ０．５μｍ、不純物濃度１×１Ｏ１５〜Ｉ Ｘ １
０”ｃｍ−’のＮ型半導体層９を成長させる。On top of this, by MBE (molecular beam epitaxial) method,
Thickness 0.5μm, impurity concentration 1×1O15~IX1
An N-type semiconductor layer 9 of 0"cm-' is grown.
つぎに硼素イオンを加速エネルギー２０〜５０ｋｅＶ、
注入ｉｔ（ドース）ＩＸ１０１５〜ｌＸｌ０”ｃｍ−２
注入して、Ｐ＋型ソース−ドレイン７を形成し、Ｎチャ
ネルＭＯ３ＦＥＴのソース−ドレインと配線との接続部
１３のＮ型半導体層９をエツチング除去することにより
ＰチャネルＭＯ３ＦＥＴが完成する。Next, the boron ions are accelerated at an energy of 20 to 50 keV.
Injection it (dose) IX1015~lXl0”cm-2
The P+ type source-drain 7 is formed by implantation, and the N-type semiconductor layer 9 at the connection portion 13 between the source-drain of the N-channel MO3FET and the wiring is removed by etching, thereby completing the P-channel MO3FET.
最後にＰＳＧ膜１０を形成してから、タングステン１１
を埋め込んでアルミニウム配線１２を形成する。Finally, after forming the PSG film 10, the tungsten film 11 is
The aluminum wiring 12 is formed by embedding.
ここでＮ型半導体層９は、ＣＶＤ法によりポリシリコン
を堆積してから、レーザーアニールにより単結晶化する
ことにより形成することもできる。Here, the N-type semiconductor layer 9 can also be formed by depositing polysilicon by a CVD method and then converting it into a single crystal by laser annealing.
また不要のＮ型半導体層９をエツチング除去する替りに
、ＬＯＣＯ８法により熱酸化して絶縁性の５ｉｎ２に変
える方法もある。Furthermore, instead of removing the unnecessary N-type semiconductor layer 9 by etching, there is also a method of thermally oxidizing it using the LOCO8 method and changing it to an insulating 5in2 layer.
つぎに本発明の第２の実施例について、第２図（ａ＞の
平面図、そのＡ−Ｂ断面図である第２図（ｂ）５とＣ−
ＤＩ７ｒ面図である第２図（ｃ）とを参照して説明する
。Next, regarding the second embodiment of the present invention, FIG. 2(a) is a plan view, and FIG.
This will be explained with reference to FIG. 2(c) which is a DI7r plane view.
この実施例ではゲート電極５が環状になっており、Ｎチ
ャネルＭＯ８ＦＥＴのソースまたはドレインの配線との
接続部１３でＮ型半導体層９に開口が形成されている。In this embodiment, the gate electrode 5 has an annular shape, and an opening is formed in the N-type semiconductor layer 9 at a connecting portion 13 to the source or drain wiring of the N-channel MO8FET.
ゲート電極５が環状なので、それぞれのＭＯＳＦＥＴの
ソース−トレイン間リーク電流を低減する効果がある。Since the gate electrode 5 is annular, it has the effect of reducing source-train leakage current of each MOSFET.
本発明によるＣＭＯ３集積回路においては、Ｎチャネル
ＭＯＳ Ｆ ＥＴの上にＰチャネルＭＯ８ＦＥＴを立体
的に積層しているため、チップ面積を縮小して集積度を
上げることができた。In the CMO3 integrated circuit according to the present invention, since the P-channel MO8FET is three-dimensionally stacked on the N-channel MOSFET, the chip area can be reduced and the degree of integration can be increased.
またＮチャネルＭＯ８ＦＥＴとＰチャネルＭＯ３ＦＥＴ
とでゲート電極を共有しているので、ゲ−ト抵抗が小さ
くなり、動作速度が向上した。Also, N-channel MO8FET and P-channel MO3FET
Since the gate electrode is shared by both, the gate resistance is reduced and the operating speed is improved.
さらに立体配置のＣＭＯ８集積回路では、ＰＮＰＮ構造
がなくなり、ラッチアップ現象を解消することができた
。Furthermore, the 3D CMO8 integrated circuit eliminates the PNPN structure, making it possible to eliminate the latch-up phenomenon.
第１図（ａ）は本発明の第１の実施例を示す平面図、第
１図（ｂ）はそのＡ−Ｂ断面図、第１図（ｃ）はそのＣ
−Ｄ断面図、第２図（ａ）は本発明の第２の実施例を示
す平面図、第２図（ｂ）はそのＡ−Ｂ断面図、第２図（
ｃ）はそのＣ−Ｄ断面図、第３図（ａ＞は従来技術を示
す平面図、第３図（ｂ）はそのＡ−Ｂ断面図である６１
・・・Ｐ型シリコン基板、２・・・フィールド酸化膜、
３・・・Ｎウェル、４・・・ゲート酸化膜、５．５ａ５
ｂ・・・ゲート電極、６・・・Ｎ＋型ソース−ドレイン
、７・・・Ｐ”型ソース−ドレイン、８・・・酸化膜、
９・・・Ｎ型半導体層、１０・・・ＰＳＧ膜、１１・・
・タングステン、１２・・・アルミニウム配線、１３・
・・接続部。FIG. 1(a) is a plan view showing the first embodiment of the present invention, FIG. 1(b) is a sectional view taken along line A-B, and FIG. 1(c) is a cross-sectional view taken along line C.
2(a) is a plan view showing the second embodiment of the present invention, FIG. 2(b) is a sectional view taken along line A-B, and FIG.
c) is a sectional view taken along the line CD, FIG. 3(a) is a plan view showing the prior art, and FIG.
...P-type silicon substrate, 2...field oxide film,
3... N well, 4... Gate oxide film, 5.5a5
b... Gate electrode, 6... N+ type source-drain, 7... P'' type source-drain, 8... Oxide film,
9... N-type semiconductor layer, 10... PSG film, 11...
・Tungsten, 12... Aluminum wiring, 13.
・Connection part.
Claims (1)
ース−ドレインからなる第１のＭＯＳＦＥＴの上に堆積
された、島状または環状の半導体層に第１のＭＯＳＦＥ
Ｔとゲート電極を共有する第２のＭＯＳＦＥＴが形成さ
れ、第１のＭＯＳＦＥＴのソース−ドレインと配線との
接続部には前記半導体層が堆積されていないことを特徴
とするＣＭＯＳ集積回路。A first MOSFET is formed on an island-shaped or annular semiconductor layer deposited on a first MOSFET consisting of a source-drain of a second conductivity type formed on the surface of a first conductivity type semiconductor substrate.
A CMOS integrated circuit characterized in that a second MOSFET sharing a gate electrode with T is formed, and the semiconductor layer is not deposited at a connection portion between the source-drain of the first MOSFET and a wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1339612A JPH03196672A (en) | 1989-12-26 | 1989-12-26 | Cmos integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1339612A JPH03196672A (en) | 1989-12-26 | 1989-12-26 | Cmos integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03196672A true JPH03196672A (en) | 1991-08-28 |
Family
ID=18329140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1339612A Pending JPH03196672A (en) | 1989-12-26 | 1989-12-26 | Cmos integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03196672A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006109287A (en) * | 2004-10-08 | 2006-04-20 | Alps Electric Co Ltd | Surface acoustic wave element and manufacturing method thereof |
| JP2009105407A (en) * | 2007-10-24 | 2009-05-14 | Chun-Chu Yang | Coaxial transistor structure |
-
1989
- 1989-12-26 JP JP1339612A patent/JPH03196672A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006109287A (en) * | 2004-10-08 | 2006-04-20 | Alps Electric Co Ltd | Surface acoustic wave element and manufacturing method thereof |
| JP2009105407A (en) * | 2007-10-24 | 2009-05-14 | Chun-Chu Yang | Coaxial transistor structure |
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