JPH03203366A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent mutual diffusion of impurities contained in gates, by isolating silicide of gate upper layers of two MOSFET's constituting a CMOSFET by using an intermediate connection part of the gates of the respective MOSFET's. CONSTITUTION:On a P-type semiconductor substrate, an N-well 2 is formed for a P-channel MOS transistor(MOST) region 1. An adjacent P-type substrate region is for an N-channel MOST 3. In order to make both channel regions a CMOST constitution, the same polycrystalline Si layers are stretched and made input gates. Titanium silicide is formed on the upper layers of the regions turning to, at least, a first gate electrode 4 of the MOST 1 part and a second gate electrode 5 of the MOST 2 part out of the input gate polycrystalline silicon. Thus gate electrodes of polycide structure is constituted. An input Al wiring 6 is connected to the contact point (common gate input contact part 7) of electrodes 4, 5. Said contact part 7 is made a boundary, and the upper layer silicide of the electrodes 4, 5 is isolated and formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, particularly a surface channel type 0M semiconductor device.
This relates to an O8 transistor.

[Conventional technology]

In the conventional 0MO8 transistor, phosphorous-doped N" type polycrystalline silicon was used for the gate electrodes of both the N-channel and P-channel transistors, so the P-channel transistor became a buried channel type, making it difficult to shorten the channel. There was a problem.

In response to this, various studies have been conducted to shorten the channel by using P+ type polycrystalline silicon for the gate electrode of a P-channel MO8 transistor to achieve surface channel type operation. In this case, the manufacturing method for the 0MO8 transistor is to implant high-dose ions into the source and drain regions of the non-doped polycrystalline silicon gate, thereby converting the gate of the N-channel transistor into an N'' type and converting the gate of the P-channel transistor into an N'' type. Gate P
After doping to + type, a method is often used in which the gate and diffusion layer are silicided in order to lower the resistance of the gate electrode.

[Problem to be solved by the invention]

In the above-mentioned conventional inverter consisting of surface channel type 0MO8 transistors, the gate of the N-channel transistor and the gate of the P-channel transistor are connected by silicide, but since the diffusion coefficient of impurities in the silicide is very large, the N-channel transistor Arsenic (As) contained in the gate of... :, there is a problem that poron (B) contained in the gate of a P-channel transistor interdiffuses, and B enters the gate of an N-channel transistor or As enters the gate of a P-channel transistor. It has the disadvantage of deteriorating the characteristics of

[Means to solve the problem]

In the 0MO8 transistor of the present invention, one end of the same polycrystalline silicon layer is doped to N+ type to serve as the gate of the N channel transistor, and the other end of this polycrystalline silicon layer is doped to P+ type to form the gate of the P channel transistor. C which serves as a gate and has silicide formed on the upper layer of the polycrystalline silicon layer in at least each transistor region.
In a MOS transistor, silicide layers above the gates of an N-channel transistor and a P-channel transistor are spaced apart from each other. Furthermore, these silicides provided at a distance are connected to the same gate input signal line. With this configuration, impurities doped in the gate polycrystalline silicon of both N-channel and P-channel transistors diffuse into each other's gate polycrystalline silicon layers via the silicide while maintaining the low resistance of the gate electrode. It is possible to realize an 0MO8 transistor with a cut-off path.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

As shown in FIG. 1, an N well 2 is provided in a predetermined region of a P-type semiconductor substrate, and this is connected to a P-channel MOS transistor (
Region 1 (hereinafter abbreviated as P-channel MO8T). Further, the adjacent P-type substrate region is an N-channel MO8 transistor (hereinafter abbreviated as N-channel MO8T) region 3. These P channel and N channel MO8T regions are CM
In order to form an OS transistor configuration, the same polycrystalline silicon layer is extended and used as an input gate. Of this input gate polycrystalline silicon, titanium silicide (for convenience of explanation, it is not shown in FIG. (hatched) is formed, forming a gate electrode with a polycide structure. An input aluminum wiring 6 to which a gate input signal is transmitted is connected to a tangent point between both gate electrodes 4 and 5 (common gate input contact portion 7). The upper layer silicide of the first gate electrode 4 and the second gate electrode 5 are provided spaced apart from each other with this common gate input contact portion 7 as a boundary. In other words, the common gate electrode is made of the same polycrystalline silicon layer 8. After forming, the areas other than the intermediate regions of the P-channel and N-channel MO3T are silicided.Then, in the common gate input terminal section 7, the input aluminum wiring 6 is formed by silicide of the first gate electrode 4 and the second gate electrode 5. It is also connected to the lower polycrystalline silicon layer 8 in the intermediate region between the two.

Further, on both sides of these gate electrodes 4.5, there are M
A source and a drain/in which constitute the O8T are provided, and the source region of the P-channel MO8TI is connected to the power supply potential (
VCC) aluminum wiring 9, the source region of N-channel MO8T2 is connected to ground potential (GND) aluminum wiring 10, and the drain regions of P-channel and N-channel MO8TI, 2 are connected to output aluminum wiring 11 through contact holes 12. Connected.

The configuration of this embodiment will be explained in more detail with reference to FIGS. 2 and 3.

Phosphorus (P) is implanted into the P-channel MO8T formation region of the P-type semiconductor substrate 210 using phosphorography technology.
An N well is formed by performing heat treatment at a high temperature of about 0°C. Next, using a known selective oxidation method, a field oxide film 2 of about 600 nm is formed on the substrate 21 region other than the active region.
form 2.

After forming a gate oxide film 3 of about 20 nm on the entire surface, undoped polycrystalline silicon is grown to a thickness of about 300 nm and patterned using lithography and etching techniques to form a gate polycrystalline silicon electrode 24.

As shown in Fig. 2, P is added to the N-channel MO8T formation region.
After implanting about 1013 an-'' of X to shorten the channel, an oxide film is grown to a thickness of about 200 nm over the entire surface.

Next, using phosphorography, we created an N-channel MO as shown in Fig. 3.
Part of the connecting part between the gate of 8T and the gate of P-channel MO8T (exposed part of lower polycrystalline silicon layer 8 in Fig. 1)
After coating the top with a resist, the entire surface is etched back to form a sidewall oxide film 25 on the gate of the transistor.

Subsequently, titanium (Ti) is sputtered to a thickness of about 60 nm over the entire surface and heat treated at a temperature of about 600° C. to cause the diffusion layer and polycrystalline silicon to react with Ti, thereby forming Ti silicide 26. At this time, the oxide film and Ti
does not react, so P channel MO8T and N channel M
The gate polycrystalline silicon layer between O8Ts is not silicided.

As in N-channel MO3T region, P-channel MO3T
The gate, source, and drain of the N-channel transistor are doped to N+ type, and the gate, source, and drain of P-channel transistor are doped to P'' type by implanting B into each region at a dose of about 5×10 ″cm−′.

Thereafter, the interlayer insulating film 27 is lengthened, a contact hole is opened, and the aluminum wiring 28 is patterned.
A MOS inverter is manufactured.

Here, as shown in FIG. 3, in the common gate input contact section, the input aluminum wiring 28 is commonly connected to each of the ends of the silicide in the upper layer of the gate electrode of the N-channel MO8T and the silicide in the upper layer of the gate electrode of the P-channel MO8T. Therefore, it is possible to prevent the wiring resistance of the gate electrode from increasing. Also, N channel MO8T and P channel MO
Since the silicides in the upper layer of the 8T gate electrode are provided apart from each other, the phenomenon in which As and B doped in the respective gate electrodes diffuse into each other through the silicides is suppressed.

FIG. 4 is a plan pattern diagram of a second embodiment of the present invention. In this embodiment, the gate electrode of the N-channel MO8T and the gate electrode of the P-channel MO8T are connected to the input aluminum wiring through different contact holes, respectively, and
Compared to the previous embodiment, since the entire surface is connected to the silicide layer above the gate electrode, there is an advantage that the contact resistance can be reduced.

〔Effect of the invention〕

As explained above, the present invention is a surface channel type CMO.
At the connection point between the gate of the N-channel MO8T and the gate of the P-channel MO8T constituting the S inverter, the silicides provided on the upper layer of each gate to reduce the resistance of the gate wiring are separated, so that impurities contained in the gate are It is possible to prevent mutual diffusion through the silicide, and there is an effect that the P channel MO3T can be made into a short channel.

[Brief explanation of drawings]

FIG. 1 is a plane pattern diagram of the first embodiment of the present invention;
The figure is a cross-sectional view taken along line A-A' in Figure 1. Figure 3 is B in Figure 1.
-B' line sectional view FIG. 4 is a plan pattern diagram of the second embodiment 2 of the present invention. l...P channel MO8 transistor, 2...
...N well, 3...N channel MO8 transistor, 4...First gate electrode, 5...
...Second gate electrode, 6...Input aluminum wiring,
7... Common gate input contact section, 8...
...Polycrystalline silicon layer, 9...Mountain/■OC aluminum wiring, 10...GND aluminum wiring L11...Output aluminum wiring, 12...Contact hole, 21...
・P-type semiconductor substrate, 22...Field oxide film, 23...Gate oxide film, 24...Gate polycrystalline silicon electrode, 25...Side wall oxidation Film, 26...Ti reside, 27...
Interlayer insulating film, 28...aluminum electrode. No.! Figure 2 Sen type 7

Claims (1)

[Claims] A first MOS transistor consisting of a polycrystalline silicon gate, source and drain diffusion layers of the same conductivity type as the substrate on a semiconductor substrate of one conductivity type, and a polycrystalline silicon gate and source and drain diffusion layers of the opposite conductivity type to the substrate. In the semiconductor device, the semiconductor device includes a second MOS transistor consisting of a layer, the gates of the first and second MOS transistors are connected to each other, and an upper layer of the gate is silicided with a high melting point metal. 1. A semiconductor device characterized in that silicide layers above the gates of two MOS transistors are provided spaced apart from each other at an intermediate connection between the gates of the respective MOS transistors.