JP3008599B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a capacitor formed on a semiconductor substrate.

[0002]

2. Description of the Related Art FIGS. 4A and 4B show a conventional semiconductor device.
As shown in FIG. 3, a P-type polycrystalline silicon film 3 selectively provided on a silicon oxide film 2 provided on a silicon substrate 1 and serving as a lead portion of a first capacitance electrode; A silicon oxide film 4 having a contact opening 5 provided on the surface including the silicon oxide film 4 and a first capacitor electrode 11 provided on the silicon oxide film 4 connected to the polycrystalline silicon film 3 in the opening 5
A silicon nitride film 8 provided on a surface including the first capacitor electrode to serve as a capacitor insulating film;
Second capacitance electrode 12 provided opposite to the first capacitance electrode 11
To form a capacitor.

Here, the first capacitor electrode 11 has a side wall substantially perpendicular to the silicon substrate 1, and the side wall and the upper surface are effective portions of the capacitor electrode.

[0004]

As the degree of integration of semiconductor devices increases, it is necessary to reduce the size of the capacitors on the semiconductor devices. However, since the capacitance value of the capacitors is proportional to the surface area of the capacitance electrodes, the above-mentioned conventional technology is not suitable. In a semiconductor device, when a capacitor is miniaturized, a required capacitance value cannot be obtained, and there is a problem that a degree of integration cannot be increased.

[0005]

According to the present invention, there is provided a semiconductor device comprising:
The side wall and the outer periphery of a stacked block in which polycrystalline silicon films having different etching rates are alternately and sequentially stacked on a semiconductor substrate.
Formed from the top of the laminated block to the middle of lamination
A first capacitor electrode having fold-like irregularities provided on a side wall of the hole ;
A capacitor insulating film provided on a surface including the first capacitor electrode;
A second capacitor electrode provided so as to face the first capacitor electrode via the capacitor insulating film.

According to the method of manufacturing a semiconductor device of the present invention, two kinds of polycrystalline silicon films containing impurities having different concentrations or different kinds of impurities are alternately and sequentially laminated on a semiconductor substrate and then selectively anisotropically formed. Forming a block of a laminated structure by reactive etching, and laminating from the top of the laminated block
Forming a hole halfway through, and thinly etching the surface of the block including the inside of the hole with an etching solution having different etching rates to the two types of polycrystalline silicon films. Outer side wall of the block and the hole
Forming a first capacitor electrode having a fold-like unevenness on a side wall of the first capacitor electrode, forming a capacitor insulating film on a surface including the first capacitor electrode, and including an impurity on a surface of the capacitor insulating film. Depositing and patterning a polycrystalline silicon film to form a second capacitor electrode opposed to the first capacitor electrode via the capacitor insulating film.

[0007]

Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1C and FIG. 2 relate to the present invention.
FIG. 7 is a cross-sectional view of a semiconductor chip shown in a process order for describing a manufacturing method of a related technique ;

First, as shown in FIG. 1A, a silicon oxide film 2 is formed to a thickness of 0.2 μm on a silicon substrate 1, and a P-type polycrystalline silicon film 3 is formed on the silicon oxide film 2.
Is deposited to a thickness of 0.2 μm and selectively oxidized to form a lead portion of the first capacitor electrode. Next, a silicon oxide film 4 is deposited to a thickness of 50 nm on the surface including the P-type polycrystalline silicon film 3 to selectively open the P-type polycrystalline silicon film 3, and a contact opening 5 is formed. Form.

Next, as shown in FIG.
Containing 0.1 × 10 ²¹ cm ⁻³ of boron on the surface containing 0.1
μm P ⁺ type polycrystalline silicon film 6 and boron
P ^- type polycrystalline silicon films 7 having a thickness of 0.1 μm including ¹⁷ cm ⁻³ are alternately and sequentially stacked, and a P ^- type polycrystalline silicon film 7 having a thickness of 0.15 μm is formed on the uppermost layer.
^{A +} -type polycrystalline silicon film 6 is formed and selectively etched sequentially to form a P ⁺ -type polycrystalline silicon film 6 and a P ⁻ -type polycrystalline silicon film 7 connected to the P-type polycrystalline silicon film 3 in the opening 5. A laminated block is formed.

Next, as shown in FIG. 1C, the surface of the laminated block is etched with a caustic potassium (KOH) solution or a hydrazine solution, and the higher the concentration of boron contained in the polycrystalline silicon film, the more these etchings are performed. Utilizing the property that the etching rate by the liquid is reduced, the P − -type polycrystalline silicon film 7 on the side wall of the laminated block is deeply etched to provide fold-like irregularities, thereby forming the first capacitor electrode. Here, boron may be added to and diffused in the stacked block having the unevenness on the surface, and there is an advantage that the resistance of the first capacitor electrode can be reduced. Instead of changing the impurity concentration, polycrystalline silicon films having different types of impurities (for example, boron and phosphorus) may be stacked.

Next, as shown in FIG. 2, a silicon nitride film 8 is deposited to a thickness of 10 nm on the surface including the stacked blocks by low pressure chemical vapor deposition (LPCVD) to form a capacitor insulating film. Next, a P-type polycrystalline silicon film 9 is deposited on the silicon nitride film 8 to a thickness of 0.25 μm and patterned to form a second capacitor electrode. Next, the silicon nitride film 8 and the silicon oxide film 4 are selectively etched sequentially to form an opening 10 for leading out a first capacitor electrode.

FIG. 3 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention.

As shown in FIG. 3, after a laminated block is formed in the same process as in FIG. 1 , holes are provided from the top of the laminated block to the middle of the lamination, and the surface of the laminated block is etched to form a side wall of the laminated block. It has the same configuration as in FIGS. 1 and 2 except that fold-like unevenness is provided on the side wall of the hole. There is an advantage that the capacitance of the capacitor can be increased because the surface area of the first capacitance electrode is further increased.

[0015]

As described above, according to the present invention, the surface area can be increased by providing fold-like irregularities on the side wall of the capacitor electrode, whereby the capacitance of the capacitor can be increased and the capacitor can be substantially manufactured. This has the effect that the size can be reduced and the degree of integration of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip shown in the order of steps for explaining a method of manufacturing a technique related to the present invention.

FIG. 2 is a cross-sectional view of the semiconductor chip, showing the steps subsequent to FIG . 1 in the order of steps;

FIG. 3 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention.

FIG. 4 is a plan view and a cross-sectional view taken along line AA ′ of a semiconductor chip showing an example of a conventional semiconductor device.

[Explanation of symbols]

1 silicon substrate 2 and 4 a silicon oxide film 3, 9 P-type polycrystalline silicon film 5, 10 opening 6 P ⁺ -type polycrystalline silicon film 7 P ^- -type polycrystalline silicon film 8 a silicon nitride film 11, 12 capacitor electrodes

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 27/04 H01L 27/10

Claims (2)

(57) [Claims] 1. A laminated block in which polycrystalline silicon films having different etching rates are alternately and sequentially laminated on a semiconductor substrate.
During lamination from the outer peripheral side wall and the upper part of the laminated block
Having a fold-like unevenness provided on the side wall of the hole formed up to
A capacitor electrode, a capacitor insulating film provided on a surface including the first capacitor electrode, and a second capacitor electrode provided so as to face the first capacitor electrode via the capacitor insulating film. A semiconductor device characterized by the above-mentioned. 2. A block having a stacked structure, in which two types of polycrystalline silicon films containing different concentrations of impurities or different types of impurities are alternately and sequentially laminated on a semiconductor substrate and then selectively anisotropically etched. Forming the laminate,
A step of forming a hole from the top of the lock to the middle of the lamination,
The surface of the block including the inside of the hole is thinly etched with an etching solution having an etching rate different from that of the two types of polycrystalline silicon films to the outside of the block.
A first side in which fold-like irregularities are provided on a peripheral side wall and a side wall of the hole;
Forming a capacitor electrode, forming a capacitor insulating film on the surface including the first capacitor electrode, and depositing and patterning a polycrystalline silicon film containing impurities on the surface of the capacitor insulating film to form the capacitor. Forming a second capacitance electrode facing the first capacitance electrode with an insulating film interposed therebetween.