JPH06120445A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method capable of manufacturing a semiconductor device including the capacitor having a large capacity with a small number of easy processes. CONSTITUTION:On the surface of a silicon substrate 1, a diffusion region 6 and gate electrodes 4, 5 are formed, and using a reduced-pressure CVD method, a non-doped polysilicon layer 8 is so deposited that the lower part thereof is connected with the diffusion region 6. Then, in the same reduced-pressure CVD method, a polysilicon layer 9 doped with phosphorus by about 5X10<20>atm/ cm<3> is deposited thereon. These depositions are repeated, and a multilayer film comprising five layers is formed. The multilayer film is etched using an RIE method, and a sidewall surface is formed on the multilayer film, and thereby, an underside electrode 11 is formed. Further, using the solution of HF:HNO3: CH3COOH=1:3:8, a wet etching is applied to the underside electrode 11. Thereby, since the etching rates of the polysilicon layers 8, 9 are different from each other, recessed parts are formed on the sidewall surface of the underside electrode 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a capacitor.

[0002]

2. Description of the Related Art Recently, a stacked capacitor type DRAM composed of a transistor and a capacitor has been required to be highly integrated. As the memory cell area is reduced accordingly, the electrode area of the capacitor is also reduced. As a countermeasure against this, a laminated semiconductor memory device in which an electrode of a capacitor is laminated above a gate electrode is known.

FIG. 1 is a schematic sectional view showing the structure of a conventional stacked type semiconductor memory device. This semiconductor memory device is manufactured as follows. First, the field oxide film 32 is formed on the silicon substrate 31, and the diffusion region 36 is formed on the surface of the silicon substrate 31 by ion implantation. Gate electrodes 34 and 34 to be word lines are formed on the insulating film 37 and the field oxide film 32 on the silicon substrate 31, and the surfaces of the gate electrodes 34 and 34 are covered with the insulating film 37. Doped polysilicon is deposited on the insulating film 37 so that its lower portion is connected to the diffusion region 36. Then, the memory electrode 38 is formed so that the upper portion is formed above the gate electrodes 34, 34. And the memory electrode 38
The surface of is covered with a capacitive dielectric film 39. In addition, capacitive dielectric film
Polysilicon is deposited on the surface of 39 to form the cell plate 30.

The semiconductor memory device thus formed is
A transistor including the gate electrode 34 and the diffusion region 36,
A memory cell is composed of the storage electrode 38, the capacitor dielectric film 39, and the capacitor including the cell plate 30.

A stacked semiconductor memory device having a fin structure in which the cell plate 30 is sandwiched between the side surfaces of the memory electrode 38 to increase the surface area of the cell plate 30 is also known. FIG. 2 is a schematic cross-sectional view showing a stacked semiconductor memory device having a fin structure. This semiconductor memory device is manufactured as follows. The process of forming a transistor on the silicon substrate 31 is shown in FIG.
The semiconductor memory device shown in FIG. Gate electrode 34, 34
Then, the surface of the gate electrodes 34, 34 is covered with an insulating film 37, and the polysilicon 38 doped on the gate electrodes 34, 34 is formed.
a is deposited so that its lower portion is connected to the diffusion region 36. An oxide film is deposited on the polysilicon 38a, a polysilicon 38b is deposited on the oxide film, and this is repeated. Then, two holes are formed above the diffusion region 36, polysilicon is deposited, and polysilicon 38a sandwiched between oxide films is formed.
38b… Make contact between. And polysilicon 38
Etching is performed so that a laminated portion of the oxide film and the oxide film is formed above the gate electrodes 34 and 34 and a hole is formed above the diffusion region 36. After that, when the oxide film is removed, the remaining polysilicon 38a, 38b ... Becomes the memory electrode 38 having a shape in which a groove is provided on its side surface. A capacitive dielectric film 39 made of a nitride film is formed on the surface of the memory electrode 38, and the surface is covered with a cell plate 30 made of polysilicon to form a semiconductor memory device having a fin structure.

[0006]

The semiconductor memory device thus formed has a larger storage capacity than the stacked type semiconductor memory device shown in FIG. 1 because of the large surface area of the capacitor electrodes. However, there is a problem that many complicated steps are required for manufacturing the semiconductor memory device having the fin structure.

As a measure against this, there has been proposed a method of manufacturing a semiconductor memory device in which a storage electrode made of polycrystalline silicon having the maximum impurity concentration in the intermediate layer portion is formed and a recess is provided on the side surface of the storage electrode 38. (Japanese Patent Laid-Open No. 3-14
8860 publication). By this method, the capacitor electrode can be formed in a simplified process as compared with the fin-type semiconductor memory device shown in FIG. 2 described above, but the side surface of the memory electrode has a structure in which the intermediate portion is largely recessed. However, there is a problem that the surface area of the capacitor electrode is smaller than that shown in FIG.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device including a capacitor having a large capacitance with ease and in a small number of steps.

[0009]

In the method of manufacturing a semiconductor device according to the present invention, the etching rate is different in the method of manufacturing a semiconductor device in which a lower electrode of a capacitor is in contact with a diffusion region formed in a semiconductor substrate. The method includes a step of forming a multilayer film by laminating at least two kinds of films in multiple layers to form the lower electrode, and a step of performing isotropic etching to form a plurality of recesses on a side surface of the multilayer film. It is characterized by

[0010]

In the method of manufacturing a semiconductor device of the present invention, by laminating a plurality of films having different etching rates and performing isotropic etching on the films, the side surface of the film having a high etching rate of the lower electrode is etched. A plurality of recesses are formed by etching deeper than the side surface of the film having a low rate. Due to this recess, the surface area of the lower electrode can be increased.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. 3 to 6 are schematic cross-sectional views showing the structure of a semiconductor memory device manufactured by the method of the present invention at the formation stage. To manufacture a semiconductor memory device by the method of the present invention, first, as shown in FIG. 3, a field oxide film 2 is formed on a silicon substrate 1, and a diffusion region 6 is formed on the surface of the silicon substrate 1 by ion implantation. Gate electrodes 4 and 5 functioning as word lines are formed on the insulating film 7 and the field oxide film 2 on the silicon substrate 1. The surfaces of the gate electrodes 4 and 5 are covered with the silicon oxide film 7 and etched. The silicon oxide film 7 on the diffusion region 6 is removed. The gate electrode 5 is a word line of an adjacent memory cell on the silicon substrate 1.

Then, a 100 nm non-doped polysilicon layer 8 is formed on the silicon oxide film 7 by using the low pressure CVD method.
Is deposited so that its lower portion is connected to the diffusion region 6.
Next, in the same low pressure CVD apparatus, the polysilicon layer 8 was doped with phosphorus at about 5 × 10 ²⁰ atm / cm ³ 1
A 00 nm polysilicon layer 9 is deposited. The non-doped polysilicon layer 8 having a thickness of 100 nm is deposited on the polysilicon layer 9, and the polysilicon layer 8 is doped with phosphorus 1.
The polysilicon layer 9 of 00 nm is deposited, the polysilicon layer 8 of 100 nm is further deposited, and the multilayer film 10 of 5 layers is deposited.
To form.

Next, as shown in FIG. 4, the multilayer film 10 is etched by RIE to form the lower electrodes 11, 11 ... Of the capacitors corresponding to the memory cells. Then, the lower electrodes 11, 11 ... Are wet-etched. The etching solution is HF: HNO ₃ : CH ₃ COOH = 1:
Use 3: 8 solution. H of the polysilicon layers 8 and 9
The etching rate for the F: HNO ₃ : CH ₃ COOH = 1: 3: 8 solution depends on the concentration of impurities contained in the polysilicon layer, and is about 0 μm / min for the non-doped polysilicon layer 8 and about 5 × 10 5 phosphorus. Approximately 1 μm / m for the polysilicon layer 9 doped by ²⁰ atm / cm ³
in. Due to this difference in etching rate, as shown in FIG.
As shown in FIG. 3, only the side surface of the polysilicon layer 9 is deeply etched, and a recess is formed on the side surface of the lower electrode 11.

Thereafter, heat treatment is performed to diffuse the impurities so that the impurity concentration of the lower electrode 11 in which the recess is formed becomes uniform. Then, as shown in FIG. 6, a capacitor dielectric film 13 made of an oxide film or a nitride film is formed on the surface including the recess formed on the side surface of the lower electrode 11. The capacitor dielectric film 13 may be a multilayer film formed of an oxide film and a nitride film. Then, polysilicon is deposited on the surface of the capacitor dielectric film 13 to form the upper electrode 14 of the capacitor.

The semiconductor memory device manufactured as described above is
By utilizing the fact that the etching rate varies depending on the impurity concentration contained in polysilicon, the lower electrode 11 in which polysilicon layers having different impurity concentrations are stacked is formed.
A concave portion is formed on the side surface, and the surface area of the capacitor electrode is increased.

In this embodiment, the lower electrode 11 is formed by alternately stacking five layers using two kinds of polysilicon layers, but the present invention is not limited to this, and how many kinds of films and how many layers are formed. You may laminate. Further, as long as the films have different etching rates and can function as electrodes, for example, a polysilicon layer and a tungsten layer may be stacked.

[0017]

As described above, according to the present invention, even if the semiconductor device is highly integrated, a semiconductor device having a large capacity can be easily manufactured with a small number of steps. Play.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a structure of a conventional stacked type semiconductor memory device.

FIG. 2 is a schematic cross-sectional view showing a stacked semiconductor memory device having a fin structure.

FIG. 3 is a schematic cross-sectional view showing the structure of a semiconductor memory device manufactured by the method of the present invention at the formation stage.

FIG. 4 is a schematic cross-sectional view showing the structure of a semiconductor memory device manufactured by the method of the present invention at the formation stage.

FIG. 5 is a schematic cross-sectional view showing the structure of a semiconductor memory device manufactured by the method of the present invention at the formation stage.

FIG. 6 is a schematic cross-sectional view showing the structure of a semiconductor memory device manufactured by the method of the present invention at the formation stage.

[Explanation of symbols]

 1 Silicon Substrate 4,5 Gate Electrode 6 Diffusion Region 8 Undoped Polysilicon Layer 9 Doped Polysilicon Layer 10 Multilayer Film 11 Lower Electrode 13 Capacitor Dielectric Film 14 Upper Electrode

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Makoto Akizuki 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. (72) Hiroyuki Aoe 2-18-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Denki Within the corporation

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a lower electrode of a capacitor is in contact with a diffusion region formed on a semiconductor substrate, wherein at least two kinds of films having different etching rates are used to form the lower electrode. A method of manufacturing a semiconductor device, comprising: a step of forming a multilayer film by laminating in multiple layers; and a step of performing isotropic etching to form a plurality of concave portions on a side surface of the multilayer film.