KR940007392B1 - Method of fabricating a semiconductor memory device - Google Patents

Abstract

The method for extending the effective area of the cell capacitor in the memory device to increase the capacitance comprises the steps of: a) forming the first contact hole exposing a part of the source region; b) forming the first stack capacitor connecting to the exposed source region; c) forming the second contact hole exposing the storage electrode of the capacitor; d) forming the second stack capacitor connecting to the exposed storage electrode; and e) connecting the plate electrodes of the first and second stack capacitors by depositing the conductive material.

Description

Manufacturing Method of Semiconductor Memory Device

1A to 1D are process flowcharts showing a manufacturing process of a stacked capacitor of a conventional semiconductor memory device.

2A to 2G are process flowcharts of one embodiment showing a manufacturing process of a stacked capacitor of a semiconductor memory device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a manufacturing method for improving the capacitance of a semiconductor memory device.

Since the invention of the DRAM (Dynamic Random Access Memory) in the early 1970s, the density of semiconductor devices has increased about four times every three years. Currently, 4Mb DRAMs are in production, 16Mb DRAMs are in mass production, and 64Mb DRAMs and 256DRAMs are being researched.

As such, the semiconductor device has only increased 1.4 times in size compared to 4 times its density, and the memory cell area per bit is reduced to 1/3, which is the capacity of the semiconductor memory (C = εA / Ti). (ε; dielectric constant of insulating film, A; area of capacitor, Ti; thickness of insulating film), and as a result, C also decreased to 1/3 as long as conditions other than area A of capacitor were the same.

The reduction of the capacitor reduces the signal-to-noise ratio (S / N), which causes a big problem in circuit operation. The α particles generated from the patch are introduced into the substrate of the chip and the information stored in the memory device is destroyed. Was generated. Thus, many capacitors of a new structure have been proposed to increase the effective area of the cell capacitance to prevent the reduction of the capacitance.

Representative examples thereof include a trench capacitor having a three-dimensional structure, a stacked capacitor, and a stack- trench merged capacitor. Among them, research on stacked capacitors is actively underway, and the related art is manufactured through the following process. 1A to 1D show a manufacturing process of a stacked capacitor according to the prior art.

Referring to FIG. 1A, a field oxide film 101 is formed on a semiconductor substrate 100 to separate an active region and an inactive region, and then a gate electrode 5 is formed on the semiconductor substrate, and a source region 7 is formed. And a drain region 8 formed by doping an impurity in the semiconductor substrate 100 using the gate electrode 5 as a mask, and insulating the gate electrode on the entire surface of the transistor including the gate, the drain, and the source. And a first insulating film 9 for etch stop purposes.

Referring to FIG. 1B, the first insulating layer 9 of the semiconductor substrate is etched to form a first contact hole 11.

Referring to FIG. 1C, a process of forming a storage electrode pattern 15 after forming a first conductive layer by depositing a conductive material on the entire surface of the semiconductor substrate on which the transistor is formed is illustrated. In this case, the conductive material is formed of a polycrystalline silicon doped with impurities to form a first conductive layer and then a mask pattern for forming a storage electrode pattern is applied to form the storage electrode 15.

Referring to FIG. 1D, in the process of forming the first dielectric layer 16 and the plate electrode 17, a thin dielectric material is applied to the entire surface of the storage electrode 15 to form the first dielectric layer 16. A second conductive layer is formed by depositing a conductive material such as polycrystalline silicon doped with impurities, for example, on the entire surface of the semiconductor substrate, and then applying a mask pattern for forming a plate electrode to form the plate electrode 17.

The conventional stacked capacitor structured memory fabricated through the above process has a simpler fabrication process, relatively fewer parasitic transistors, and is more resistant to soft errors than other capacitor memory structures, whereas the capacitor area is limited to a small portion of a single cell. It is difficult to increase the accumulated capacity.

An object of the present invention is to provide a method of manufacturing a capacitor of a highly integrated semiconductor memory device that can increase the effective area of the cell capacitor to solve such a problem.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2a and 2g are an embodiment according to the present invention, the process of providing a first stacked capacitor according to the present invention is the same as the method of Figs. For reference, the process thereafter is as follows.

Referring to FIG. 2A, a process of forming a second insulating film to insulate the first and second stacked capacitors is illustrated. An example is shown on the entire surface of the semiconductor substrate on which the first stacked capacitors are formed. For example, a thermal oxide film, a low pressure chemical vapor deposition (LPCVD) oxide film, a plasma enhanced chemical vapor deposition (PECVD) oxide film, or the like may be used as the oxide film, or SiN, SiON, etc. may be stacked to a thickness of 500 kPa to 2000 kPa as the nitride film. To form.

Referring to FIG. 2B, a storage electrode 15 of a first stacked capacitor and a storage electrode of a second stacked capacitor may be connected to a first stacked capacitor manufactured by a conventional stacked capacitor manufacturing technique. The process of forming the second contact hole 19 is shown. The second insulating film 18 and the plate electrode 17 and the first dielectric film 16 of the first stacked capacitor are formed using a photolithography process. The second contact hole 19 is formed by etching.

Referring to FIG. 2C, an oxide film and a nitride film are stacked on the entire surface of the semiconductor substrate to form a third insulating film 20, which illustrates a process for forming the third insulating film 20.

Referring to FIG. 2D, the storage electrode 15 and the plate electrode 17 of the first stacked capacitor are insulated and the storage electrode of the first stacked capacitor and the storage electrode of the second stacked capacitor are connected to each other. In order to form a spacer, the third insulating film 20 is etched to form a spacer with the third insulating film remaining without being etched on the inner wall of the second contact hole.

Referring to FIG. 2E, a process of forming the storage electrode 22 of the second stacked capacitor is illustrated. For example, polysilicon, amorphous silicon, or the like may be used as a conductive layer on the entire surface of the semiconductor substrate. By depositing thickly, the storage electrode 22 is formed.

Referring to FIG. 2F, a process for forming the second dielectric film 24 and the plate electrode 25 of the second stacked capacitor is illustrated. The thermal oxide film and silicon nitride are formed on the entire surface of the storage electrode 23. Dielectric material such as (SiN), nitrososilicon (SiON), titanium dioxide (TiO ₂ ), tantalum pentoxide (Ta ₂ O ₅ ) and lead zirconate tartaric acid (PZT: Pb _x Zr _y Ti ₂ O) Forming an insulating film of a film structure or a composite film structure in which two or more materials are stacked, and then depositing a material such as, for example, polycrystalline silicon doped with impurities on the semiconductor substrate, thereby forming a plate electrode of the second stacked capacitor. To form 25.

Referring to FIG. 2G, a process for connecting the plate electrodes 17 and 25 of the first and second stacked capacitors on the semiconductor substrate is illustrated, and the plate electrodes 17 and 25 are formed. And one side of the second insulating film 18, and then etching the side surface of the second insulating film 18 by a wet etching process for 10 seconds to 2 minutes in order to facilitate the connection between the two electrodes, and then polycrystalline silicon and amorphous silicon The back electrode is deposited on the entire surface of the semiconductor substrate with a thickness of 300 Å to 2000 Å to connect the plate electrodes 17 and 25.

The semiconductor memory device having the stacked capacitor of the multi-layer structure according to the present invention made through the manufacturing process as described above increases the effective area of the capacitor by multiplying the storage electrodes, thereby increasing the capacitance 1.5 times higher than that of the conventional stacked capacitor. You can get it. In addition, since the dielectric layers of the primary stack and the secondary stack may use different dielectric materials, it is possible to manufacture a highly integrated semiconductor memory device having a capacitance desired by a manufacturer.

As mentioned above, although this invention was demonstrated concretely according to the said Example, this invention is not limited to the said Example, Of course, a various change is possible in the range which does not deviate from the summary.

Claims (7)

A method of manufacturing a semiconductor memory device having a plurality of memory cells comprising one transistor and one capacitor on a semiconductor substrate, the method comprising: forming a first insulating film to insulate the transistor; Etching the first insulating layer to form a first contact hole exposing a portion of a source region of the transistor; Forming a first stacked capacitor to be connected to the exposed source region; Forming a second insulating film to insulate the first stacked capacitor; Forming a second contact hole by applying a mask on the second insulating layer to expose the storage electrode of the first stacked capacitor; Insulating the plate electrode of the first stacked capacitor exposed along the inner wall of the second contact hole; Forming a second stacked capacitor to be connected to the exposed storage electrode of the first stacked capacitor; Performing an etching process to expose the first insulating film over the drain region of the transistor; Removing a part of the side surface of the second insulating layer which insulates the first stacked capacitor and the second stacked capacitor by the wet etching process, the exposed portion through the etching process; And interconnecting the plate electrodes of the first and second stacked capacitors by depositing a conductive material on the entire surface of the resultant. The method of claim 1, wherein the insulating of the plate electrode of the first stacked capacitor exposed along the inner wall of the second contact hole comprises anisotropic etching after forming an insulating film on the entire surface of the resultant product in which the second contact hole is formed. A method of manufacturing a semiconductor memory device, characterized by The method of claim 1, wherein the wet etching process of removing a portion of the sidewall of the second insulating layer is performed for about 10 seconds to about 2 minutes. The semiconductor memory device according to claim 1, wherein the storage electrodes, the plate electrodes, and the conductive materials of the first and second stacked capacitors are deposited by depositing polycrystalline silicon doped with impurities by the LPCVD method. Manufacturing method. The second insulating film for insulating the first stacked capacitor and the second stacked capacitor includes an oxide film such as a thermal oxide film, an LPCVD oxide film or a PECVD oxide film, or a nitride film such as SiN. A method of manufacturing a semiconductor memory device, characterized in that formed by the thickness of. The method of claim 1, wherein the first and second dielectric films of the first stacked capacitor and the second stacked capacitor are formed using a thermal oxide film, SiON, PZT, TiO ₂ , Ta ₂ O _5, or the like. A method for manufacturing a semiconductor memory device, characterized by forming a film or a composite film structure in which two or more materials are laminated. 7. The method of claim 6, wherein the first dielectric film and the second dielectric film can be formed using different materials.