KR100277864B1 - Smeiconductor memory device and for manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a semiconductor memory device suitable for improving capacitance with a simple structure and a method for manufacturing the same. Such a semiconductor memory device includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, a T-shaped trench formed in the insulating film, a first storage node formed in the trench and having a groove on the upper side thereof, except for the groove portion. A first dielectric layer formed on the storage node, a plate node formed on the first dielectric layer, a second dielectric layer formed on the plate node, a second storage node formed on the second dielectric layer, and the second storage above the groove A third dielectric layer formed on side surfaces of the node, the second dielectric layer, the plate node, the first dielectric layer, and the first storage node, and formed above the groove of the first storage node, and formed on the third dielectric layer and the second storage node. And a third storage node.

Description

Semiconductor memory device and manufacturing method therefor {SMEICONDUCTOR MEMORY DEVICE AND FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a semiconductor memory device suitable for improving capacitance with a simple structure and a method for manufacturing the same.

BACKGROUND With the development of semiconductor devices, the work of integrating many devices on one semiconductor chip has been actively performed. In particular, in memory cells of DRAM (Dynamic Random Access Memory), various various cell structures have been proposed to minimize the device size.

Generally, a DRAM memory cell is composed of one transistor and one capacitor. As described above, in a memory cell including one transistor and one capacitor, signal charges are stored in a storage node of a capacitor connected to a transistor (switching transistor). Therefore, when the size of the memory cell is reduced due to the high integration of the semiconductor memory device, the size of the capacitor is also reduced, thereby reducing the number of charges that can be stored in the storage node. Therefore, in order to deliver the desired signal without malfunctioning, the capacitor storage node of the memory cell must have a surface area above a certain value in order to secure the capacitor capacity required for signal transmission. Therefore, in order to reduce the size of the memory cell, the storage node of the capacitor should have a relatively large surface area within the limited area of the semiconductor substrate. Therefore, the form of the capacitor is to use the fin (FIN) or cylinder structure in the parallel plate structure.

Hereinafter, a conventional semiconductor memory device will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a conventional semiconductor memory device.

As shown in FIG. 1, a conventional semiconductor memory device includes a trench formed on an insulating film 1 including a semiconductor substrate and a storage formed on an insulating film 1 adjacent to the trench 2 and the trench 2. A node 5, a dielectric film 6 formed on a surface of the storage node 5, and a plate node 7 formed on the dielectric film 6 are included.

One such conventional semiconductor memory device has a crown-shaped stack structure and has pillars formed on the side surfaces of the first storage node 3 and the first storage node 3 having a T-shape. It consists of the second storage node 4 of the structure.

As such crown type stack structure, nitride film (Si ₃ N ₄ ) was used as dielectric film 6 up to 64M DRAM (DRAM) class, but it was not suitable for its structural problem above 256M DRAM (DRAM) class. Known.

2 is a cross-sectional structural view of a semiconductor memory device according to another conventional example.

As shown in FIG. 2, a semiconductor memory device according to another example includes a trench 12 formed on an insulating film 11 including a semiconductor substrate, and an insulating film 11 adjacent to the trench 12 and the trench 12. The storage node 13 includes a dielectric layer 14 formed on a surface of the storage node 13 and a plate node 15 formed on the dielectric layer 14.

The other conventional semiconductor memory device has a simple planar stack structure and has a T-shaped storage node 13 and a plate node 15 formed on the storage node 13 via a dielectric layer 14. And the material of the dielectric film 14 is formed by using a high dielectric material such as high dielectric material (for example, Ta ₂ O ₅ ) or a ferroelectric material (for example, PZT: PbZrTiO ₃ ) or ferroelectric material. It is possible to provide a memory device having advantages of ease of processing of materials and low capacitor height.

The conventional semiconductor memory device has the following problems.

First, in the conventional semiconductor memory device, since the height of the pillar-shaped storage node needs to be increased in order to improve capacitance, a step in the entire device increases and a dielectric film having a high insulation constant is required. There is a difficult problem with the film forming technology.

Second, in the conventional semiconductor memory device, the capacitance securing problem is largely dependent on the dielectric constant of the dielectric film, thereby limiting the selection range of the dielectric film material.

The present invention has been made to solve the problems of the conventional semiconductor memory device as described above, and its object is to provide a semiconductor memory device suitable for improving capacitance with a simple structure and a method of manufacturing the same.

1 is a cross-sectional structural view of a semiconductor memory device according to an exemplary embodiment

2 is a cross-sectional structural view of a semiconductor memory device according to another conventional example

3 is a cross-sectional structure diagram of a semiconductor memory device of the present invention.

4A to 4G are cross-sectional views of a manufacturing process of the semiconductor memory device according to the present invention.

Explanation of symbols for main parts of the drawings

21: insulating film 22: trench

23: first storage node 24: first dielectric layer

25: plate node 26: the second dielectric film

27: second storage node 28: contact hole

29: third dielectric layer 30: third storage node

A semiconductor memory device according to the present invention includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, a T-shaped trench formed in the insulating film, a first storage node formed in the trench, and the storage node except the groove portion. A first dielectric layer formed on the first dielectric layer, a plate node formed on the first dielectric layer, a second dielectric layer formed on the plate node, a second storage node formed on the second dielectric layer, the second storage node above the groove, and a second A third dielectric layer formed on a side of a dielectric layer, a plate node, a first dielectric layer, and a first storage node, and a third storage node formed on an upper side of the groove of the first storage node and formed on the third dielectric layer and the second storage node; It includes. In the method of manufacturing a semiconductor memory device of the present invention as described above, forming an insulating film on a semiconductor substrate, forming a T-shaped trench in the insulating film, and forming a first storage node in the trench. Forming a first dielectric film and a plate node on the dielectric film on the insulating layer adjacent to the first storage node and the first storage node, and forming a plate node on the dielectric film and a second dielectric film on the plate node. Forming a trench by selectively removing the second storage node, the second dielectric layer, the plate node, the first dielectric layer, and the first storage node; forming the trench, the first storage node in the trench, Forming a third dielectric layer on side surfaces of the first dielectric layer, the plate node, the second dielectric layer, and the second storage node; Value including a step of forming a third storage node on the second storage node.

Such a semiconductor memory device and a method of manufacturing the same will be described with reference to the accompanying drawings.

3 is a cross-sectional structural view of the semiconductor memory device of the present invention.

As shown in FIG. 3, the semiconductor memory device of the present invention includes an insulating film 21 formed on the semiconductor substrate including a semiconductor substrate, a T-shaped trench 22 formed in the insulating film 21, and A first storage node 23 formed in the trench 22 and having a groove on the upper side, a first dielectric layer 24 formed on the first storage node 23 except for the groove portion, and the first dielectric layer A plate node 25 formed on the 24, a second dielectric layer 26 formed on the plate node 25, a second storage node 27 formed on the second dielectric layer 26, and A third dielectric layer 29 formed on side surfaces of the second storage node 27, the second dielectric layer 26, the plate node 25, the first dielectric layer 24, and the first storage node 23 above the groove; A third dielectric layer 29 and a second storage node 2 formed above the groove of the first storage node 23. And a third storage node 30 formed on 7).

In this case, both edge portions of the second dielectric layer 26, the second storage node 27, and the third storage node 30 formed on the plate node 25 are narrower than both edge portions of the plate node 25. It is formed in width.

In addition, the dielectric layer 32 including the first, second, and third dielectric layers 24, 26, and 29 may be formed of any one of a nitride film, a high dielectric film, and a ferroelectric film. The storage node 31 composed of the third storage nodes 23, 27 and 30 is formed of either polysilicon or platinum.

4A to 4G are cross-sectional views illustrating a manufacturing process of the semiconductor memory device of the present invention.

First, as shown in FIG. 4A, a T-shaped trench 22 is formed on the insulating film 21 formed on the semiconductor substrate including the semiconductor substrate. A first storage node 23 is then formed in the tee-shaped trench 22.

As shown in FIG. 4B, the first dielectric layer 24 and the plate node 25 are sequentially formed on the insulating layer 21 adjacent to the first storage node 23 and the first storage node 23. At this time, the plate node 25 is formed of platinum (Pt) or polysilicon.

As shown in FIG. 4C, a second dielectric layer 26 and a second storage node 27 are formed on the plate node 25.

As shown in FIG. 4D, the second storage node 27 and the second dielectric layer 26 are patterned (photolithography process + etching process) in a narrower width than the plate node 25.

As shown in FIG. 4E, a first storage including the second storage node 27, the second dielectric layer 26, the plate node 25, and the first dielectric layer 24 of the contact hole region is defined. The node 23 is etched to a predetermined depth to form the contact hole 28. In this case, the contact hole region is defined as the same position as the central portion of the tee (T) shaped trench 22.

As shown in FIG. 4F, the second storage node 27, the second dielectric layer 26, the plate node 25, the first dielectric layer 24 and the first storage node 23 in the trench 28 are formed. A third dielectric layer 29 is formed on the side surface.

As shown in FIG. 4G, the third storage node 30 is formed on the contact hole 28 and the second storage node 27 on both sides of the contact hole 28.

In this case, the dielectric layer 32 including the first, second, and third dielectric layers 24, 26, and 29 may include any one or more of a nitride film, a high dielectric film, and a ferroelectric film. The storage node 31 including the first, second, and third storage nodes 23, 27, 30 may use either polysilicon or platinum.

The semiconductor memory device and its manufacturing method according to the present invention have the following effects.

First, since the area of the capacitor is formed in a structure in which the plate node is formed between the storage nodes to increase the area of the dielectric layer, the semiconductor memory device and the method of manufacturing the semiconductor memory device suitable for improving the capacitance as well as wide selectivity to the dielectric film are provided. can do.

Second, since the storage node and the dielectric film are formed in several times, various materials and processes can be used depending on their characteristics such as adhesion problem, processability problem, or heat treatment, so that the selectivity is wide.

Claims (4)

Semiconductor substrates; An insulating film formed on the semiconductor substrate; A T-shaped trench formed in the insulating film; A first storage node formed in the trench and having a groove thereon; A first dielectric layer formed on the storage node except for the groove portion; A plate node formed on the first dielectric layer; A second dielectric layer formed on the plate node; A second storage node formed on the second dielectric layer; A third dielectric layer formed on side surfaces of the second storage node, the second dielectric layer, the plate node, the first dielectric layer, and the first storage node above the groove; And a third storage node formed above the groove of the first storage node and formed on the third dielectric layer and the second storage node. The semiconductor memory device of claim 1, wherein the first, second, and third dielectric films comprise at least one of a nitride film, a high dielectric film, and a ferroelectric film. The semiconductor memory device of claim 1, wherein both edge portions of the second dielectric layer, the second storage node, and the third storage node formed on the plate node have a width narrower than an edge portion of the plate node. Forming an insulating film on the semiconductor substrate; Forming a T-shaped trench in the insulating film; Forming a first storage node in the trench; Forming a first dielectric layer on the insulating layer adjacent to the first storage node and the first storage node and a plate node on the dielectric layer; Forming a second dielectric layer on the plate node and a second storage node on the second dielectric layer; Selectively removing the second storage node, the second dielectric layer, the plate node, the first dielectric layer, and the first storage node to form a trench; Forming a third dielectric layer on sides of the first storage node, the first dielectric layer, the plate node, the second dielectric layer, and the second storage node in the trench; And forming a third storage node on the second storage node including the trench.

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