JP3104262B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a dynamic random access memory (DRAM) having a stacked capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art DRA having a stacked capacitor
In M, as a method of increasing the surface area of the capacitor,
A node electrode having a fin structure has been proposed. For example, IED Technical Digest 1
988, p. 592-595 (IEDM Tec
h. Dig. , 1988, pp 592-595).
There have been proposed a structure in which a bit line is formed above a stacked capacitor and a structure in which a stacked capacitor is formed above a bit line. FIG. 6 shows the former structure.
A description will be given with reference to cross-sectional views in the order of steps shown in FIGS.

First, on the surface of a p-type silicon substrate 201,
An element isolation oxide film 202 is formed, and a word line 203, an n-type node diffusion layer 204a, and an n-type bit diffusion layer 204b are formed.
Is formed. Next, a first interlayer insulating film 215 is deposited on the entire surface. At least interlayer insulating film 2
15 is formed of a silicon nitride film. Subsequently, a silicon oxide film 216a, an n-type polycrystalline silicon film 207a, and a silicon oxide film 216b are sequentially deposited (FIG. 6).

Next, the silicon oxide film 216b, the polycrystalline silicon film 207a, the silicon oxide film 216a, and the interlayer insulating film 215 are sequentially etched to open a node contact hole 206 reaching the node diffusion layer 204a. continue,
An n-type polycrystalline silicon film 207b is deposited on the entire surface. Next, the polysilicon film 207b, the silicon oxide film 216b, the polysilicon film 207a, and the silicon oxide film 216a are sequentially formed by anisotropic etching such as reactive ion etching using a photoresist film (not shown) as a mask. Etch. After removing the photoresist film, the polycrystalline silicon film 20 is etched by hydrofluoric acid based wet etching.
The silicon oxide film 216b sandwiched between the polysilicon film 207a and the polycrystalline silicon film 207a and the silicon oxide film 216a sandwiched between the polycrystalline silicon film 207a and the interlayer insulating film 215 are removed to form a fin-structured node electrode 209. [FIG. 7].

Next, a capacitive insulating film 210 is deposited on the entire surface. Subsequently, an n-type polycrystalline silicon film is deposited on the entire surface, and this is etched to form a cell plate electrode 211 made of the n-type polycrystalline silicon film. Using the cell plate electrode 211 as a mask, the capacitor insulating film 210 is etched away to form a stacked capacitor. Next, a second interlayer insulating film 212 is deposited on the entire surface, and the interlayer insulating films 212 and 21 on the bit diffusion layer 204b are deposited.
5 are sequentially etched to open a bit contact hole 213. Next, a bit line 214 is formed to complete the DRAM (FIG. 8).

[0006]

In the method of increasing the surface area of the node electrode by the fin structure, the processing steps are complicated and difficult. In realizing the structure of the node electrode, at the stage where the silicon oxide film sandwiched between the polycrystalline silicon films is removed by etching, the mechanical strength of the node electrode is reduced, and a process such as cleaning becomes difficult. It is difficult to deposit and fill the capacitance insulating film and the film constituting the cell plate electrode on the surface of the deep fin.

[0007]

According to the present invention, there is provided a semiconductor device comprising:
Dynamic Lander with Stacked Capacitor
A semiconductor device having a memory access memory;
The tacked capacitor has a first width and does not contain oxygen.
The first polycrystalline silicon film is different from the first width
A second polycrystalline silicon film having a second width and containing oxygen
And node electrodes alternately stacked on a semiconductor substrate
And a capacitor insulating film formed over the node electrode;
A cell plate electrode formed covering the capacitance insulating film;
Characterized in that it is a stacked capacitor with
You.

Further, a method of manufacturing a semiconductor device according to the present invention
Dynamic Lander with Stacked Capacitor
In a method of manufacturing a node electrode of a mux cell memory,
A node contact hole is formed in the interlayer insulating film provided on the conductor substrate.
An opening step, the interlayer insulating film and the node contour
Oxygen-free first polycrystalline silicon
A first polycrystalline silicon layer forming step of forming a capacitor layer;
Oxidizing the surface of the first polycrystalline silicon layer to contain oxygen
Second polycrystalline silicon forming second polycrystalline silicon layer
Layer forming step and the first polycrystalline silicon layer forming step
And the step of forming the second polycrystalline silicon layer are repeated.
Forming a laminated polycrystalline silicon layer by
The laminated polycrystalline silicon layer is formed on the first
Of the polycrystalline silicon layer and the second polycrystalline silicon layer
Perform isotropic etching under conditions with different etching rates
Forming a region to be the node electrode .

[0009]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 to 3 are cross-sectional views illustrating a method for manufacturing a semiconductor device and a structure of the semiconductor device according to the present embodiment. FIG. 4 is a graph showing a change over time in a gas flow rate for explaining the manufacturing method according to the present embodiment. FIG. 5 is a graph for explaining effects according to the present embodiment.

The description will proceed along the method of manufacturing a semiconductor device according to this embodiment. First, a p-type silicon substrate 101
By forming an element isolation oxide film 102 on the surface, an active region and an element isolation region are partitioned, and after forming a gate oxide film on the active region, a word line 103 is formed. next,
Using the word line 103 on the active region as a mask, an n-type node diffusion layer 104a and a bit diffusion layer 10
4b, and the formation of the DRAM transistor is completed. Subsequently, a first interlayer insulating film 105 is formed on the entire surface. The interlayer insulating film 105 does not need to have at least its surface made of a silicon nitride film as in the conventional example. Next, the interlayer insulating film 105 on the node diffusion layer 104a is etched to open a node contact hole 106.

Next, in a low pressure CVD (LPCVD) apparatus, for example, a non-doped polycrystalline silicon film 107a is formed by thermal decomposition of silane in a temperature range of 500 ° C. to 600 ° C.
Is deposited. Subsequently, the polycrystalline silicon film 10 is
7a, the surface of the polycrystalline silicon film 107a is exposed to an argon atmosphere containing 0.2% to 5% of oxygen to form a polycrystalline silicon film 108a containing oxygen.
To form By repeating the same operation, the non-doped polycrystalline silicon film 107b, the oxygen-containing polycrystalline silicon film 108b, and the non-doped polycrystalline silicon film 107 are formed.
A polycrystalline silicon film 108c containing c and oxygen is sequentially formed to form a laminated polycrystalline silicon film, and the structure shown in FIG. 1 is obtained.

Here, the flow rates of silane and oxygen diluted with argon are periodically changed, for example, as shown in FIG. The thickness of the oxygen-containing polycrystalline silicon film 108 is LP
It is determined by the temperature, pressure, partial pressure of oxygen, time and the like in the CVD apparatus, but in the above-mentioned range, it is 5 nm to 200 nm. This is because the polycrystalline silicon film 10 is formed in the LPCVD apparatus.
By exposing the surface of the silicon oxide film 7 to oxygen, 1 to 3 molecular silicon oxide film layers are formed on the surface of the polycrystalline silicon film 107, but the oxygen that does not form the silicon oxide is more widely dispersed. It is considered to be.

Next, it is taken out of the LPCVD apparatus and
The non-doped polycrystalline silicon film 107 and the oxygen-containing polycrystalline silicon film 108 are made n-type by diffusion of phosphorus oxychloride by bubbling at 0 ° C. to 850 ° C. continue,
Isotropic etching is performed with sulfur hexafluoride gas using a photoresist film (not shown) as a mask, and n-type polycrystalline silicon films 107a, 107b, 107c and n
Type oxygen-containing polycrystalline silicon films 108a, 108b,
A stacked capacitor node electrode 109 made of 108c is formed to obtain the structure shown in FIG.

In this embodiment, after forming a laminated polycrystalline silicon film, phosphorus is diffused into the film to make it an n-type. By using a mixed gas of silane and phosphine in an LPCVD apparatus, an n-type laminated polycrystalline silicon film can be formed. Also, MB
There is also a method in which the thickness of the oxygen-containing polycrystalline silane film is thinly formed with good controllability by using the E apparatus.

Here, if isotropic etching using sulfur hexafluoride gas is used, the polycrystalline silicon film 108 containing oxygen is used.
Since the etching rates of a, 108b, and 108c are lower than that of the polycrystalline silicon films 107a, 107b, and 107c containing no oxygen, the side surfaces of the node electrode 109 have irregularities. The depression of the concave portion is about 0.1 to 0.3 μm. By utilizing this phenomenon, the node electrode 1
In particular, an increase in the surface area of the side surface of the embodiment 09 is obtained. This is proportional to the number of oxygen-containing polycrystalline silicon films 108, as shown in FIG. This effect becomes more effective by reducing the thickness of the polycrystalline silicon film 108.

Next, a capacitor insulating film 110 and a cell plate electrode 111 are formed to complete a stacked capacitor. Note that, unlike the conventional example, in the present embodiment, since the unevenness on the side surface of the node electrode 109 is not severe, the formation of the capacitor insulating film 110 and the cell plate electrode 111 can be performed easily and reliably. Subsequently, a second interlayer insulating film 11 is formed on the entire surface.
2 and an interlayer insulating film 11 on the bit diffusion layer 104b.
2105 are sequentially etched to form a bit contact hole 1
13 is opened. Finally, the bit line 114 is formed, and the DRAM is completed as shown in FIG.

In the present embodiment, the oxygen-containing polycrystalline silicon film 108 constituting the node electrode 109, even if it contains oxygen, is not entirely in the form of silicon oxide. , N-type. The sheet resistance of the polycrystalline silicon film 108 in this embodiment is:
The value is about 200Ω / □ to 1000Ω / □.

In this embodiment, as described above, the number of steps is smaller than that of a manufacturing method for obtaining a normal fin structure. Further, in this embodiment, the concave portion of the fin is at most 0.1 mm.
Since the dent is about 3 μm, mechanical strength is secured.

[0019]

As described above, according to the present invention, since the node electrode is constituted by the laminated polycrystalline silicon film having at least one polycrystalline silicon film containing oxygen, the fin structure can be manufactured by a simple method. it can. Further, the deterioration of the mechanical strength of the fin structure and the difficulty of forming the capacitor insulating film and the cell plate electrode are eliminated.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining one embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining one embodiment of the present invention.

FIG. 4 is a graph for explaining a manufacturing method according to an embodiment of the present invention.

FIG. 5 is a graph for explaining an effect of one embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a conventional stacked capacitor having a fin structure.

FIG. 7 is a cross-sectional view illustrating a stacked capacitor having a conventional fin structure.

FIG. 8 is a cross-sectional view illustrating a stacked capacitor having a conventional fin structure.

[Explanation of symbols]

 101, 201 silicon substrate 102, 202 element isolation region oxide film 103, 203 word line 104a, 204a node diffusion layer 104b, 204b bit diffusion layer 105, 112, 212, 215 interlayer insulating film 106, 206 node contact hole 107, 207 Crystal silicon film 108 Polycrystalline silicon film containing oxygen 109, 209 Node electrode 110, 210 Capacitance insulating film 111, 212 Cell plate electrode 113, 213 Bit contact hole 114, 214 Bit line 216 Silicon oxide film

Claims (9)

(57) [Claims] (1)Dynami with a stacked capacitor
Semiconductor devices with random access memory
And The stacked capacitor,  A first polycrystalline silicon film having a first width and containing no oxygen
And having a second width different from the first width and containing oxygen
And the second polycrystalline silicon film alternately formed on the semiconductor substrate.
A stacked node electrode, a capacitor insulating film formed over the node electrode, and a cell plate electrode formed over the capacitor insulating film.
WithCharacterized by being a stacked capacitor
ToSemiconductor device. 2. The semiconductor device according to claim 2, wherein said first polycrystalline silicon film is
2. The semiconductor device according to claim 1, wherein said semiconductor device is thicker than said polycrystalline silicon film. 3. The semiconductor device according to claim 1, wherein said second polycrystalline silicon film contains said oxygen to such an extent that the conductivity type can be changed by diffusion of impurities. 4. The semiconductor device according to claim 1, wherein said second polycrystalline silicon film includes one to three molecular layers of a silicon oxide film layer on its surface . 5. Dynami having a stacked capacitor
Method of manufacturing node electrode of check random access memory
A node contact hole in an interlayer insulating film provided on a semiconductor substrate.
Forming an opening of the interlayer insulating film and the opening of the node contact hole.
A first polycrystalline silicon layer forming step of forming a first polycrystalline silicon layer containing no oxygen thereon, and a second polycrystalline silicon layer containing oxygen by oxidizing a surface of the first polycrystalline silicon layer a second polycrystalline silicon layer forming step of forming a step of forming a laminated polysilicon layers by repeating said first polycrystalline silicon layer forming step and the second polysilicon layer forming step Isotropically etching the laminated polycrystalline silicon layer on the basis of a desired mask under conditions that the first polycrystalline silicon layer and the second polycrystalline silicon layer have different etching rates.
Forming a region to be the node electrode . 6. The step of forming a second polycrystalline silicon layer ,
6. The method according to claim 5, further comprising exposing the first polycrystalline silicon layer to an atmosphere of an inert gas containing oxygen. 7. The step of forming a second polycrystalline silicon layer ,
7. The method of manufacturing a semiconductor device according to claim 6, wherein the first polycrystalline silicon layer is formed in the same apparatus at the same temperature. 8. A step of forming a capacitive insulating film so as to cover the entire surface of the laminated polycrystalline silicon layer after the isotropic etching is performed, and opposing the laminated polycrystalline silicon layer on the capacitive insulating film. The stacked type capacitor is formed by forming a conductor provided by
6. The method according to claim 5, further comprising the step of forming a region to be a cell plate electrode of the semiconductor device. 9. The method according to claim 5, wherein said isotropic etching is performed by sulfur hexafluoride gas.