JPH04278578A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To dissolve the deterioration of the mechanical strength of a fin structure and the difficulty of the formation of a capacitor insulating film and a selfplate electrode by a method wherein a node electrode is constituted of a laminated polycrystalline silicon film having at least one layer of an oxygen- containing polycrystalline silicon film. CONSTITUTION:A non-doped polycrystalline silicon film 107a is deposited by the thermal decomposition of a silane in a reduced CVD device. Subsequently, the silane is exposed in an argon atmosphere containing 0.2 to 0.5% of oxygen under the same temperature as that of the film 107a in the same device. Thereby, an oxygen-containing polycrystalline silicon film 108a is formed. By repeating the same operation, a non-doped polycrystalline silicon film 107b, an oxygen- containing polycrystalline silicon film 108b, a non-doped polycrystalline silicon film 107c and an oxygen-containing polycrystalline silicon film 108c are formed in order and a laminated polycrystalline silicon film is formed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a dynamic random access memory (DRAM) having a stacked capacitor and a method of manufacturing the same.

0002

[Prior Art] DRA with stacked capacitors
In M, as a method of increasing the surface area of the capacitor,
A node electrode with a fin structure has been proposed. For example, IEDM Technical Digest 1988, pages 592-595 (IEDM T
ech. Dig. , 1988, pp. 592-595) propose a structure in which a bit line is formed above a stacked capacitor and a structure in which a stacked capacitor is formed above a bit line. Regarding the former structure,
This will be explained with reference to cross-sectional views of the steps shown in FIGS. 6 to 8.

First, on the surface of the p-type silicon substrate 201,
An element isolation oxide film 202 is formed, and a word line 203, an n-type node diffusion layer 204a, and an n-type bit diffusion layer 204b are formed.
Form a transistor consisting of Next, a first interlayer insulating film 215 is deposited over the entire surface. At least interlayer insulating film 2
The surface of 15 is formed of a silicon nitride film. Subsequently, a silicon oxide film 216a, an n-type polycrystalline silicon film 207a, and a silicon oxide film 216b are sequentially deposited (FIG. 6).

Next, the silicon oxide film 216b, the polycrystalline silicon film 207a, the silicon oxide film 216a, and the interlayer insulating film 215 are sequentially etched to open a node contact hole 206 that reaches the node diffusion layer 204a. continue,
An n-type polycrystalline silicon film 207b is deposited over the entire surface. Next, by anisotropic etching such as reactive ion etching using a photoresist film (not shown) as a mask, the polycrystalline silicon film 207b, silicon oxide film 216b, polycrystalline silicon film 207a, and silicon oxide film 216a are sequentially etched. etching. After removing the photoresist film, the polycrystalline silicon film 20 is etched by hydrofluoric acid wet etching.
The silicon oxide film 216b sandwiched between the polycrystalline silicon film 207b and the polycrystalline silicon film 207a, and the silicon oxide film 216a sandwiched between the polycrystalline silicon film 207a and the interlayer insulating film 215 are removed to form a fin-structured node electrode 209. [Figure 7].

Next, a capacitor insulating film 210 is deposited on the entire surface. Subsequently, an n-type polycrystalline silicon film is deposited on the entire surface and etched to form a cell plate electrode 211 made of an n-type polycrystalline silicon film. Using the cell plate electrode 211 as a mask, the capacitor insulating film 210 is etched away to form a stacked capacitor. Next, a second interlayer insulating film 212 is deposited on the entire surface,
The interlayer insulating films 212 and 215 on the bit diffusion layer 204b are sequentially etched to open a bit contact hole 213. Next, bit lines 214 are formed to complete the DRAM (FIG. 8).

[0006]

Problems to be Solved by the Invention In the method of increasing the surface area of a node electrode using a fin structure, the processing steps are complicated and difficult. When realizing the structure of a node electrode, the mechanical strength of the node electrode decreases when the silicon oxide film sandwiched between the polycrystalline silicon films is removed by etching, making cleaning and other steps difficult. It is difficult to deposit and fill the capacitive insulating film and the film constituting the cell plate electrode on the surface of the deep fin.

[0007]

[Means for Solving the Problems] A semiconductor device of the present invention includes:
A DRAM having a stacked capacitor has a node electrode made of a laminated polycrystalline silicon film including at least one polycrystalline silicon film containing oxygen.

[0008] Furthermore, the method for manufacturing a semiconductor device of the present invention includes:
A method of manufacturing a DRAM node electrode consisting of one transistor and one stacked capacitor includes the steps of forming the transistor on the surface of a silicon substrate, forming an interlayer insulating film on the entire surface, and forming a node contact hole. A process of forming a multilayer polycrystalline silicon film including at least one layer of a type polycrystalline silicon film and an n-type polycrystalline silicon film containing oxygen, and dry etching using sulfur hexafluoride gas. The method includes a step of etching the crystalline silicon film to form a node electrode.

[0009]

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings. 1 to 3 are cross-sectional views for explaining the method of manufacturing a semiconductor device and the structure of the semiconductor device according to this embodiment. FIG. 4 is a graph showing temporal changes in gas flow rate for explaining the manufacturing method according to this embodiment. FIG. 5 is a graph for explaining the effects of this embodiment.

The description will proceed along with the method of manufacturing a semiconductor device according to this embodiment. First, a p-type silicon substrate 101
An active region and an element isolation region are defined by forming an element isolation oxide film 102 on the surface, and after forming a gate oxide film on the active region, a word line 103 is formed. next,
Using the word line 103 on the active region as a mask, an n-type node diffusion layer 104a and a bit diffusion layer 10 are formed on the surface of the active region.
4b is formed to complete the formation of the DRAM transistor. Subsequently, a first interlayer insulating film 105 is formed over the entire surface. The interlayer insulating film 105 does not need to have at least its surface made of a silicon nitride film as in the conventional example. Next, the interlayer insulating film 105 on the node diffusion layer 104a is etched to open a node contact hole 106.

Next, in a low pressure CVD (LPCVD) apparatus, for example, a non-doped polycrystalline silicon film 107a is deposited by thermally decomposing silane in a temperature range of 500.degree. C. to 600.degree. Subsequently, a polycrystalline silicon film 107 is formed in the same apparatus.
Polycrystalline silicon film 1 is formed by exposing it to an argon atmosphere containing 0.2% to 5% oxygen at the same temperature as a.
A polycrystalline silicon film 108a containing oxygen is formed on the surface of the polycrystalline silicon film 108a. By repeating the same operation, a non-doped polycrystalline silicon film 107b, an oxygen-containing polycrystalline silicon film 108b, and a non-doped polycrystalline silicon film 107c are formed.
, a polycrystalline silicon film 108c containing oxygen is sequentially formed,
A laminated polycrystalline silicon film is formed to obtain the structure shown in FIG.

[0012] Here, the flow rates of silane and argon diluted oxygen are changed periodically, as shown in FIG. 4, for example. The thickness of the polycrystalline silicon film 108 containing oxygen is LPC.
Although it is determined by the temperature, pressure, oxygen partial pressure, time, etc. in the VD device, the above-mentioned range is 5 nm to 200 nm. This is done by exposing the surface of the polycrystalline silicon film 107 to oxygen in the LPCVD apparatus.
A silicon oxide film layer of 1 to 3 molecular layers is formed on the surface of 7, but this is considered to be because oxygen, which is not in the form of silicon oxide, becomes more widely dispersed.

[0013] Next, take it out from the LPCVD apparatus and
Non-doped polycrystalline silicon film 107 and oxygen-containing polycrystalline silicon film 108 are made n-type by diffusion by bubbling of phosphorus oxychloride at 0°C to 850°C. continue,
Isotropic etching is performed using sulfur hexafluoride gas using a photoresist film (not shown) as a mask, and the n-type polycrystalline silicon films 107a, 107b, 107c and n-type polycrystalline silicon films 107a, 107b, 107c are
type oxygen-containing polycrystalline silicon films 108a, 108b,
A node electrode 109 of a stacked capacitor 108c is formed to obtain the structure shown in FIG. 2.

In this example, after forming a laminated polycrystalline silicon film, phosphorus was diffused into it to make it n-type. An n-type laminated polycrystalline silicon film can also be formed by using a mixed gas of silane and phosphine in an LPCVD apparatus. Also, M.B.
There is also a method of forming a thin polycrystalline syringe film containing oxygen with good controllability by using an E apparatus.

Here, if isotropic etching with sulfur hexafluoride gas is used, the polycrystalline silicon film 108 containing oxygen can be etched.
Since the etching rate of the polycrystalline silicon films a, 108b, and 108c is slower than that of the oxygen-free polycrystalline silicon films 107a, 107b, and 107c, the side surface of the node electrode 109 has irregularities. The depression of the recess is approximately 0.1 to 0.3 μm. By utilizing this phenomenon, the node electrode 1
An increase in the surface area of 09, especially on the sides, is obtained. As shown in FIG. 6, this is proportional to the number of layers of polycrystalline silicon film 108 containing oxygen. Note that this effect becomes more effective by reducing the thickness of the polycrystalline silicon film 108.

Next, a capacitor insulating film 110 and a cell plate electrode 111 are formed to complete a stacked capacitor. Note that, unlike the conventional example, in this example, since the side surface of the node electrode 109 is not extremely uneven, the capacitive insulating film 110 and the cell plate electrode 111 can be formed easily and reliably. Subsequently, a second interlayer insulating film 112 is formed on the entire surface.
is deposited to form an interlayer insulating film 112 on the bit diffusion layer 104b.
, 105 are sequentially etched to form the bit contact hole 11.
Open 3. Finally, the bit line 114 is formed and
The DRAM is completed as shown in FIG.

Even if the polycrystalline silicon film 108 containing oxygen constituting the node electrode 109 in this embodiment contains oxygen, all of this oxygen is not in the form of silicon oxide, and therefore, due to diffusion of phosphorus, etc. , converted to n-type. The sheet resistance of the polycrystalline silicon film 108 in this example is:
The value is about 200Ω/□ to 1000Ω/□.

As described above, this embodiment requires fewer steps than the manufacturing method for obtaining a normal fin structure. In addition, in this embodiment, the recess of the fin is at most 0.3
Since the dent is on the order of μm, mechanical strength is ensured.

[0019]

As described above, according to the present invention, the fin structure can be manufactured by a simple method because the node electrode is formed of a laminated polycrystalline silicon film having at least one layer of polycrystalline silicon containing oxygen. can. Furthermore, the deterioration of the mechanical strength of the fin structure and the difficulty in forming the capacitor insulating film and the cell plate electrode are eliminated.

[Brief explanation of the drawing]

FIG. 1 is a sectional view for explaining one embodiment of the present invention.

FIG. 2 is a sectional view for explaining one embodiment of the present invention.

FIG. 3 is a sectional view for explaining one embodiment of the present invention.

FIG. 4 is a graph for explaining a manufacturing method according to an embodiment of the present invention.

FIG. 5 is a graph for explaining the effects of one embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining a conventional stacked capacitor having a fin structure.

FIG. 7 is a cross-sectional view for explaining a conventional stacked capacitor having a fin structure.

FIG. 8 is a cross-sectional view for explaining a conventional stacked capacitor having a fin structure.

[Explanation of symbols]

101, 201 Silicon substrate 102, 202 Element isolation region oxide film 103, 20
3 Word line 104a, 204a Node diffusion layer 104b, 2
04b Bit diffusion layer 105, 112, 212,
215 Interlayer insulating film 106, 206 Node contact hole 107, 207 Polycrystalline silicon film 108 Polycrystalline silicon film 109 containing oxygen,
209 Node electrode 110, 210 Capacitive insulating film 111, 212 Cell plate electrode 113, 21
3 Bit contact hole 114, 214
Bit line 216 silicon oxide film

Claims (4)

[Claims] 1. A semiconductor device in a dynamic random access memory having a stacked capacitor, comprising a laminated polycrystalline silicon film including at least one layer of polycrystalline silicon film containing oxygen as a node electrode of the capacitor. . 2. A method for manufacturing a node electrode of a dynamic random access memory comprising one transistor and one stacked capacitor, in which the transistor is formed on the surface of a silicon substrate, an interlayer insulating film is deposited on the entire surface, and the node electrode is forming a contact hole;
The laminated polycrystalline silicon film is formed by forming a laminated polycrystalline silicon film including at least one layer of a type polycrystalline silicon film and an n-type polycrystalline silicon film containing oxygen, and dry etching using sulfur hexafluoride gas. A method for manufacturing a semiconductor device, comprising the step of etching a polycrystalline silicon film to form the node electrode. 3. In the step of forming the laminated polycrystalline silicon film, a non-doped polycrystalline silicon film is deposited, and the non-doped polycrystalline silicon film is exposed to an oxygen atmosphere to form a layered polycrystalline silicon film on the surface of the non-doped polycrystalline silicon film. a step of forming a polycrystalline silicon film containing oxygen and forming an undoped laminated polycrystalline silicon film consisting of a non-doped polycrystalline silicon film and a non-doped polycrystalline silicon film containing oxygen; 3. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of diffusing phosphorus into the film. 4. The step of forming the laminated polycrystalline silicon film includes forming the n-type polycrystalline silicon film using a silane-based gas containing phosphine, and exposing the n-type polycrystalline silicon film to an oxygen atmosphere. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of forming the n-type polycrystalline silicon film containing oxygen on the surface of the n-type polycrystalline silicon film.