JPH03147364A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an extremely fine aluminum contact stably and at high yield rate by covering an opposed electrode with an etching mask, and removing the insulating film between the bit line layer at a nonmemory cell part and the charge accumulated electrode layer, and then forming the insulating layer between an opposed electrode layer and a wiring layer and the aluminum contact. CONSTITUTION:An accumulated electrode-substrate contact 32, an accumulated electrode 9, and a capacity insulating layer 10 are made in this order, and after an opposed electrode 11 is formed, the opposed electrode 11 is cut out with an opposed electrode resist pattern 14. An unnecessary second interlayer insulating film 8 is removed only from a peripheral circuit part 30, where a deep aluminum contact exists, with a resist pattern 15 to cover a cell part 29, and the third interlayer insulating film 12 is accumulated anew, and a contact hole for aluminum wiring, that is, an opposed electrode-aluminum contact 34, an aluminum-substrate contact 35, an aluminum-gate electrode contact 36, and an aluminum-bit line contact 37 are opened, and an aluminum wiring 13 is made.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a method for manufacturing a high-density semiconductor device, but also relates to a method for manufacturing a high-density semiconductor device.Conventional technology After forming a gate electrode, a charge storage electrode using polysilicon is formed. DRAM called stack type
An example is shown in FIG. In FIG. 4, after forming an element isolation oxide film 2 on a silicon substrate 1, a MOS transistor consisting of a gate oxide film 3, a source/drain region 4, and a gate electrode 5 is formed in the element formation region, and a first
After forming the interlayer insulating film 6 and the bit line 7 in this order, the second interlayer insulating film 8, the charge storage electrode 9, and the capacitive insulating film 1 are formed.
0. Form the counter electrode 11. Furthermore, the third interlayer insulating film 1
After forming 2, contacts 38 to 41 are formed, and aluminum wiring 13 is formed. The contact force of 5 (a very deep contact that penetrates the three layers of the first interlayer insulating film 6, the second interlayer insulating film 8, and the third interlayer insulating film 12) is also a problem to be solved by the invention. In a configuration with a very deep contact hole, if the hole diameter is small, the aluminum coverage is insufficient and the contact characteristics become unstable.The present invention was devised in view of the above-mentioned problems. An object of the present invention is to provide a method for manufacturing a semiconductor device that can stably form ultra-fine aluminum contacts at a high yield in a stacked DRAM. In order to solve the problem, in a stacked DRAM that has a configuration in which a charge storage electrode, a capacitor insulating film, and a counter electrode are formed after forming the gate electrode, the bit line, and the bit line in this order, after forming the counter electrode, this counter electrode part is formed. The insulating film between the bit line layer and the charge storage electrode layer in the non-memory cell area is covered with an etching mask and removed by etching, and then the insulating film and aluminum contact are formed between the counter electrode layer and the next wiring layer. With the above-described structure, it is possible to partially remove and thin the interlayer insulating film in the peripheral circuit area where deep aluminum contacts exist.As a result, the aluminum contacts can be made shallower and the aluminum coating The reliability of the contact is improved and the reliability of the contact can be stabilized.

Example (Example 1) FIG. 1 (above) is a process cross-sectional view showing a method for manufacturing a semiconductor device in the first example of the present invention. After forming an isolation oxide film 2 on a silicon substrate 1 by the LOCO5 method, A MOS transistor consisting of a gate oxide film 3, a source/drain region 4, and a gate electrode 5 is formed in the element formation region, a first interlayer insulating film 6 is formed thereon, a bit line-to-substrate contact 31, a bit line-to-gate electrode contact 33,
The bit line layer wiring 6 and the second interlayer insulating film 8 are formed.
After forming the storage electrode-substrate contact 32, storage electrode 9, and capacitive insulating film 10 in this order, and depositing the counter electrode 11,
The counter electrode 11 is cut out using the counter electrode resist pattern 14 (FIG. 1(a)).

Next, with the resist pattern 15 covering the cell part 29, the unnecessary second interlayer insulating film 8 is removed only in the peripheral circuit part 30 where a deep aluminum contact exists (FIG. 1(b)), and a new third interlayer insulating film 12 is removed. 1(C)), contact holes for aluminum wiring are opened, that is, counter electrode-aluminum contact 34, aluminum-substrate contact 35, aluminum-gate electrode contact 36, and aluminum-bit line contact 37. Forming aluminum wiring 13 (first
Figure (d)). By doing this, leakage between each wiring can be suppressed. (1) Aluminum contacts 35, 36, and 37 can be made shallow,
When etching the deep contacts (35, 36) among the contacts 34 to 37, there is less over-etching of the shallow ones (34, 37). (2) Shallow contacts If the hole diameter is the same, the aluminum coverage will be better. Although two improvements were obtained in that the reliability of the contact was increased (Embodiment 2), FIG. The first and second interlayer insulating films 6 and 8 are etched by an appropriate amount using a resist pattern 16 enlarged by 0 to 5 microns in radius of the resistor peripheral circuit aluminum contact dimension formed up to the counter electrode in the same manner as in the embodiment. Figure 2(a)). After that, a third interlayer insulating film 12 is deposited, and this is etched with an aluminum contact resist batten 17 to form an opening (FIG. 2(b)), and an aluminum wiring is formed in the same manner as in Example 1.
A relatively large step difference between the non-cell portion and the cell portion where the interlayer insulating film is etched is limited to only the periphery of the aluminum contact, making it easier to form the aluminum resist pattern 17.

(Embodiment 3) FIG. 3 is a process sectional view showing a method for manufacturing a semiconductor device in a third embodiment of the present invention. Following the steps up to FIG. Then, the second and first interlayer insulating films 8.6 are etched by an appropriate amount, and the steps shown in FIGS. It is possible to reduce the number of times by one and obtain the same effect.Also, the second layer between the bit line layer and the charge storage electrode layer in the non-memory cell part
The charge storage electrode 9 itself is used as a mask for etching and removing the insulating film 8 of As is clear from the above explanation, the method of etching away the gate electrode and the bit line according to the present invention, In a stacked DRAM having a configuration in which a charge storage electrode, a capacitive insulating film, and a counter electrode are formed, the aluminum contact in the peripheral circuit can be made shallower, and the reliability of the aluminum contact can be improved, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a process cross-section diagram of a second embodiment of the present invention. FIG. 4
The figure is a cross-sectional view of the configuration of a conventional stacked DRAM.

Claims (4)

[Claims] (1) In a stacked DRAM in which a charge storage electrode using polysilicon is formed after forming a gate electrode, the gate electrode and bit line are formed in this order, and then the charge storage electrode, capacitive insulating film, and counter electrode are formed. In the semiconductor device, after forming the counter electrode, the insulating film between the bit line layer and the charge storage electrode layer in the non-memory cell part is etched away using an etching mask, and then the counter electrode layer and the next wiring layer are removed. 1. A method of manufacturing a semiconductor device, comprising forming an insulating film between. (2) For the mask that etches and removes the insulating film between the bit line layer and charge storage electrode layer in the non-memory cell area, remove the aluminum contact in the cell area from a normal aluminum contact mask and contact the aluminum contact in the non-memory cell area. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a resist pattern with enlarged holes is used. (3) A resist mask with the charge storage electrode patterned thereon is used as a mask for etching and removing the insulating film between the bit line layer and the charge storage electrode layer in the non-memory cell part, and after the charge storage electrode is processed, Claim 1, characterized in that the insulating film between the bit line layer and the charge storage electrode layer in the non-memory cell portion is removed by etching.
A method for manufacturing a semiconductor device according to section 1. (4) Using the charge storage electrode itself as a mask for etching and removing the insulating film between the bit line layer and the charge storage electrode layer in the non-memory cell part, after processing the charge storage electrode and removing the photoresist, the non-memory cell 2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film between the bit line layer and the charge storage electrode layer is removed by etching.