JPH02281650A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To lessen the occupied area on a semiconductor chip by a method wherein the capacitor is provided with a laminated capacity section, a first and a second opening, a first and a second insulating film, and a first and a second conductor layer. CONSTITUTION:A field oxide film 2 is formed on a silicon board 1, and a lower insulating film is formed thereon. Then, a capacitor electrode 4 is formed on a silicon nitride film 3, and a silicon nitride film 5 is deposited thereon to form a dielectric layer. Next, an electrode 6 is formed on the silicon nitride film 5, a structure composed of the silicon nitride film 3 to the capacitor electrode 6 is successively laminated in repetition, and a silicon nitride film 7 is deposited thereon as an uppermost layer to constitute a multi-structured laminated capacitive section. Then, the laminated capacitive section is selectively etched in an isotropic manner to form a first opening 8. Only the inside of the opening 8 is selectively subjected to an isotropic etching to remove the side face of the capacitive section electrode 6 which contains phosphorus atoms as impurity. Then, a silicon nitride film 9 is formed on the surface including the opening 8, which is isotropically etched to remove the part of the silicon nitride film 9 on the flat part. Next, a polycrystalline silicon layer 10 is formed on the surface including the opening 8 to be filled into the opening 8, and boron atoms are thermally diffused into the polycrystalline silicon layer 10 as impurity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a capacitor and a method of manufacturing the same.

[Conventional technology]

In a conventional semiconductor device, a dielectric layer is sandwiched between each capacitor electrode on an insulating layer provided on a semiconductor substrate, and the capacitor electrodes are alternately drawn out and electrically connected to external wiring.

In the prior art, a capacitor is formed by alternately patterning capacitor electrodes by depositing a conductor layer and using photolithography technology each time a capacitor electrode is formed layer by layer via a dielectric layer.

[Problem to be solved by the invention]

In conventional semiconductor devices, when creating a large capacitance capacitor on a semiconductor substrate, it is necessary to increase the opposing area of capacitor electrodes, so a laminated structure in which capacitor electrodes and dielectric layers are stacked alternately is used. It will be done.

With conventional technology, patterning using photolithography must be performed each time each capacitor electrode is formed, so increasing the number of layers in the laminated structure significantly increases the number of manufacturing steps, and the number of layers in the laminated structure increases. As a result, the area per layer of the capacitor electrode has become large. Furthermore, since the shape of each capacitor electrode is different and the contact portion is uneven, it is necessary to provide a large margin for the contact portion, which increases the area occupied by the capacitor on the semiconductor chip.

[Means to solve the problem]

In the semiconductor device of the present invention, two types of conductive layers with different chemical properties are alternately laminated with a capacitive film in between to form a laminated structure, and this laminated structure is selectively anisotropically etched to form a cut surface. and selectively etching the cut surface with chemical substances having different etching speeds for the two types of conductive layers to selectively establish an electrical connection with one of the two types of conductive layers. Therefore, the capacitor can be multilayered without using a patterning process using photolithography technology for each conductive layer formation, and the area occupied by the capacitor on the semiconductor chip can be reduced.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(j) are a plan view of a semiconductor chip and a process order diagram for explaining one embodiment of the present invention.A-A
'It is a line cross-sectional view.

First, as shown in FIGS. 1(a) and 1(b), a silicon oxide film is deposited on a silicon substrate 1 to a thickness of 950 nm by vapor phase growth.
Field oxidation deposited to the thickness of! form 2. Next, a silicon nitride film 3 of 150 nm is deposited on the field oxide film 2.
A lower insulating film is formed by depositing the lower insulating film to a thickness of m. Next, a polycrystalline silicon film is deposited to a thickness of 400 nm on the silicon nitride film 3, and boron atoms are implanted by ion implantation to form the capacitor electrode 4. Next, a silicon nitride film 5 is deposited to a thickness of 50 nm on the polycrystalline silicon film 4 to form a dielectric layer. Next, a polycrystalline silicon film is deposited to a thickness of 400 nm on the silicon nitride film 5, and phosphorus atoms are implanted by ion implantation to form the capacitor electrode 6. Next, the silicon nitride film 3 described above is applied onto the capacitor electrode 6.
Repeat the above steps in order to stack the layers. Next, silicon nitride M7 was deposited as the top layer to a thickness of 50 nm to form a multilayer structure. A laminated capacitor section is formed. Next, the laminated capacitor section is selectively etched using an anisotropic etching method to form the first opening 8.

Next, as shown in FIG. 1(c), only the inside of the opening 8 is isotropically etched with a hydrazine aqueous solution to remove the side surface of the capacitor electrode 6 containing phosphorus atoms as an impurity.
00 nm thickness is removed. At this time, the capacitor electrode 4 containing boron atoms has a lower etching rate than the capacitor electrode 6 containing phosphorus atoms, so it is not etched much.

Next, as shown in FIG. 1(d), a silicon nitride film 9 is formed to a thickness of 200 nm on the surface including the opening 8 by low pressure vapor phase epitaxy. At this time, since the side surface of the capacitor electrode 6 is deeply etched, the silicon nitride film 9 deposited on that portion is thicker than on other portions.

Next, as shown in FIG. 1(e), the silicon nitride film 9 is isotropically etched with hot phosphoric acid to etch the silicon nitride film 9 in the flat part.
remove. At this time, the silicon nitride adhering to the recess on the side surface of the capacitor electrode 6 is left unetched. Next, a polycrystalline silicon layer 10 is deposited on the surface including the opening 8, and the opening 8 is filled with impurities. As a result, boron atoms are thermally diffused into the polycrystalline silicon film 10. Next, a silicon nitride film 11 is laminated to a thickness of 200 nm on the polycrystalline silicon layer 10 to form a capacitor insulating film. Next, the laminated capacitor section is selectively and sequentially etched to form a second opening 12.

Next, as shown in FIG. 1(f), only the inside of the opening 12 is selectively etched with a hydrazine aqueous solution to remove 500% of the side surface of the capacitor electrode 6 containing phosphorus atoms as impurities.
Only nm thickness is removed.

Next, in the same manner as in the case of the first opening 8, a silicon nitride film 13 is formed to a thickness of 200 nm, and the silicon nitride film 13 is isotropically etched with hot phosphoric acid to etch the side surface of the capacitor electrode 6. The silicon nitride film 13 is left only on.

Next, as shown in FIG. 1(g), the side surface of the capacitor electrode 4 containing boron atoms as an impurity was coated with dilute nitric acid at a 900-degree angle.
It is etched and removed by a thickness of nm. At this time, the side surfaces of the capacitor electrode 6 are not etched because they are covered with the silicon nitride film 13.

Next, as shown in FIG. 1(h), a silicon nitride film 14 of 300 nm is deposited on the surface including the opening 12 by low pressure vapor phase epitaxy.
Form to a thickness of m.

Next, as shown in FIG. 1(i), the silicon nitride film 14 is isotropically etched with hot phosphoric acid to expose the side surface of the capacitor electrode 6.

Next, as shown in FIG. 1<j), a polycrystalline silicon layer 15 is deposited on the surface including the opening 12 to fill the opening 12, and phosphorus atoms as impurities are thermally diffused to form the capacitor electrode 6. Form an external lead electrode connected to the Next, the multilayer capacitor is selectively anisotropically etched to form a multilayer capacitor in a region including the opening 10.12, and the outer peripheral side of the multilayer capacitor is thermally oxidized to form a silicon oxide film 16. Next, the silicon nitride film 11 is selectively etched to form a contact opening 17 in the polycrystalline silicon layer 10, and an aluminum layer is laminated to a thickness of 10.5 μm, and then selectively etched to form a polycrystalline silicon layer 10. Electrode 1 connected to crystalline silicon layer 10
8a and an electrode 18b connected to the polycrystalline silicon layer 15, respectively.

Here, instead of providing the openings 8 and 12, the multilayer capacitor is selectively etched to form a multilayer capacitor, and the capacitor electrodes 4 and 6 exposed on two opposing cut surfaces of the multilayer capacitor are etched. A similar structure can be obtained by processing in the same manner as in the steps described above.

〔Effect of the invention〕

As explained above, the present invention can significantly increase the number of conductive layers of a capacitor provided on a silicon substrate, thereby reducing the area per layer of capacitor electrode and contact area, and reducing the area occupied on the capacitor chip. It is possible to reduce the

[Brief explanation of drawings]

FIGS. 1(a) to 1(j) are a plan view of a semiconductor chip and A-A' shown in order of steps for explaining one embodiment of the present invention.
FIG. 1... Silicon substrate, 2... Silicon oxide film, 3...
・Silicon nitride film, 4... Capacitive part electrode, 5... Silicon nitride film, 6... Capacitive part electrode, 7... Silicon nitride film,
8... Opening, 9... Silicon nitride film, 1o... Polycrystalline silicon layer,... Silicon nitride film, 2... Opening, 4... Silicon nitride film, 5... Polycrystalline silicon layer. Crystalline silicon layer, 6...Silicon oxide film,...Opening, 8b...Electrode.

Claims (2)

[Claims] (1) The first layer is placed on the field oxide film provided on the semiconductor substrate.
a laminated capacitor section in which a capacitor electrode and a second capacitor electrode are alternately laminated with dielectric layers interposed therebetween; an opening, a first insulating film provided on a side surface of the second capacitor electrode in the first opening, and the first capacitor electrode by filling the inside of the first opening. a first conductor layer, a second insulating film provided on a side surface of the first capacitor electrode in the second opening, and a second insulating film that fills the second opening and is connected to the second capacitor electrode. A semiconductor device characterized by having a second conductor layer. (2) The first layer is placed on the field oxide film provided on the semiconductor substrate.
a step of forming a laminated capacitor part by alternately laminating capacitor electrodes and a second capacitor electrode having a higher etching rate than the first capacitor electrode via a dielectric layer, and selectively forming the laminated capacitor part. forming a first opening by sequentially anisotropically etching the second capacitor electrode, and isotropically etching the second capacitor electrode with an etching solution having a higher etching rate than the first capacitor electrode. a step of partially removing a side surface of the second capacitor electrode in a first opening to provide a recess; depositing a first insulating film on the surface including the first opening; and anisotropic etching. and leaving the first insulating film only in the recess on the side surface of the second capacitor electrode, and filling the first opening with a first conductor layer and connecting it to the first capacitor electrode. a step of selectively anisotropically etching the laminated capacitor portion to provide a second opening; and partially etching a side surface of the second capacitor electrode in the second opening by isotropic etching. forming a recess by depositing a protective film on the surface including the second opening, and anisotropically etching the protective film to leave the protective film only in the recess; and isotropically etching the first capacitor. etching the side surface of the electrode deeper than the recess; and depositing a second insulating film in the second opening and anisotropically etching the second insulating film only on the side surface of the first capacitor electrode. a step of removing the protective film by isotropic etching to expose the side surface of the second capacitor electrode;
A method for manufacturing a semiconductor device, comprising the step of filling a conductor layer and connecting it to the second capacitor electrode.