JPH0445571A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To see that the step at the wiring part to become a bit line does not become sharp by removing the lower electrode by continuous etching to expose the lower electrode during the patterning of an upper electrode. CONSTITUTION:A polycrystalline Si film 115 and an insulating film 116 are made continuously on a capacitor insulating film 114. Next, the insulating film 116 is etched, until a polycrystalline Si film 190 is exposed, so as to form an opening 117 which includes bit contact. Next, an insulating film is made again on the whole face, and by etchback treatment, it is etched and left as sidewalls 118 and 119 so that they may cover the sides of the polycrystalline Si film 115 to become an upper electrode and the polycrystalline Si film pattern to become a lower electrode. Lastly, wiring 120 is made to be conductive with the Si film 190 at the bit line contact part, thus a stacked memory cell can be gotten. Thereupon, the step at the wiring part to become the bit line does not become sharp, and wiring coverage improves.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention provides a DRA having stacked memory cells.
M (Dynamic Random Ac
The present invention relates to a method of manufacturing a semiconductor device 1 that greatly improves the step coverage of IC and minimizes the electrode area.

(Prior art) The miniaturization of so-called planar DRAMs, in which cell capacitors are formed on the surface of a Si substrate, does not allow for higher integration due to area limitations. Structural cells have been vigorously developed.

Among them, stacked capacitor cells are widely used due to their ease of manufacturing, but in order to achieve future miniaturization, stacked capacitor cells are widely used.
Furthermore, an increase in capacity is essential.

FIG. 3 shows a cross-sectional structure of a typical conventional stacked capacitor cell. In FIG. 3, 1 is a semiconductor Si substrate, and 2.3 is a diffusion layer having conductivity opposite to that of the semiconductor substrate 1. In FIG.

Further, 5 is a thin insulating film, and a transfer gate electrode is formed on the thin insulating film, and 7 and 8 are insulating films for separating the lower electrode and the gate electrode, respectively.

A polycrystalline Si film 9 is formed on the insulating films 7 and 8. This polycrystalline Si film 9 serves as a lower electrode. On this polycrystalline Si film, there is a thin insulating film 1 that becomes a capacitor.
0 is formed, and normally this insulating film 10 is an oxide film,
A composite membrane of nitride membranes is used.

Polycrystalline S, which will become the capacitor electrode, is placed on this thin insulating film 10.
An i film 11 is formed, and an oxide film 1 is further formed thereon.
2. Metal wiring layers 13 are sequentially formed.

The insulating film 12 is an insulating film for separating the lower wiring layer and the upper M-thread wiring, and is usually an oxide film containing impurities such as boron and phosphorus.

Further, the metal wiring layer 13 is electrically connected to the semiconductor substrate l via the contact portion 14.

Note that 15 is a contact portion formed so that the diffusion layer 2 and the polycrystalline Si film 9 are electrically connected.

(Problems to be Solved by the Invention) The conventional stacked capacitor cell has the above-described structure, and there are problems listed below when miniaturizing the cell.

(1) Since the capacitor capacitance is defined by the area of the lower electrode made of polycrystalline Si films 9 and 11, the area of the upper electrode, and the thin insulating film thickness 10 interposed between the electrodes, in order to advance miniaturization, maintaining the electrode area, There are many difficulties, such as the need to make the film thinner without compromising film quality.

(2) When miniaturization occurs, the contact portion 15 that establishes conduction with the semiconductor substrate in the memory cell portion is miniaturized, and especially in a stacked structure, the steps become steep, so the coverage of the steps of the aluminum wiring at the contact portion is reduced. Problems with reliability, such as a decrease in contact resistance and an increase in contact resistance due to solid-phase epitaxial contact, become apparent.

This invention is a method for manufacturing a semiconductor device that solves the problems of the above-mentioned conventional technology, such as the difficulty in thinning the electrode while maintaining the area, and the deterioration of reliability due to miniaturization. It provides:

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor device in which an insulating film is formed on an active region of a semiconductor substrate after forming a transfer gate electrode and flattened to form bits and After forming a contact hole for the cell, filling this contact hole with a polycrystalline Si film that will become a lower electrode, and sequentially forming a capacitor electrode, an upper electrode, and an insulating film, the lower electrode is also etched by continuous etching when patterning the upper electrode. This method introduces a process of removing the lower electrode to expose the lower electrode and dividing it into individual bits.

(Function) According to the present invention, since the above steps are introduced in the method for manufacturing a semiconductor device, the insulating film is flattened before patterning the lower electrode, and the lower electrode can be patterned with high precision. and then the capacitor electrode,
The upper electrode and the insulating film are formed, and the lower electrode is patterned at the same time as the lower electrode is patterned.
Since the bit line is divided into focus units, the lower electrode is buried in the contact portion of the bit line in advance, and the level difference in the wiring portion that will become the bit line does not become steep, thereby eliminating the above-mentioned problem.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. Figure 1(a) to Figure 1(
i) is a process sectional view of one embodiment.

First, in FIG. 1fa), 100 is a Si semiconductor substrate, and 101 and 102 are thick field insulating films separating active regions 191 of memory cells.

Next, as shown in FIG. 1, a thin gate insulating film 1 is formed.
03 is formed on the active region 191, mainly a polycrystalline Si film,
Transfer gate electrode 104 made of polycide structure
, 105, this Si semiconductor substrate 1
Diffusion layer 106.107.1 with conductivity opposite to 00
08 is formed.

Next, as shown in FIG. 1(c), an insulating film is formed on the entire surface, and a flat layer 109 is obtained by depositing an insulating film containing poron or phosphorus as an impurity at a high concentration or using a known etch-back technique.

Next, contact holes 110 and 11 are provided to establish conduction between the polycrystalline Si film that will become the capacitor lower electrode and the Si semiconductor substrate 100, and between the wiring that will become the bit line and the Si semiconductor substrate 100.
As shown in FIG. 1(b), holes 1 and 112 are formed by photolithography and etching.

Next, as shown in FIG. 1(e), the contact holes 110, 111, and 112 are filled with a flatness ratio of 300.
Low pressure CVD of polycrystalline Si film with a deposited film thickness of less than 0.
After deposition by the method, an area corresponding to two bits is formed by patterning with a bit contact in between to obtain a polycrystalline Si film pattern 113, and then a capacitor insulating film 114 is formed on the entire surface.

FIG. 2 shows a plan view of the memory cell at the stage obtained in the process of FIG. 1(e). 20 in this figure 2
The area surrounded by 0 indicates an active area, and is the same as the active area 191 in FIG. 1(a). Further, 204 and 205 are wirings of transfer gate electrodes. 206 and 208 are contact holes for establishing electrical conduction between the polycrystalline S+ film and the Si substrate, and are filled with the polycrystalline Si film pattern 113 shown in FIG. 1(e).

Further, 207 in FIG. 2 is a contact for establishing conduction between the bit wiring and the St semiconductor substrate, and similarly, 207 in FIG.
It is filled with a polycrystalline Si film pattern 113 shown in e). 201 is a pattern for forming a polycrystalline Si film that will become the lower electrode. Normally, the pattern is formed so that it is separated at the bit line contact, but in this invention, 2 bits are formed as one body. There is.

Here, the explanation returns to FIG. 1. In FIG. 1(f),
A polycrystalline Si film 115 serving as an upper electrode is formed on the capacitor insulating film 114. Continuously form insulation #116.

Next, as shown in FIG. 1 (8), the insulating film 116 is
．． Polycrystalline Si film 115. Capacitor insulation Ill 14.
The polycrystalline ST film pattern 113 is removed by etching. At this time, a polycrystalline 51M corresponding to the polycrystalline Si film pattern 113 embedded in the bit contact portion is also added.
Etching is performed until 190 is exposed.

In the plan view of FIG. 2, the upper electrode pattern 203 is etched to ensure that the lower electrode 201 is separated, as shown by the broken line.

Next, as shown in FIG. 1(c), an insulating film is again formed on the entire surface, and a well-known etch-back process is performed to form a polycrystalline Si layer film 115 that will become the upper electrode. A sidewall film 11 is formed to cover the side surface of the polycrystalline St film pattern 113 that will become the lower electrode.
It will remain as 8,119.

Finally, as shown in FIG. 1(i), a wiring 120 mainly made of aluminum is formed so as to be electrically conductive to the polycrystalline Si film 190 embedded in the via line contact portion, and the stacked memory cell is get.

(Effects of the Invention) As described in detail above, according to the present invention, after forming a transfer gate electrode, after flattening the insulating film to form a contact hole, the lower electrode fills the contact hole and connects the capacitor insulating film to the upper part. The electrode and insulating film were formed one after another, and the upper electrode was patterned until the lower electrode was exposed, dividing the lower electrode into bits at a time, so the lower insulating film was sufficiently planarized before patterning the lower electrode. Therefore, the patterning accuracy and alignment margin of the lower electrode are improved, and the effective area of the electrode can be expanded.

Further, since a polycrystalline Si film is embedded in advance in the bit line contact portion, the level difference in the wiring portion that will become the bit line does not become two steep, and the wiring coverage is greatly improved.

Further, since the polycrystalline Si films of the upper and lower electrodes are etched continuously, there is an advantage that there is no need to consider alignment margins, etc.

[Brief explanation of drawings]

1(a) to 1(i) are process sectional views of an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 is a process sectional view of the process end stage of FIG. 1(e) in the same embodiment The plan view and FIG. 3 are cross-sectional views of a conventional stacked capacitor cell. 100...Si semiconductor substrate, 101.102...Field insulating film, 103...Gate insulating film, 1041
05.204,205...Transfer gate electrode,
106-10 days...diffuse layer, 109...flat layer,
110-112, 117, 206-208... contact hole, 113... polycrystalline St film pattern, 114...
...Capacitor insulating film, 115.190...Polycrystalline S
i film, 116... Insulating film, 118.119... Side wall, 191.200... Active region. 191: Active 4 motions Before the process of the present invention Figure 3

Claims (1)

[Claims] (a) After forming a transfer gate electrode in an active region on a semiconductor substrate, a step of forming an insulating film with a flattened surface; (b) forming a contact hole conductive to the substrate; Steps of sequentially forming in this contact hole a polycrystalline Si film and a capacitor insulating film that will become a lower electrode, and a polycrystalline Si film and an insulating film that will become an upper electrode; (c) forming the upper electrode in a region that will become a bit contact; The polycrystalline Si insulating film, the polycrystalline Si film, the capacitor electrode, and the polycrystalline Si film that will become the lower electrode are removed by etching, and the polycrystalline Si film of the lower electrode is removed by etching.
Polycrystalline S divided into bits and filled in the bit contact area
A method for manufacturing a semiconductor device, comprising: exposing the i film; and (c) forming a sidewall film by covering the sidewall of the portion removed by the etching with a polycrystalline Si film.