JPS63107161A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To obtain a semiconductor element, in which crystallinity is very excellent and homogeneity of quality in a wafer is very excellent, by using bulk silicon itself as a silicon layer (SOI), which is formed on an insulator. CONSTITUTION:An n-type silicon substrate 1 is coated with a thin silicon dioxide formed by thermal oxidation. The irregularities on the surface thereof are flattened by polishing. Then, the n-type silicon substrate 1 is made thin to a thickness of about 10 microns by lapping from the rear surface of the n-type silicon substrate 1. The n-type silicon substrate 1 is made thin to a thickness of about 1.5 microns by polishing. Thus the surface position of the thin n-type silicon substrate can be made to be the same position of the surface of an element isolating region consisting of a silicon dioxide film 4. An SOI structure, in which element regions are isolated by a dielectric body matching a desired element structure, is obtained. Since the silicon substrate having the defect density of the SOI, which is formed in this way, is used, the semiconductor element, in which homogeneity in a wafer is excellent, is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device at high speed and with low power consumption.

[Conventional technology]

Bipolar element and complementary field effect element (0MO8 element)
By forming these two elements on the same chip and taking advantage of the characteristics of these two elements, high speed and low power consumption can be achieved. When realizing such a device (hereinafter referred to as Bi-CMOS), an n-type epitaxial silicon film is usually formed on a p-type silicon substrate having an embedded layer, and a desired npn+g bipolar film is formed on the epitaxial silicon film. Manufacture transistors and CMOS devices. In order to further increase latch-up resistance and high speed performance, it is extremely effective to form such an element on an insulator. So-called S, which forms a single crystal silicon film on an insulator
OI (Silicon on In5ulator)
A conventionally known technique is, for example, to deposit a polycrystalline silicon film on an insulator and recrystallize it by melting the polycrystalline silicon film using a laser or an electron beam.

A desired element is then manufactured using the single crystal silicon film formed by such a method.

[Problem that the invention seeks to solve]

The conventional manufacturing method described above causes the following problems. When recrystallizing a polycrystalline silicon film on an insulator,
A recrystallization method using a laser or an electron beam can locally form high-quality single-crystal silicon with almost no defects. However, since the beam shape is a spot beam with a diameter of several tens of microns or a linear beam with a length of at most several hundred microns, the beam must be scanned back and forth many times in order to recrystallize the entire wafer surface. Therefore, it is difficult to uniformly recrystallize the entire wafer due to fluctuations in the scanning system, beam intensity, or non-uniformity of the substrate structure. Therefore, there is a need for a manufacturing method that can uniformly form a high quality single crystal silicon region over the entire wafer surface on an insulator and is compatible with the Bi-CMO8 element structure.

[Failure to solve the problem]

The manufacturing method of the present invention includes a step of forming a groove in one main surface of a first semiconductor substrate to partition this one main surface into a plurality of parts;
A step of coating the surface of the one principal surface and at least a surface portion of the helmet with a dielectric material, and a step of coating the one principal surface of the first semiconductor substrate covered with the dielectric material and a second semiconductor substrate covered with the dielectric material. The method includes a step of bonding one main surface of the first semiconductor substrate, and a step of exposing the groove and the first semiconductor substrate by polishing from the main surface side opposite to the one main surface of the first semiconductor substrate.

5. Forming a groove in one principal surface of the first semiconductor substrate to divide the one principal surface into a plurality of parts, and covering the surface of the one principal surface and at least the surface portion of the groove with a dielectric material. S.O.
An underlying isolation layer of I and an element isolation region made of a dielectric material can be easily formed. The depth of this trench is formed to be greater than the depth required for element isolation.

Further, the coating with the dielectric may be formed by oxidizing the semiconductor substrate, the dielectric may be deposited by vapor phase growth, or the dielectric may be oxidized first and then deposited. good.

Preferably, this dielectric layer is silicon dioxide. In order to bond semiconductor substrates with silicon dioxide layers formed on their surfaces, for example, Applied Physics Letters, 1986, Vol. 48, p. 78 (App.
Lied Physics Letters, Vol.

48, P, 78 (1986'):], silanol junctions can be used.

Furthermore, by adopting such a manufacturing method, a high concentration buried layer for lowering the collector resistance of a bipolar transistor can be easily formed by forming it in advance on the surface of one main surface of the first semiconductor substrate. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 and FIG. 2 respectively show the first embodiment of the present invention. It is a vertical cross-sectional view showing the manufacturing process in each of the second embodiments.

[First Example] As shown in Fig. 1(a), the specific resistance is 10/my n 54
On the surface of the silicon substrate 1, a 1×
An N buried layer 2 doped with 1019 pieces/cm 3 of arsenic (As) and having a thickness of 0.5 μm is formed. Next, as shown in FIG. 1(b), p-MOS, n-MOS
A groove 3 having a depth greater than the depth necessary for element isolation is formed in a portion that will become an element isolation region for separating bipolar elements from each other. For example, 1 micron and 1.5 micron are used as the length of the dispensing area.

Next, as shown in FIG.
deposit. At this time, the n-type silicon substrate 1 may be first covered with a thin layer of silicon dioxide by thermal oxidation, and then a silicon dioxide film may be deposited.

In this case, the interface between the n-type silicon substrate 1 and the silicon dioxide film will be of high quality with few defects.

For example, 1 micron is used as the thickness of the silicon dioxide film 4 in the region excluding the groove 3. Next, Figure 1(d)
As shown in FIG. 2, the surface irregularities of the silicon dioxide film 4 are made flat by boring. In polishing, for example, about 200 angstroms of silica (Sin) is used as the polishing liquid.
An ammonia solution mixed with is used and polished according to Isoshiro et al. Next, as shown in FIG. 1(e), an n-type silicon substrate 5 whose surface has been thermally modified by about 3000 angstroms is prepared, and after the silicon dioxide surfaces of both substrates are brought into close contact with each other, heat treatment is performed. The two silicon substrates are bonded by utilizing the fact that the surfaces of the silicon dioxide films of both substrates are bonded (by applying the silicon dioxide film). For example, heat treatment is 1000
°C, Nt8 atmosphere is used. Next, as shown in FIG. 1(f), the n-type silicon substrate 1 is thinned to about 1f:10 microns by lapping from the back side of the n-type silicon substrate 1, and then the n-type silicon substrate 1 is thinned by boring.
Thin to about 1.5 microns. In polishing, silicon can be selectively removed by polishing, for example, by using a mixture of silica particles with a particle size of 50A and aqueous ammonia, and the surface position of the thinned n-type silicon substrate 1 is shown in FIG. As shown in f), it can be made the same as the surface of the element isolation region made of the silicon dioxide film 4. In this way, an SOI structure is obtained in which the valley element regions are separated by a dielectric material that is in good agreement with the desired element structure. next,
As shown in FIG. 1(g), the pt! 1Ni6 is formed. In forming the p-type layer 6, a normal impurity diffusion method is used. After that, Figure 1 (
h) pJ Zeng 7, n for the kuto area of Tongzhu as shown in
- Form the n-layer 8 for the source and drain of the MO8 transistor, the collector contact, emitter, and rear regions of the npn bipolar transistor. Since the silicon substrate 1 itself, which has a defect density of 80I formed by a method such as C, is used, the defect density is less than 1 defect/crIL2 everywhere in the wafer, and the S
In Bi-MO8 formed using O-structure °,
High speed and low power consumption were achieved with a delay time of 0.5 layer seconds (nsec) and a power/delay time product of 02 pJ.

[Second Embodiment] FIGS. 2(a) to 2(g) are longitudinal sectional views showing a part of the manufacturing process in a second embodiment of the present invention.

In this embodiment, an example is shown in which the element isolation region is composed of two layers of silicon dioxide and polycrystalline silicon. First, as shown in FIG. 2(a), the surface of an n-type silicon substrate 1 with a resistivity of 1 Ω·σ is doped with As of lXl0''/c7rL3 in a portion corresponding to the position of the bipolar transistor to be finally formed. An N+ buried layer 1-2 with a thickness of 0.5 microns is formed.As shown in FIG. 2(b), a p-MOS
, n-MOS, and a groove 3 having a depth greater than the depth necessary for element isolation is formed in a portion corresponding to an element isolation region for separating the bipolar element regions from each other. width of the separation area,
For example, 1 micron or 1.5 micron is used as the depth, and the depth of the groove 3 is set to be 15 microns or more. Next, as shown in FIG. 2(C), the surface of the n-type silicon substrate 1 is coated with a silicon dioxide film 4 having a thickness of 0.2 microns.

At this time, the silicon dioxide film 4 may be formed by thermal oxidation. In this case, the interface between the n-type silicon substrate 1 and the silicon dioxide film 4 will be of high quality with few defects. Alternatively, silicon dioxide may be deposited. Next, see Figure 2 (
As shown in d), a polycrystalline silicon film 9 of about 2 microns is deposited so that the groove 3 is completely filled. In this way, by covering the groove 3 with a thin silicon dioxide film 4, it is possible to isolate the elements, and by filling the remaining part with polycrystalline silicon 9, which is the same material as the substrate, the difference in thermal expansion coefficient can be reduced. Mechanical distortion and cracks caused by this can be prevented. Next, as shown in FIG. 2(e), this polycrystalline silicon film 9 is left only in the trenches 3 by boring so that the surface of the substrate becomes flat. In this borising, for example, by using a mixed solution of silica fine particles with a particle size of 50 angstroms and aqueous ammonia, only the polycrystalline silicon can be selectively removed by polishing. In other places, the silicon dioxide film 4 can remain on the surface and the inside of the groove 3 can be filled with polycrystalline silicon.

Next, as shown in FIG. 2(f), an n-type silicon substrate 5 whose surface is thermally oxidized to a thickness of about 3000 angstroms is prepared, and the p-type silicon substrate surface and the n-type After the surfaces are brought into close contact with the silicon substrate 10, the silicon dioxide films of both substrates are bonded by heat treatment, and the two silicon cram boards are bonded together.The heat treatment is performed at, for example, 1000° C0N in an atmosphere. Next, as shown in Figure VJ2 (g), the n-type silicon substrate 1 is made thinner to about 10 microns by lapping from the back side of the n-type silicon substrate 1, and then the pn-type silicon substrate 1 is further made thinner by boring. In polishing, for example, by using the same technique after removing the polycrystalline silicon film 9, the surface of the n-type silicon 1 can be made to be at the same height as the surface of the silicon dioxide film 40 forming the element isolation region. Thereafter, a desired element is formed using a process similar to that shown in FIGS. 1(g) to (hl) of the first embodiment.

〔Effect of the invention〕

As explained above, in the present invention, since bulk silicon itself is used as the silicon layer (SOI) formed on the insulator, the silicon layer formed by the conventional recrystallization method has different characteristics. The crystallinity of 80I obtained by the invention is of extremely high quality, and the quality uniformity within the wafer is also extremely excellent. In addition, the element isolation region is also
Since it can be formed at the same time as the insulating layer for I, element isolation and the 80I structure can be formed with a simple manufacturing process. ° Even a highly concentrated buried layer can be easily formed by simply forming it on the surface of the substrate. Thus, bipolar, p-MO8.

The element region of each n-MOS transistor has an SOf structure, and is formed in a silicon layer that has the quality of bulk silicon itself. Furthermore, each element region is separated by a dielectric material, and the high concentration buried layer is also in the valley. Since it is formed in the element region as necessary, parasitic capacitance can be reduced, and C-MO8
latch-up can be prevented. Therefore, Bi-0MO8 elements that are compatible with high speed and low power consumption can be formed uniformly within the wafer.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(h) are longitudinal sectional views showing manufacturing steps in a first embodiment of the present invention. FIGS. 2(a) to 2(g) are longitudinal cross-sectional views showing manufacturing steps in a second embodiment of the present invention. 1...,... n-type silicon substrate, 2...... n
Buried layer, 3...groove, 4...silicon dioxide layer, 5...p-type/recon substrate, 6...
...p-type layer, 7...p+ layer, 8...
・n II, g... Polycrystalline silicon film. Agent: Patent Attorney Shin Uchihara
4゜￥i1 Figure foil 10 i2 figure

Claims (1)

[Claims] forming a groove on one principal surface of a first semiconductor substrate to divide the one principal surface into a plurality of parts; and coating the surface of the one principal surface and at least a surface portion of the groove with a dielectric; bonding the one main surface of the semiconductor substrate covered with the dielectric and the one main surface of the second semiconductor substrate covered with the dielectric; and the opposite main surface of the first semiconductor substrate. A method for manufacturing a semiconductor device, comprising the step of exposing the groove and the first semiconductor substrate by polishing from the surface side.