KR100297867B1 - Insulator type silicon semiconductor integrated circuit manufacturing method - Google Patents
Insulator type silicon semiconductor integrated circuit manufacturing method Download PDFInfo
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- KR100297867B1 KR100297867B1 KR1019950044537A KR19950044537A KR100297867B1 KR 100297867 B1 KR100297867 B1 KR 100297867B1 KR 1019950044537 A KR1019950044537 A KR 1019950044537A KR 19950044537 A KR19950044537 A KR 19950044537A KR 100297867 B1 KR100297867 B1 KR 100297867B1
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- single crystal
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 33
- 239000010703 silicon Substances 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000012212 insulator Substances 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000013078 crystal Substances 0.000 claims abstract description 14
- 150000002222 fluorine compounds Chemical class 0.000 claims abstract description 12
- 239000012298 atmosphere Substances 0.000 claims abstract description 9
- 239000011521 glass Substances 0.000 claims abstract description 8
- 229910052736 halogen Inorganic materials 0.000 claims abstract description 7
- 150000002367 halogens Chemical class 0.000 claims abstract description 7
- 238000005498 polishing Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000002230 thermal chemical vapour deposition Methods 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 238000010894 electron beam technology Methods 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 239000010408 film Substances 0.000 description 37
- 239000010410 layer Substances 0.000 description 15
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 239000011159 matrix material Substances 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000010453 quartz Substances 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 239000011029 spinel Substances 0.000 description 4
- 229910052596 spinel Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000003513 alkali Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
- H01L21/02645—Seed materials
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
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- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
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Abstract
유리와 같은 저가의 기판상에 단결정 실리콘을 사용한 반도체 집적회로를 형성하는 방법을 제공하고자 한다. 단결정 실리콘 웨이퍼 상에, 시드 개방부를 갖고 주로 실리콘 산화물로 이루어지는 절연층이 제공되며, 그위에 비단결정 실리콘막이 증착된다. 비단결정 실리콘막은 예컨대 스트립 히터를 사용하여 주사함으로써 시드 개방부에서 시작하여 용융되고 그에 따라 실리콘막이 된다. 이렇게 생성된 단결정막을 사용하여 소자를 형성한 후 소자 표면에는 유리기판과 같은 절연성 기판이 접착된다. 그후, 실리콘 기판은 비플라즈마 상태에서 ClF3와 같은 플루오르화 할로겐의 분위기내에 방치됨으로써 에칭된다. 플루오르화 할로겐에 의한 에칭전에, 실리콘 기판은 10 내지 100㎛의 두께로 연마될 수도 있다. 실리콘 산화물에 대한 실리콘의 선택적 에칭비가 크면, 플루오르화 할로겐은 실리콘만을 에칭한다. 즉, 실리콘 산화물은 거의 에칭하지 않는다. 따라서, 실리콘 산화물층이 과에칭되어 소자를 파괴시키는 경우가 발생되지 않는다. 이로써, 양호한 특성을 갖는 집적회로가 높은 수율로 절연성 기판상에 형성될 수 있다.A method for forming a semiconductor integrated circuit using single crystal silicon on a low cost substrate such as glass is provided. On the single crystal silicon wafer, an insulating layer having a seed opening and consisting mainly of silicon oxide is provided, on which a non-single crystal silicon film is deposited. The non-single crystal silicon film is melted starting from the seed opening, for example by scanning using a strip heater, and thus becoming a silicon film. After forming the device using the single crystal film thus formed, an insulating substrate such as a glass substrate is adhered to the surface of the device. Thereafter, the silicon substrate is etched by being left in an atmosphere of fluorinated halogen such as ClF 3 in a non-plasma state. Prior to etching with halogenated fluoride, the silicon substrate may be polished to a thickness of 10 to 100 mu m. If the selective etch ratio of silicon to silicon oxide is large, the halogenated fluoride etches only silicon. That is, silicon oxide is hardly etched. Therefore, the case where the silicon oxide layer is overetched to destroy the device does not occur. In this way, an integrated circuit having good characteristics can be formed on the insulating substrate with high yield.
Description
제1(a)도 내지 제1(d)도는 본 발명의 실시예에 따른 반도체 집적 회로를 형성하는 웨이퍼 공정을 도시하는 단면도.1 (a) to 1 (d) are cross-sectional views showing a wafer process for forming a semiconductor integrated circuit according to an embodiment of the present invention.
제2(a)도 내지 제2(c)도는 SOI형 집적회로를 형성하는 SOI 형성 공정을 도시하는 단면도.2 (a) to 2 (c) are cross-sectional views showing an SOI forming process for forming an SOI type integrated circuit.
제3도는 액정 디스플레이의 단면도.3 is a cross-sectional view of a liquid crystal display.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 단결정 실리콘 기판 12 : 실리콘 산화물막11: single crystal silicon substrate 12: silicon oxide film
13 : 시드 개방부 14 : 다결정 실리콘막13 seed opening 14 polycrystalline silicon film
16 : 실리콘 용융부 27 : 층간 절연막16 silicon melting part 27 interlayer insulating film
37 : ITO 전극 38 : 액정37: ITO electrode 38: liquid crystal
[발명의 배경][Background of invention]
[발명의 분야][Field of Invention]
본 발명은 SOI(silicon on insulator : 절연체상 실리콘)형 반도체 집적 회로의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a silicon on insulator (SOI) type semiconductor integrated circuit.
[관련 기술의 설명][Description of Related Technology]
최근, 실리콘 반도체 소자는 고속으로 동작하는 것이 요구되고 있다. 종래 방식으로 실리콘 기판상에 형성된 회로에서 이와 같은 요구사항을 만족시키기 위해서는 기판과 회로 사이의 기생 캐패시턴스가 장애물이 된다. 이 문제를 피하기 위해, 절연체로 된 기판을 사용함으로써 그와 같은 기생 캐패시턴스를 제거하는 SOI형 집적 회로가 개발되었다.Recently, silicon semiconductor devices are required to operate at high speed. In a circuit formed on a silicon substrate in a conventional manner, parasitic capacitance between the substrate and the circuit is an obstacle to satisfying such a requirement. To avoid this problem, SOI type integrated circuits have been developed that eliminate such parasitic capacitance by using an insulator substrate.
SOI형 집적 회로의 제조 방법은 일반적으로 두가지로 분류된다. 첫번째 방법에서는 사파이어, 스피넬 (spinel) 및 석영등의 물질로 이루어진 내열성이 높은 기판상에 단결정 실리콘 박막이 형성되는데, 이것은 예컨대 열적 어닐링에 의해 결정화된다. 이와같이하여 얻은 실리콘막을 사용함으로써 회로가 형성된다.The manufacturing method of the SOI type integrated circuit is generally classified into two types. In the first method, a single crystalline silicon thin film is formed on a high heat resistant substrate made of materials such as sapphire, spinel and quartz, which is crystallized by thermal annealing, for example. The circuit is formed by using the silicon film thus obtained.
사파이어, 스피넬등과 같이 그 결정 구조 및 격자상수가 실리콘 결정과 비슷한 기판 재료를 사용함으로써, 단결정 실리콘 막내에 헤테로에피텍셜 성장이 발생하여 실리콘 결정막을 산출한다. 그러나, 사파이어 및 스피넬 기판은 고가여서 큰 면적의 기판으로 형성될 수 없으므로 이 제조 방법을 생산 단계에 적용하기는 어렵다. 석영 기판은 사파이어 및 스피넬 기판보다는 저가이지만 다결정막만을 제공할 수 있다. 또한, 가장 저가인 유리 기판은 높은 처리 온도에 견딜 수 없다.By using a substrate material whose crystal structure and lattice constant is similar to that of silicon crystals, such as sapphire and spinel, heteroepitaxial growth occurs in a single crystal silicon film to yield a silicon crystal film. However, sapphire and spinel substrates are expensive and cannot be formed into large area substrates, making it difficult to apply this manufacturing method to the production stage. Quartz substrates are less expensive than sapphire and spinel substrates but can provide only polycrystalline films. In addition, the lowest cost glass substrates cannot withstand high processing temperatures.
두번째 방법에서는 단결정 실리콘 기판상에 반도체 집적 회로가 형성된 후, 소자 표면이 절연성 기판에 접착되고 단결정 실리콘 기판은 기계적 연마 또는 드라이 에칭(dry ething)에 의해 그 후면부터 얇아진다. 소자 제조 공정이 완료된 후 소자는 절연성 기판에 고정되므로, 이 제조 방법은 결정 구조 및 절연성 기판의 내열성에서 초래되는 문제가 거의 없고 실질상 단결정 소자를 제공할 수 있다 (J.P. Salemo 등의 SID International Symposium. Digest of Technical Papers. pp. 63-66. May 1992 참조).In the second method, after the semiconductor integrated circuit is formed on the single crystal silicon substrate, the device surface is adhered to the insulating substrate and the single crystal silicon substrate is thinned from the rear side by mechanical polishing or dry etching. Since the device is fixed to the insulating substrate after the device manufacturing process is completed, this manufacturing method can provide a single crystal device substantially without problems caused by the crystal structure and the heat resistance of the insulating substrate (SID International Symposium of JP Salemo et al. Digest of Technical Papers.pp. 63-66.May 1992).
J.P. Salemo 등의 이 논문에 따르면, 단결정 실리콘 기판상에 부분적 개구부(“시드 개구부(seed opening)”라 칭함)를 갖는 실리콘 산화물층 및 다결정 실리콘막이 형성된다. 이 다결정 실리콘막을 대상 용융법(zone melting method)에 의해 용융시킴으로써, 시드 개방부를 통해 단결정 실리콘 기판을 시드로 사용하여 다결정 실리콘막은 단결정 막으로 전환된다. 이 단결정막은 소자 형성에 사용될 수 있다.J.P. According to this paper by Salemo et al., A silicon oxide layer and a polycrystalline silicon film having a partial opening (called a "seed opening") are formed on a single crystal silicon substrate. By melting this polycrystalline silicon film by a zone melting method, the polycrystalline silicon film is converted into a single crystal film using a single crystal silicon substrate as a seed through the seed opening. This single crystal film can be used for element formation.
실리콘 산화막은 소자 형성층과 단결정 실리콘 기판 사이에 삽입되므로, 소자 상면이 절연성 기판에 접착된 후 단결정 실리콘 기판이 에칭될 때 소자가 파괴될 가능성이 낮다.Since the silicon oxide film is inserted between the element formation layer and the single crystal silicon substrate, there is a low possibility that the device is destroyed when the single crystal silicon substrate is etched after the upper surface of the device is adhered to the insulating substrate.
J.P. Salemo 등의 SOI 집적 회로 제조방법은 단결정 실리콘 기판의 박막화 공정시에 큰 문제점이 존재하므로 충분히 높은 양산수율(mass-production yield)이 달성되지 않는다.J.P. The SOI integrated circuit manufacturing method such as Salemo has a big problem in the thinning process of a single crystal silicon substrate, so that a sufficiently high mass-production yield is not achieved.
이 제조방법에서, 보통 단결정 실리콘 기판의 박막화는 두 단계로 수행된다. 먼저 기계적 연마가 수행되고 그 다음에 플라즈마를 사용하는 드라이 에칭에 의해 나머지 실리콘 기판이 에칭된다.In this manufacturing method, thinning of a single crystal silicon substrate is usually performed in two steps. Mechanical polishing is first performed and then the remaining silicon substrate is etched by dry etching using plasma.
드라이 에칭에 있어서의 큰 문제점은 실리콘 산화물에 대한 실리콘의 선택적 에칭비가 약 10 정도로 낮다는 것이다. 예컨대, 단결정 실리콘 기판의 두께가 10㎛ 일 경우, 드라이 에칭시에 에칭의 불균일성에 일부 기인하여 단결정 실리콘 기판의 표면에 약 3㎛의 요철이 발생할 것이다. 따라서, 단결정 실리콘 기판이 에칭에 의해 완전히 제거될 경우, 실리콘 산화물층은 몇몇 장소에서 0.5㎛만큼 과에칭(overetching)될 수도 있다. 이 과에칭은 확률적인 현상이므로, 실리콘 산화물층은 장소에 따라 1㎛ 이상 에칭될 수도 있다. 이 과에칭은 회로 전체가 불량이 되는 원인이 될 수도 있다.A major problem with dry etching is that the selective etch ratio of silicon to silicon oxide is as low as about 10. For example, if the thickness of the single crystal silicon substrate is 10 mu m, roughness of about 3 mu m will occur on the surface of the single crystal silicon substrate due in part to the nonuniformity of the etching during dry etching. Thus, when the single crystal silicon substrate is completely removed by etching, the silicon oxide layer may be overetched by 0.5 [mu] m in some places. Since this overetching is a probabilistic phenomenon, the silicon oxide layer may be etched 1 µm or more depending on the place. This overetching may cause the entire circuit to be defective.
과에칭을 피하기 위해, 다음 두 방법중 한 방법을 사용하는 것이 필요하다. 첫번째 방법은, 단결정 실리콘 기판을 드라이 에칭 공정전에 연마함으로써 10㎛ 이하로 박막화하는 것이다. 두번째 방법은, 실리콘 산화물층을 2㎛ 이상 두껍께 만드는 것이다. 그러나, 첫번째 방법에서는, 소자가 기계적으로 손상될 가능성이 높다. 두번째 방법에서는 실리콘 산화물층이 단결정 실리콘 기판에서 박리되기 쉽다는 문제점이 있다. 또한, 이 소자가 예컨대 액정 디스플레이의 주변 회로에 사용되면, 대향 전극과의 거리가 크게 될 경우 소자 동작에 문제가 발생한다.To avoid overetching, it is necessary to use one of the following two methods. The first method is to thin the single crystal silicon substrate to 10 mu m or less by grinding before the dry etching process. The second method, the silicon oxide layer 2㎛ It will make more than thick. However, in the first method, there is a high possibility that the device is mechanically damaged. In the second method, there is a problem that the silicon oxide layer is easily peeled off from the single crystal silicon substrate. In addition, when this element is used in a peripheral circuit of a liquid crystal display, for example, a problem occurs in the operation of the element when the distance from the counter electrode becomes large.
또한, 단결정 실리콘 기판이 박막화됨에 따라, 기판의 절연성이 높아지고, 그에 따라 대전(charge up)에 의한 정전 파괴의 가능성이 증가된다.In addition, as the single crystal silicon substrate is thinned, the insulation of the substrate is increased, thereby increasing the possibility of electrostatic breakdown due to charge up.
[발명의 개요][Overview of invention]
본 발명은 상기 문제점들의 관점에서 이루어진 것으로, 실질상 플라즈마를 사용하지 않고 단결정 실리콘 기판을 선택적으로 에칭함으로써 SOI형 집적 회로의 제조 수율을 개선시키는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and aims to improve the production yield of an SOI type integrated circuit by selectively etching a single crystal silicon substrate without substantially using plasma.
본 발명에 따라, 플루오르화 할로겐, 즉, ClF, ClF3, BrF, BrF3, IF 또는 IF3와 같은 화학식 XFn(X는 플루오르 이외의 할로겐, n은 정수)으로 표현되는 물질을 포함하는 분위기내에서 단결정 실리콘 기판을 에칭함으로써, 상기 문제점들이 해소된다.According to the invention, in an atmosphere comprising a fluorinated halogen, i.e. a substance represented by the formula XFn (X is a halogen other than fluorine, n is an integer) such as ClF, ClF 3 , BrF, BrF 3 , IF or IF 3 By etching the single crystal silicon substrate at, the above problems are solved.
즉, 본 발명에 따라, (1) 단결정 실리콘 기판상에 주로 실리콘 산화물로 이루어진 층을 형성하는 단계; (2) 상기 실리콘 산화물층상에 비단결정 실리콘 피막을 형성하는 단계; (3) 상기 단결정 실리콘 기판을 시드로 사용하여 상기 비단결정 실리콘 피막을 결정화하는 단계; (4) 단계 (3)에서 얻은 결정화된 실리콘막을 사용하여 반도체 집적 회로를 형성하는 단계; (5) 상기 반도체 집적 회로의 상면에 절연성 기판을 접착시키는 단계 및; (6) 상기 단결정 실리콘 기판을 플루오르화 할로겐을 포함하는 비플라즈마 분위기에 방치함으로써 상기 단결정 실리콘 기판을 에칭하는 단계를 포함하는 SOI형 반도체 집적 회로 제조방법이 제공된다.That is, according to the present invention, (1) forming a layer mainly composed of silicon oxide on a single crystal silicon substrate; (2) forming a non-single crystal silicon film on the silicon oxide layer; (3) crystallizing the non-single crystal silicon film using the single crystal silicon substrate as a seed; (4) forming a semiconductor integrated circuit using the crystallized silicon film obtained in step (3); (5) adhering an insulating substrate to an upper surface of the semiconductor integrated circuit; (6) An SOI type semiconductor integrated circuit manufacturing method comprising etching the single crystal silicon substrate by leaving the single crystal silicon substrate in a non-plasma atmosphere containing halogenated fluoride is provided.
상기 SOI형 반도체 집적 회로의 제조 방법은, 실리콘이 비플라즈마 상태에서 플루오르화 할로겐으로 에칭되는 것을 특징으로 한다.The method for manufacturing the SOI type semiconductor integrated circuit is characterized in that silicon is etched with halogenated fluoride in a non-plasma state.
비플라즈마 상태의 플루오르화 할로겐은, 실리콘을 에칭하고 실리콘 산화물은 전혀 에칭하지 않는다는 특징을 갖는다. 따라서, 단결정 실리콘 기판상의 실리콘 산화물층은 실리콘의 드라이 에칭시에 과에칭되지 않는다.Halogenated fluorinated halogens are characterized by etching silicon and not silicon oxide at all. Therefore, the silicon oxide layer on the single crystal silicon substrate is not overetched during dry etching of silicon.
또한, 실리콘 산화물층의 과에칭을 방지하기 위해 단결정 실리콘 기판을 연마할 필요가 없다. 즉, 플루오르화 할로겐에 의한 에칭만으로 단결정 실리콘 기판이 박막화되는 SOI형 반도체 집적 회로를 얻을 수 있다.In addition, there is no need to polish the single crystal silicon substrate to prevent overetching of the silicon oxide layer. That is, an SOI type semiconductor integrated circuit can be obtained in which a single crystal silicon substrate is thinned only by etching with a fluorinated halogen.
연마에 의한 단결정 실리콘 기판의 박막화 단계가 상기 과정중 단계 (4)와 단계 (5) 사이에 삽입될 수도 있다. 이 단계에서는 단결정 실리콘 기판을 10~100㎛의 두께로 박막화하면 충분한다. 종래의 과정과 대조적으로, 단결정 실리콘 기판을 10㎛ 이하로 박막화할 필요가 없다. 이것은 연마중 소자의 파괴를 방지한다.The thinning of the single crystal silicon substrate by polishing may be inserted between step (4) and step (5) during the process. In this step, it is sufficient to thin the single crystal silicon substrate to a thickness of 10 to 100 µm. In contrast to the conventional process, it is not necessary to thin the single crystal silicon substrate to 10 mu m or less. This prevents destruction of the element during polishing.
상기 과정중 단계 (3)에서, 실리콘 산화물층은 시드 개방부를 차지하지 않는다. 결정화된 실리콘막 중 시드 개방부를 차지하는 부분을 산화하는 공정이 단계 (3)와 단계 (4) 사이에 삽입될 수도 있다. 시드 개방부에 실리콘 산화물을 형성함으로써, 에칭은 실리콘 산화물층 보다 위쪽으로 진행하지 않으며 따라서 수율의 증가에 기여한다.In step (3) of the process, the silicon oxide layer does not occupy the seed opening. A process of oxidizing the portion occupying the seed opening of the crystallized silicon film may be inserted between step (3) and step (4). By forming silicon oxide in the seed openings, the etching does not proceed above the silicon oxide layer and thus contributes to an increase in yield.
본 발명에서, 절연성 기판은 무알칼리 보로실리케이트 유리(no-alkali borosilicate glass) (코닝 7059가 대표적임), 무알칼리 알루미나 실리케이트 유리(no-alkali alumina silicate glass) (코닝 1737이 대표적임)와 같은 다양한 재료 및 각종 플라스틱 재료로 이루어질 수 있다. 테플론형 재료는 플루오르화 할로겐으로 에칭될 수 없지만 그 이외의 어떤 재료로 에칭될 수도 있다. 따라서, 표면을 실리콘 산화물 또는 테플론으로 코팅하는 것이 양호하다.In the present invention, the insulating substrate may be a variety of materials such as no-alkali borosilicate glass (Corning 7059 is typical), no-alkali alumina silicate glass (Corning 1737 is typical). Material and various plastic materials. The teflon-type material cannot be etched with halogenated fluoride but may be etched with any other material. Therefore, it is preferable to coat the surface with silicon oxide or teflon.
플루오르화 할로겐에 의한 에칭은 광(자외광 또는 레이저광)이 조사되고 있는 표면에서 보다 빨리 진행한다는 특징을 갖는다. 따라서, 단결정 실리콘 기판의 측면에서부터 광을 인가함으로써 에칭 시간이 단축될 수 있다. 그 결과, 절연성 기판의 손상이 감소될 수 있다. 유사한 효과는 이온이나 전자빔을 인가함으로써 얻을 수 있다.Etching with halogenated fluoride is characterized by faster progress on the surface to which light (ultraviolet light or laser light) is being irradiated. Therefore, the etching time can be shortened by applying light from the side of the single crystal silicon substrate. As a result, damage to the insulating substrate can be reduced. Similar effects can be obtained by applying ions or electron beams.
[양호한 실시예의 설명]DESCRIPTION OF THE PREFERRED EMBODIMENTS
본 발명의 양호한 실시예는 제1(a)도 내지 제1(d)도, 제2(a)도 내지 제2(c)도 및 제3도를 참조로 설명될 것이다.Preferred embodiments of the present invention will be described with reference to FIGS. 1 (a) to 1 (d), 2 (a) to 2 (c) and 3rd.
본 실시예는 SOI형 반도체 집적 회로를 사용하여 생성되는, 액정 디스플레이용 능동 매트릭스에 관한 것이다. 제1(a)도 내지 제1(d)도는 단결정 실리콘 기판상에서 수행되는 웨이퍼 공정을 도시하는 단면도이다. 제2(a)도 내지 제2(c)도는 SOI 형성 공정을 도시하는 단면도이다. 제3도는 완성된 액정 디스플레이의 단면도이다.This embodiment relates to an active matrix for a liquid crystal display, which is produced using an SOI type semiconductor integrated circuit. 1 (a) to 1 (d) are cross-sectional views showing a wafer process performed on a single crystal silicon substrate. 2 (a) to 2 (c) are cross-sectional views showing the SOI forming process. 3 is a cross-sectional view of the completed liquid crystal display.
웨이퍼 공정에서는, 제1(a)도에 도시된 바와 같이, 우선, 0.3㎜ 두께의 단결정 기판 (11)상에 2000 내지 5000Å 두께의 실리콘 산화물막 (12)이 열 CVD법에 의해 증착된다. 실리콘 산화물막 (12)내에 시드 개방부(13)가 형성된다. 또한, 실리콘 산화물막 (12)상에 300 내지 1000Å 두께의 다결정 실리콘막(14)이 열 CVD 법에 의해 증착된다.In the wafer process, as shown in FIG. 1 (a), first, a silicon oxide film 12 having a thickness of 2000 to 5000 Pa is deposited on a 0.3 mm thick single crystal substrate 11 by thermal CVD. The seed opening 13 is formed in the silicon oxide film 12. In addition, a polycrystalline silicon film 14 having a thickness of 300 to 1000 상 에 is deposited on the silicon oxide film 12 by thermal CVD.
다음에, 스트립 히터(strip heater: 15)에 의해 다결정 실리콘막(14)이 가열되어 용융되고 그 스트립 히터(15)는 시드 개방부(13)에서부터 시작하여 이용된다. 따라서, 단결정 실리콘 기판(11)은 먼저 시드 개방부(13)에서 용융되고 거기에 용융 실리콘 영역(16)이 형성된다. 용융 실리콘 영역(16)은 스트립 히터(15)의 이동과 함께 이동한다. 용융 실리콘 영역(16)의 이동은, 실리콘이 용융된 후 응고됨으로써 결정화된다는 것을 의미한다. 결과적으로, 단결정 실리콘 기판(11)을 시드로 하여 실질상 단결정인 실리콘막(17)이 형성된다. “실질상 단결정”이란 것은 적층 결함의 존재에도 불구하고 10㎛ 이상의 직경 범위에서 거시적으로 볼때 결정을 단결정으로 간주할 수 있다는 것을 의미한다(제1(b)도).Next, the polycrystalline silicon film 14 is heated and melted by a strip heater 15 and the strip heater 15 is used starting from the seed opening 13. Thus, the single crystal silicon substrate 11 is first melted in the seed opening 13 and a molten silicon region 16 is formed therein. The molten silicon region 16 moves with the movement of the strip heater 15. Movement of the molten silicon region 16 means that the silicon is crystallized by melting and solidifying. As a result, the silicon film 17 which is substantially single crystal is formed using the single crystal silicon substrate 11 as a seed. "Substantially single crystal" means that the crystal can be regarded as a single crystal when viewed macroscopically in the diameter range of 10 mu m or more despite the presence of lamination defects (Fig. 1 (b)).
공지된 LOCOS법에 의해 실리콘막(17)을 선택적으로 열산화함으로써 소자분리용 절연부(18 및 19)가 형성된다. 이 선택적 열산화는 시드 개방부(13)에서 실리콘이 완전히 산화되도록 수행된다. 따라서, 단결정 실리콘막(17)과 단결정 실리콘 기판(11)은 실리콘 산화물부(19)에 의해 서로 분리된다. 그후, 열산화에 의해 게이트 절연막(21)이 형성된다. 이상의 공정에 의해, 다른 부분과 분리된 실리콘 영역(20)이 형성된다 (제1(c)도).By selectively thermally oxidizing the silicon film 17 by a known LOCOS method, the isolation portions 18 and 19 for element isolation are formed. This selective thermal oxidation is performed such that the silicon is completely oxidized in the seed opening 13. Thus, the single crystal silicon film 17 and the single crystal silicon substrate 11 are separated from each other by the silicon oxide portion 19. Thereafter, the gate insulating film 21 is formed by thermal oxidation. By the above process, the silicon region 20 separated from another part is formed (FIG. 1 (c)).
그후, 공지된 반도체 집적 회로 제조 기술에 의해 반도체 집적 회로가 형성된다. 이 실시예에서는 액정 디스플레이용 능동 매트릭스 회로가 형성된다.Thereafter, a semiconductor integrated circuit is formed by a known semiconductor integrated circuit manufacturing technique. In this embodiment, an active matrix circuit for a liquid crystal display is formed.
우선, 게이트 절연막(21)상에 다결정 실리콘막이 증착되고, 그후 게이트 전극/배선(22 내지 24)으로 패턴화된다. 게이트 전극/배선(22 내지 24)을 마스크로 사용하여 실리콘 영역(20)에 이온을 주입함으로서 소스(25) 및 드레인(26)을 형성하고, 열 어닐링에 의해 그것을 재결정화한다. 다음에, 층간 절연막(27)이 증착된다. 여기에 접촉홀(contact hole)이 형성된 후, 소스 전극/배선(28) 및 보유 캐패시터 전극/배선(29)이 형성된다. 마지막으로, 실리콘 질화물의 패시베이션막(passivation film)이 형성된다. 이로써 능동 매트릭스 회로를 얻는다. 이 단계에서, 드레인(26)과 보유 캐패시터 전극/배선(29) 사이에 위치하는 영역(30)내에, 층간 절연막(27)과 게이트 절연막(21)을 유전막으로 갖는 캐패시터가 형성된다(제1(d)도).First, a polycrystalline silicon film is deposited on the gate insulating film 21, and then patterned with the gate electrodes / wiring 22 to 24. The source 25 and the drain 26 are formed by implanting ions into the silicon region 20 using the gate electrodes / wiring 22 to 24 as a mask, and recrystallizing it by thermal annealing. Next, an interlayer insulating film 27 is deposited. After the contact holes are formed therein, the source electrode / wiring 28 and the retention capacitor electrode / wiring 29 are formed. Finally, a passivation film of silicon nitride is formed. This results in an active matrix circuit. In this step, a capacitor having an interlayer insulating film 27 and a gate insulating film 21 as a dielectric film is formed in a region 30 located between the drain 26 and the holding capacitor electrode / wiring 29 (first ( d) degrees).
이로써, 웨이퍼 공정이 완료된다. 본 발명의 웨이퍼 공정의 응용은 제1(a)도 내지 제1(d)도에 도시된 단순 구조에 한정되지 않고 제1(a)도 내지 제1(d)도의 회로와 다른 구조를 갖는 다양한 회로를 포함할 수 있다. 예컨대, 능동 매트릭스 회로뿐만 아니라, 그 능동 매트릭스 회로용 주변 구동 회로 및 고도의 정보 처리 회로가 형성될 수도 있다. 고도의 정보 처리 회로가 형성될 경우 그 디스플레이의 부가가치를 높일 수 있다.This completes the wafer process. The application of the wafer process of the present invention is not limited to the simple structure shown in FIGS. 1 (a) to 1 (d), but has various structures different from those of the circuits of FIGS. 1 (a) to 1 (d). It may include a circuit. For example, not only an active matrix circuit, but also a peripheral drive circuit for the active matrix circuit and a highly information processing circuit may be formed. If a highly information processing circuit is formed, the added value of the display can be increased.
다음 단계에서, 접착/밀폐제(33)로 에폭시 수지를 사용함으로써 소자의 상면에 유리 기판(코닝 7059)(32)이 접착된다(제2(a)도).In the next step, the glass substrate (Corning 7059) 32 is adhered to the upper surface of the device by using an epoxy resin as the adhesive / sealing agent 33 (Fig. 2 (a)).
다음에, ClF3로 에칭이 수행된다. 우선, 기판(11)을 세워서 석영관에 설치한다. 석영관은 1 내지 10 토르(Torr)로 배기되고 질소와 ClF3의 혼합 가스가 유입된다. 이 단계에서 에칭이 시작된다. 질소와 ClF3각각의 유량은 500sccm으로 설정된다. 이 상태를 50 시간 유지시킴으로써, 단결정 실리콘 기판(11)은 완전히 에칭된다. 에칭의 중간 상태(에칭이 약 0.2㎜ 정도 진행된 상태)에서 단결정 실리콘 기판(11)의 에칭된 표면 (34)은, 보통의 드라이 에칭에 의해 야기되는 것과 동일한 최대 20㎛의 큰 요철을 갖는다는 것이 관찰되었다(제2(b)도).Next, etching is performed with ClF 3 . First, the board | substrate 11 is stood up and it installs in a quartz tube. The quartz tube is evacuated to 1 to 10 Torr and a mixed gas of nitrogen and ClF 3 is introduced. Etching begins at this stage. The flow rate of nitrogen and ClF 3 was set to 500 sccm. By maintaining this state for 50 hours, the single crystal silicon substrate 11 is completely etched. In the intermediate state of etching (etching progressed by about 0.2 mm), the etched surface 34 of the single crystal silicon substrate 11 has a large unevenness of up to 20 μm, which is the same as that caused by normal dry etching. Was observed (figure 2 (b)).
그러나, 에칭은 전부 실리콘 산화물층(12)의 표면에서 정지되므로, 에칭이 완료될때 매우 평탄한 표면(35)을 얻는다. 본 에칭 단계는 50시간의 소요되나, 동시에 다량의 기판이 처리될 수 있으므로, 양산성의 저하는 초래되지 않는다. 이와 같이하여 능동 매트릭스측 기판을 생성한다. 트랜지스터를 보호하기 위해, 예컨대 실리콘 질화물의 패시베이션막이 실리콘 산화물층(12)상에 추가로 형성될 수도 있다 (제2(c)도).However, since the etching is all stopped at the surface of the silicon oxide layer 12, a very flat surface 35 is obtained when the etching is completed. This etching step takes 50 hours, but at the same time a large amount of substrates can be processed, so that no deterioration in productivity is caused. In this way, an active matrix side substrate is produced. In order to protect the transistor, for example, a passivation film of silicon nitride may be further formed on the silicon oxide layer 12 (Fig. 2 (c)).
그후, 1000Å 두께의 ITO(indium tin oxide: 인듐 주석 산화물) 막(37)이 유리 기판(코닝 7059)상에 형성되어 대향 기판으로 동작한다. 유리 기판(32 및 36)은 러빙 처리된 후 서로에 대향된다. 유리 기판(32 및 36) 사이에는 액정(38)이 삽입되어 액정 디스플레이를 완성한다.Thereafter, an ITO (indium tin oxide) film 37 of 1000 占 퐉 thickness is formed on a glass substrate (Corning 7059) to operate as an opposing substrate. The glass substrates 32 and 36 face each other after the rubbing treatment. A liquid crystal 38 is inserted between the glass substrates 32 and 36 to complete the liquid crystal display.
이 실시예에서 트랜지스터의 드레인(26) 자체가 능동 매트릭스측 기판의 픽셀 전극으로 사용된다. 이것은 매우 얇은 단결정 실리콘막은 광학적으로 투명하다는 사실을 이용한다(제3도).In this embodiment, the drain 26 of the transistor itself is used as the pixel electrode of the active matrix side substrate. This takes advantage of the fact that very thin single crystal silicon films are optically transparent (FIG. 3).
이 실시예에서, 능동 매트릭스측의 픽셀 전극(즉, 드레인(26))과 액정간의 거리는 실리콘 산화물층(12)의 두께 2000 내지 5000Å과 같거나 그 두께에 실리콘 질화물의 패시베이션막의 두께를 더한 것과 같다. 그 거리는 액정의 구동시에 어떤 문제도 발생시키기 않는다.In this embodiment, the distance between the pixel electrode on the active matrix side (i.e., the drain 26) and the liquid crystal is equal to the thickness of the silicon oxide layer 12 of 2000 to 5000 microns or the thickness of the passivation film of silicon nitride. . The distance does not cause any problem when driving the liquid crystal.
본 발명은 SOI형 반도체 집적 회로가 고수율로 제조될 수 있도록 한다. 특히, 본 발명은 단결정 실리콘 기판의 에칭에 플라즈마를 사용하지 않으므로 회로의 제조 수율뿐만 아니라 신뢰성을 증가시킬 수 있다. 상기 실시예에서는 반도체 집적 회로의 예로서 능동 매트릭스 회로가 사용되었지만, 메모리 회로, CPU 등도 본 발명에 따라 제작가능하다. 따라서, 본 발명은 산업적인 측면에서 매우 유용하다.The present invention allows an SOI type semiconductor integrated circuit to be manufactured in high yield. In particular, since the present invention does not use plasma for etching single crystal silicon substrates, it is possible to increase the manufacturing yield as well as the reliability of the circuit. In the above embodiment, an active matrix circuit is used as an example of a semiconductor integrated circuit, but memory circuits, CPUs, and the like can also be manufactured in accordance with the present invention. Therefore, the present invention is very useful from an industrial point of view.
Claims (20)
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| JP94-315635 | 1994-11-25 | ||
| JP31563594A JP3512496B2 (en) | 1994-11-25 | 1994-11-25 | Manufacturing method of SOI type semiconductor integrated circuit |
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| JP2900229B2 (en) * | 1994-12-27 | 1999-06-02 | 株式会社半導体エネルギー研究所 | Semiconductor device, manufacturing method thereof, and electro-optical device |
| JP3364081B2 (en) | 1995-02-16 | 2003-01-08 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| US5757456A (en) * | 1995-03-10 | 1998-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Display device and method of fabricating involving peeling circuits from one substrate and mounting on other |
| US5834327A (en) | 1995-03-18 | 1998-11-10 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing display device |
| US6979632B1 (en) * | 1995-07-13 | 2005-12-27 | Semiconductor Energy Laboratory Co., Ltd. | Fabrication method for thin-film semiconductor |
| KR100228719B1 (en) * | 1996-05-27 | 1999-11-01 | 윤덕용 | Manufacturing method for soi type semiconductor material that use electrochemical etching method and active drive liquid crystal display device |
| JP3871764B2 (en) * | 1997-03-26 | 2007-01-24 | 株式会社半導体エネルギー研究所 | Reflective display device |
| US5976959A (en) * | 1997-05-01 | 1999-11-02 | Industrial Technology Research Institute | Method for forming large area or selective area SOI |
| DE19752404C1 (en) * | 1997-11-26 | 1999-08-19 | Siemens Ag | Very thin semiconductor chip manufacturing method |
| US6709985B1 (en) * | 1999-08-26 | 2004-03-23 | Advanced Micro Devices, Inc. | Arrangement and method for providing an imaging path using a silicon-crystal damaging laser |
| KR100327341B1 (en) * | 1999-10-27 | 2002-03-06 | 윤종용 | Method for manufacturing semiconductor device using polysilicon hard mask and apparatus for the same |
| JP2002366051A (en) * | 2001-06-08 | 2002-12-20 | Sanyo Electric Co Ltd | Integrated circuit chip and display device using the same |
| US7102367B2 (en) * | 2002-07-23 | 2006-09-05 | Fujitsu Limited | Probe card and testing method of semiconductor chip, capacitor and manufacturing method thereof |
| US6753239B1 (en) * | 2003-04-04 | 2004-06-22 | Xilinx, Inc. | Bond and back side etchback transistor fabrication process |
| JP4801337B2 (en) * | 2004-09-21 | 2011-10-26 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| US7456104B2 (en) * | 2005-05-31 | 2008-11-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US7253083B2 (en) * | 2005-06-17 | 2007-08-07 | Northrop Grumman Corporation | Method of thinning a semiconductor structure |
| JP4890491B2 (en) * | 2008-03-31 | 2012-03-07 | 株式会社半導体エネルギー研究所 | Method for manufacturing electronic device |
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| US4310380A (en) * | 1980-04-07 | 1982-01-12 | Bell Telephone Laboratories, Incorporated | Plasma etching of silicon |
| US4498953A (en) * | 1983-07-27 | 1985-02-12 | At&T Bell Laboratories | Etching techniques |
| JPS63308386A (en) * | 1987-01-30 | 1988-12-15 | Sony Corp | Semiconductor device and manufacture thereof |
| US5089441A (en) * | 1990-04-16 | 1992-02-18 | Texas Instruments Incorporated | Low-temperature in-situ dry cleaning process for semiconductor wafers |
| JPH0817166B2 (en) * | 1991-04-27 | 1996-02-21 | 信越半導体株式会社 | Ultra thin film SOI substrate manufacturing method and manufacturing apparatus |
| US5326406A (en) * | 1991-07-31 | 1994-07-05 | Kawasaki Steel Corporation | Method of cleaning semiconductor substrate and apparatus for carrying out the same |
| JPH05243218A (en) * | 1992-02-28 | 1993-09-21 | Nec Corp | Manufacture of semiconductor device |
| US5350480A (en) * | 1993-07-23 | 1994-09-27 | Aspect International, Inc. | Surface cleaning and conditioning using hot neutral gas beam array |
| US5403434A (en) * | 1994-01-06 | 1995-04-04 | Texas Instruments Incorporated | Low-temperature in-situ dry cleaning process for semiconductor wafer |
| US5534107A (en) * | 1994-06-14 | 1996-07-09 | Fsi International | UV-enhanced dry stripping of silicon nitride films |
| JPH0845935A (en) * | 1994-07-26 | 1996-02-16 | Sony Corp | Forming method of multilayer interconnection |
| JP3454951B2 (en) * | 1994-12-12 | 2003-10-06 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
-
1994
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| JP3512496B2 (en) | 2004-03-29 |
| US5786242A (en) | 1998-07-28 |
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