JP5538673B2 - Manufacturing method of semiconductor substrate using SOQ substrate - Google Patents

Manufacturing method of semiconductor substrate using SOQ substrate Download PDF

Info

Publication number
JP5538673B2
JP5538673B2 JP2007286101A JP2007286101A JP5538673B2 JP 5538673 B2 JP5538673 B2 JP 5538673B2 JP 2007286101 A JP2007286101 A JP 2007286101A JP 2007286101 A JP2007286101 A JP 2007286101A JP 5538673 B2 JP5538673 B2 JP 5538673B2
Authority
JP
Japan
Prior art keywords
substrate
insulating film
manufacturing
semiconductor element
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007286101A
Other languages
Japanese (ja)
Other versions
JP2009117460A (en
Inventor
関口  金孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Finetech Miyota Co Ltd
Original Assignee
Citizen Finetech Miyota Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Finetech Miyota Co Ltd filed Critical Citizen Finetech Miyota Co Ltd
Priority to JP2007286101A priority Critical patent/JP5538673B2/en
Publication of JP2009117460A publication Critical patent/JP2009117460A/en
Application granted granted Critical
Publication of JP5538673B2 publication Critical patent/JP5538673B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Element Separation (AREA)

Description

本発明は、SOQ基板を用いた半導体基板の製造方法に関するものである。
The present invention relates to the production how the semiconductor substrate using the SOQ substrate.

絶縁体層上に設けられたシリコン層を半導体装置の形成に利用するSOI(Silicon On Insulator)技術は、α線耐性、ラッチアップ特性、あるいはショートチャネルの抑制効果など、通常の単結晶シリコン基板では達成し得ない優れた特性を示すため、半導体装置の高集積化を目的として開発が進められている。   SOI (Silicon On Insulator) technology, which uses a silicon layer provided on an insulator layer for the formation of a semiconductor device, has an α-ray resistance, a latch-up characteristic, or a short channel suppression effect in a normal single crystal silicon substrate. In order to exhibit excellent characteristics that cannot be achieved, development has been promoted for the purpose of high integration of semiconductor devices.

最近では、100nm以下の厚さにまで薄膜化されたSOI層にデバイスを形成したものによって、優れたショートチャネル抑制効果が見いだされている。また、このようにして形成されたSOIデバイスは、放射線耐性に優れていることによる高信頼性を備えるとともに、寄生容量の低減による素子の高速化や低消費電力化を図れること、あるいは完全空乏型電界効果トランジスタを作製できることによるプロセスルールの微細化を図れることなどの優れた点を備えている。   Recently, an excellent short channel suppression effect has been found by forming a device on an SOI layer thinned to a thickness of 100 nm or less. In addition, the SOI device formed in this way has high reliability due to its excellent radiation resistance, and can increase the speed and power consumption of the element by reducing parasitic capacitance, or can be completely depleted. It has excellent points such as miniaturization of process rules due to the ability to produce field effect transistors.

このようなSOI構造を形成する方法としては、単結晶シリコン基板の貼り合わせによるSOI基板の製造方法がある。一般に貼り合わせ法と呼ばれるこの方法は、単結晶シリコン基板と支持基板とを酸化膜を介して重ね合わせ、基板表面のOH基を利用して室温程度で貼り合わせた後、単結晶シリコン基板を研削や研磨、またはエッチングによって薄膜化し、続いて700℃〜1200℃程度の熱処理によってシロキサン結合(Si−O−Si)して、貼り合わせ強度を上げて、単結晶シリコン層を支持基板上に形成するものである。この手法では、単結晶シリコン基板を直接、薄膜化するので、シリコン薄膜の結晶性に優れ、高性能のデバイスを作成できる。また、この貼り合わせ法を応用したものとして、単結晶シリコン基板に水素イオンを注入し、これを支持基板と貼り合わせた後、400℃〜600℃程度の熱処理によって薄膜シリコン層を単結晶シリコン基板の水素注入領域から分離し、次に1100℃程度までの熱処理で貼り合わせ強度を上げる手法や、表面を多孔質化したシリコン基板上に単結晶シリコン層をエピタキシャル成長させ、これを支持基板と貼り合わせた後にシリコン基板を除去し、多孔質シリコン層をエッチングすることにより支持基板上にエピタキシャル単結晶シリコン薄膜を形成する手法などが知られている。   As a method for forming such an SOI structure, there is a method for manufacturing an SOI substrate by bonding single crystal silicon substrates. This method, commonly referred to as a bonding method, is a method in which a single crystal silicon substrate and a support substrate are overlapped via an oxide film, bonded together at room temperature using OH groups on the substrate surface, and then the single crystal silicon substrate is ground. The film is thinned by polishing, polishing, or etching, and then siloxane bond (Si—O—Si) is formed by heat treatment at about 700 ° C. to 1200 ° C. to increase the bonding strength, and a single crystal silicon layer is formed on the supporting substrate. Is. In this method, since the single crystal silicon substrate is directly thinned, a silicon thin film having excellent crystallinity and a high performance device can be produced. Further, as an application of this bonding method, hydrogen ions are implanted into a single crystal silicon substrate, bonded to a support substrate, and then a thin film silicon layer is formed by heat treatment at about 400 ° C. to 600 ° C. A method of increasing the bonding strength by heat treatment up to about 1100 ° C. after separating from the hydrogen injection region of this layer, or epitaxially growing a single crystal silicon layer on a porous silicon substrate and bonding this to a support substrate After that, a method of forming an epitaxial single crystal silicon thin film on a supporting substrate by removing the silicon substrate and etching the porous silicon layer is known.

貼り合わせ法によるSOI基板は通常のバルク半導体基板(半導体集積回路)と同様に、様々なデバイスの作製に用いることができるが、従来のバルク基板と異なる点として、支持基板に様々な材料を使用することが可能である点を挙げることができる。すなわち、支持基板としては、通常のシリコン基板はもちろんのこと、透光性を備えた石英基板、あるいはガラス基板などを用いることができる。従って、透光性基板上に単結晶シリコン薄膜を形成することによって、光透過性を必要とするデバイス、例えば、透過型の液晶装置などの電気光学装置においても、アクティブマトリクス基板上に、結晶性に優れた単結晶シリコン層を用いて高性能なトランジスタ素子を形成することができる。すなわち、画素電極を駆動する画素スイッチング用MIS形トランジスタや、画像表示領域の周辺領域で駆動回路を構成する駆動回路用MIS形トランジスタを単結晶シリコン層であるSOI層に形成することにより表示の微細化、高速化を図ることができる。(特許文献1参照)   The SOI substrate by the bonding method can be used for manufacturing various devices like a normal bulk semiconductor substrate (semiconductor integrated circuit). However, as a difference from the conventional bulk substrate, various materials are used for the support substrate. The point which can be done can be mentioned. That is, as the supporting substrate, not only a normal silicon substrate but also a translucent quartz substrate or a glass substrate can be used. Therefore, by forming a single-crystal silicon thin film on a light-transmitting substrate, even in a device that requires light transmission, for example, an electro-optical device such as a transmission-type liquid crystal device, A high-performance transistor element can be formed using a single crystal silicon layer that is excellent in the above. That is, by forming a pixel switching MIS type transistor for driving a pixel electrode or a driving circuit MIS type transistor constituting a driving circuit in a peripheral region of the image display region in an SOI layer which is a single crystal silicon layer, fine display can be achieved. And speeding up can be achieved. (See Patent Document 1)

図3は従来技術によるSOI基板を用いたLSIプロセスの絶縁膜形成工程を示す工程断面図であり、透過型液晶表示装置に用いる例である。(A)はSOI基板、(B)はシリコン基板を加工した図、(C)は絶縁膜を形成した図である。   FIG. 3 is a process sectional view showing an insulating film forming process of an LSI process using an SOI substrate according to the prior art, and is an example used for a transmissive liquid crystal display device. (A) is an SOI substrate, (B) is a diagram obtained by processing a silicon substrate, and (C) is a diagram in which an insulating film is formed.

(A)においてSOI基板は、絶縁基板にシリコン基板1を使用し、表面に酸化シリコン膜2を介して単結晶シリコン基板(以下、シリコン膜という)3が貼り合わされたSOI基板である。
(B)は、液晶画素電極を駆動するのに必要な複数の半導体素子部4以外を除去した図である。
(C)は、その上に絶縁膜(例えば窒化シリコン膜)5を形成した図である。窒化シリコン膜5はLSI製造プロセスの中で幾度も形成され、除去される。熱膨張係数は、シリコン膜3が3.9×10−6/℃、窒化シリコン膜5が3.5×10−6/℃であり、殆んど同じであり、熱膨張係数に起因する熱応力の発生は少なかった。
In (A), the SOI substrate is an SOI substrate in which a silicon substrate 1 is used as an insulating substrate and a single crystal silicon substrate (hereinafter referred to as a silicon film) 3 is bonded to the surface via a silicon oxide film 2.
FIG. 6B is a diagram in which a portion other than the plurality of semiconductor element portions 4 necessary for driving the liquid crystal pixel electrode is removed.
(C) is a view in which an insulating film (for example, a silicon nitride film) 5 is formed thereon. The silicon nitride film 5 is formed and removed many times during the LSI manufacturing process. The thermal expansion coefficients of the silicon film 3 are 3.9 × 10 −6 / ° C. and the silicon nitride film 5 is 3.5 × 10 −6 / ° C., which are almost the same, and the heat caused by the thermal expansion coefficient There was little generation of stress.

特開2003−142664号公報JP 2003-142664 A

ここで、透過型液晶表示装置のコントラストを上げるために、透過型液晶表示装置に使用するSOI基板として光透過率の高い石英を使用したSOQ基板を用いた場合、支持基板である石英基板と半導体プロセスで形成される絶縁膜において、例えば900℃〜1100℃程度で形成する窒化シリコン膜の熱膨張係数(3.5×10−6/℃)と石英基板の熱膨張係数(0.5×10−6/℃)間では熱膨張係数が大きく違う。900℃〜1100℃から室温(25℃)まで温度を下げると窒化シリコン膜には強い引張り応力が発生し、窒化シリコン膜の剥離あるいは窒化シリコン膜に囲繞された半導体素子部に悪影響を与える。 Here, in order to increase the contrast of the transmissive liquid crystal display device, when an SOQ substrate using quartz with high light transmittance is used as the SOI substrate used in the transmissive liquid crystal display device, the quartz substrate which is the supporting substrate and the semiconductor In the insulating film formed by the process, for example, the thermal expansion coefficient (3.5 × 10 −6 / ° C.) of the silicon nitride film formed at about 900 ° C. to 1100 ° C. and the thermal expansion coefficient (0.5 × 10 10) of the quartz substrate. The coefficient of thermal expansion differs greatly between -6 / ℃. When the temperature is lowered from 900 ° C. to 1100 ° C. to room temperature (25 ° C.), a strong tensile stress is generated in the silicon nitride film, which adversely affects the peeling of the silicon nitride film or the semiconductor element portion surrounded by the silicon nitride film.

かかる問題点に鑑みて、本発明の課題は、支持基板(石英)とシリコン膜上に形成される窒化シリコン膜との熱膨張係数の差により発生する熱応力を緩和する半導体基板を形成可能な半導体基板の製造方法を提供することにある。
In view of such a problem, an object of the present invention is to form a semiconductor substrate that relieves thermal stress generated by a difference in thermal expansion coefficient between a support substrate (quartz) and a silicon nitride film formed on a silicon film. It is to provide a manufacturing how the semiconductor substrate.

SOQ基板上に形成された半導体素子部と、半導体素子部周辺に石英と熱膨張係数の異なる絶縁膜を形成するSOQ基板を用いた半導体基板の製造方法において、前記絶縁膜を形成する前に、前記半導体素子部周辺に前記絶縁膜の分離部材を設け、前記絶縁膜を形成した後に、前記分離部材の上面の前記絶縁膜を除去する半導体基板の製造方法とする。
In a semiconductor substrate manufacturing method using a semiconductor element portion formed on an SOQ substrate and an SOQ substrate that forms an insulating film having a different thermal expansion coefficient from quartz around the semiconductor element portion, before forming the insulating film, wherein the separating member of the insulating film in the peripheral semiconductor element portion is provided, it said after forming the insulating film, a method of manufacturing a semiconductor substrate you remove the insulating film on the upper surface of the separating member.

SOQ基板上に形成された半導体素子部と、半導体素子部周辺に石英と熱膨張係数の異なる絶縁膜を形成するSOQ基板を用いた透過型液晶表示装置用半導体基板の製造方法において、前記絶縁膜を形成する前に、画素周辺部及びまたは前記半導体素子部周辺に前記絶縁膜の分離部材を設け、前記絶縁膜を形成した後に、前記分離部材の上面の前記絶縁膜を除去する半導体基板の製造方法とする。 In the method of manufacturing a semiconductor substrate for a transmissive liquid crystal display device using a semiconductor element portion formed on an SOQ substrate and an SOQ substrate in which an insulating film having a thermal expansion coefficient different from that of quartz is formed around the semiconductor element portion, the insulating film before forming a separation member of the insulating film provided in the peripheral pixel portion periphery and or the semiconductor element, the after forming the insulating film, the semiconductor substrate you remove the insulating film on the upper surface of the separating member Let it be a manufacturing method.

前記絶縁膜が窒化シリコン膜であり、前記分離部材が酸化シリコン膜である前記の半導体基板の製造方法とする。
Wherein the insulating film is a silicon nitride Makudea is, the separating member is a method for manufacturing a semiconductor substrate Ru silicon oxide Makudea.

前記絶縁膜形成後、前記分離部材を除去する前記の半導体基板の製造方法とする。   After the formation of the insulating film, the semiconductor substrate is manufactured by removing the separation member.

本発明によると、SOQ基板を用いた半導体基板において、石英基板と絶縁膜の熱膨張係数差による応力を緩和できるので、半導体素子のクラック防止や応力による劣化を防止できる。光透過率の高い石英基板を使用し、単結晶シリコン基板を使用できるので、コントラストの高い高精細な液晶表示装置を提供することができる。   According to the present invention, in a semiconductor substrate using an SOQ substrate, stress due to a difference in thermal expansion coefficient between the quartz substrate and the insulating film can be relieved, so that cracking of the semiconductor element and deterioration due to stress can be prevented. Since a quartz substrate with high light transmittance is used and a single crystal silicon substrate can be used, a high-definition liquid crystal display device with high contrast can be provided.

SOQ基板上に形成された半導体素子部と、半導体素子部周辺に石英と熱膨張係数の異なる絶縁膜を形成するSOQ基板を用いた半導体基板の製造方法において、前記半導体素子部周辺に前記絶縁膜の分離部材を設ける半導体基板の製造方法とし、前記絶縁膜は窒化シリコン膜とし、窒化シリコン膜形成後、前記分離部材は除去する半導体基板の製造方法とする。   In a method for manufacturing a semiconductor substrate using a semiconductor element portion formed on an SOQ substrate and an SOQ substrate having an insulating film having a thermal expansion coefficient different from that of quartz around the semiconductor element portion, the insulating film is formed around the semiconductor element portion. A method of manufacturing a semiconductor substrate in which the isolation member is provided, wherein the insulating film is a silicon nitride film, and after the silicon nitride film is formed, the isolation member is removed.

図1は本発明によるSOQ基板を用いたLSIプロセスの絶縁膜形成工程を示す工程断面図であり、透過型液晶表示装置に用いる例である。(A)はSOQ基板、(B)はシリコン膜を加工した図、(C)は絶縁膜Iを形成した図、(D)は絶縁膜をパターニングした図、(E)は絶縁膜IIを形成した図、(F)は半導体素子部と分離部材部の上面の窒化シリコン膜を除去した図(G)は絶縁膜Iを除去した図である。   FIG. 1 is a process sectional view showing an insulating film forming process of an LSI process using an SOQ substrate according to the present invention, and is an example used for a transmissive liquid crystal display device. (A) is an SOQ substrate, (B) is a processed silicon film, (C) is an insulating film I, (D) is an insulating film, and (E) is an insulating film II. FIG. 5F is a view in which the silicon nitride film on the upper surface of the semiconductor element portion and the separation member portion is removed. FIG. 5G is a view in which the insulating film I is removed.

(A)においてSOQ基板は、絶縁基板に石英基板11を使用し、表面に酸化シリコン膜12を介してシリコン膜13が貼り合わされている。
(B)は、液晶画素電極を駆動するのに必要な複数の半導体素子部14以外のシリコン膜13を除去した図である。
(C)は、その上に石英基板11と熱膨張係数の近い絶縁膜(例えば酸化シリコン膜)15を形成した図である。熱膨張係数は、石英基板0.5×10−6/℃、酸化シリコンが0.5×10−6/℃であり、同じである。
In (A), the SOQ substrate uses a quartz substrate 11 as an insulating substrate, and a silicon film 13 is bonded to the surface via a silicon oxide film 12.
FIG. 5B is a diagram in which the silicon film 13 other than the plurality of semiconductor element portions 14 necessary for driving the liquid crystal pixel electrode is removed.
(C) is a view in which an insulating film (for example, a silicon oxide film) 15 having a thermal expansion coefficient close to that of the quartz substrate 11 is formed thereon. The thermal expansion coefficients are the same, ie, quartz substrate 0.5 × 10 −6 / ° C. and silicon oxide 0.5 × 10 −6 / ° C.

(D)は、酸化シリコン膜15をパターニングし、次に形成する窒化シリコン膜を分離するための分離部材部16を半導体素子部14の周囲に形成し、その余の部分を除去した図である。(C)の絶縁膜15形成時にマスキングした蒸着により直接(D)の状態の分離部材部16を形成しても良い。   FIG. 4D is a diagram in which the silicon oxide film 15 is patterned, the separation member portion 16 for separating the silicon nitride film to be formed next is formed around the semiconductor element portion 14, and the remaining portion is removed. . The separation member portion 16 in the state (D) may be directly formed by vapor deposition masked when the insulating film 15 is formed in (C).

(E)は、窒化シリコン膜17を形成した図である。   (E) is a view in which a silicon nitride film 17 is formed.

(F)は半導体素子部14と分離部材部16の上面の窒化シリコン膜17を除去した図で、図2はその上面図である。図2においては液晶表示装置の4つの画素部を示している。窒化シリコン膜17は半導体素子部14の周囲に形成された分離部材16で分断されている。図示していないが、画素部境界に分離部材16を設けても良い。窒化シリコン膜17を分離部材16で分断しているので、石英基板11に直接形成される窒化シリコン膜17の面積が減少し応力が緩和される。また、半導体素子部14に影響を与える窒化シリコン膜17は分離部材16の内周と半導体素子部14の外周間の微小部分になるので、半導体素子14のクラック防止や応力による劣化を防止できる。
(G)は分離部材16を除去した例であり、より窒化シリコン膜の引張り応力が緩和できる。
FIG. 2F is a view in which the silicon nitride film 17 on the top surfaces of the semiconductor element portion 14 and the separation member portion 16 is removed, and FIG. 2 is a top view thereof. FIG. 2 shows four pixel portions of the liquid crystal display device. The silicon nitride film 17 is divided by a separating member 16 formed around the semiconductor element portion 14. Although not shown, a separating member 16 may be provided at the pixel portion boundary. Since the silicon nitride film 17 is divided by the separating member 16, the area of the silicon nitride film 17 directly formed on the quartz substrate 11 is reduced and the stress is relaxed. Further, since the silicon nitride film 17 that affects the semiconductor element portion 14 is a minute portion between the inner periphery of the separation member 16 and the outer periphery of the semiconductor element portion 14, the semiconductor element 14 can be prevented from cracking and deterioration due to stress.
(G) is an example in which the separation member 16 is removed, and the tensile stress of the silicon nitride film can be more relaxed.

本発明によるSOQ基板を用いたLSIプロセスの絶縁膜形成工程を示す工程断面図Process sectional drawing which shows the insulating film formation process of the LSI process using the SOQ substrate by this invention 半導体素子部と分離部材部の上面の窒化シリコン膜を除去した上面図Top view with the silicon nitride film removed from the top surface of the semiconductor element and isolation member 従来技術によるSOI基板を用いたLSIプロセスの絶縁膜形成工程を示す工程断面図Process sectional view showing the insulating film formation process of the LSI process using the SOI substrate according to the prior art

符号の説明Explanation of symbols

1 絶縁基板(シリコン基板)
2 シリコン酸化膜
3 単結晶シリコン基板(シリコン膜)
4 半導体素子部
5 絶縁膜(窒化シリコン膜)
11 石英基板
12 絶縁膜(酸化シリコン膜)
13 単結晶シリコン膜(基板)
14 半導体素子部
15 絶縁膜I(酸化シリコン膜)
16 分離部材部
17 絶縁膜II(窒化シリコン膜)
1 Insulating substrate (silicon substrate)
2 Silicon oxide film 3 Single crystal silicon substrate (silicon film)
4 Semiconductor element part 5 Insulating film (silicon nitride film)
11 Quartz substrate 12 Insulating film (silicon oxide film)
13 Single crystal silicon film (substrate)
14 Semiconductor element portion 15 Insulating film I (silicon oxide film)
16 Separating member 17 Insulating film II (silicon nitride film)

Claims (4)

SOQ基板上に形成された半導体素子部と、半導体素子部周辺に石英と熱膨張係数の異なる絶縁膜を形成するSOQ基板を用いた半導体基板の製造方法において、前記絶縁膜を形成する前に、前記半導体素子部周辺に前記絶縁膜の分離部材を設け、前記絶縁膜を形成した後に、前記分離部材の上面の前記絶縁膜を除去することを特徴とする半導体基板の製造方法。 In a semiconductor substrate manufacturing method using a semiconductor element portion formed on an SOQ substrate and an SOQ substrate that forms an insulating film having a different thermal expansion coefficient from quartz around the semiconductor element portion, before forming the insulating film, wherein the peripheral semiconductor element provided separating member of the insulating film, after forming the insulating film, a method of manufacturing a semiconductor substrate, it characterized that you remove the insulating film on the upper surface of the separating member. SOQ基板上に形成された半導体素子部と、半導体素子部周辺に石英と熱膨張係数の異なる絶縁膜を形成するSOQ基板を用いた透過型液晶表示装置用半導体基板の製造方法において、前記絶縁膜を形成する前に、画素周辺部及びまたは前記半導体素子部周辺に前記絶縁膜の分離部材を設け、前記絶縁膜を形成した後に、前記分離部材の上面の前記絶縁膜を除去することを特徴とする半導体基板の製造方法。 In the method of manufacturing a semiconductor substrate for a transmissive liquid crystal display device using a semiconductor element portion formed on an SOQ substrate and an SOQ substrate in which an insulating film having a thermal expansion coefficient different from that of quartz is formed around the semiconductor element portion, the insulating film before forming a separation member of the insulating film provided in the peripheral pixel portion periphery and or the semiconductor element, after formation of the insulating film, characterized that you remove the insulating film on the upper surface of the separating member A method for manufacturing a semiconductor substrate. 前記絶縁膜が窒化シリコン膜であり、前記分離部材が酸化シリコン膜であることを特徴とする請求項1または2記載の半導体基板の製造方法。   3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the insulating film is a silicon nitride film, and the separation member is a silicon oxide film. 前記絶縁膜形成後、前記分離部材を除去することを特徴とする請求項1、2または3記載の半導体基板の製造方法。
4. The method of manufacturing a semiconductor substrate according to claim 1, wherein the separating member is removed after the insulating film is formed.
JP2007286101A 2007-11-02 2007-11-02 Manufacturing method of semiconductor substrate using SOQ substrate Expired - Fee Related JP5538673B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007286101A JP5538673B2 (en) 2007-11-02 2007-11-02 Manufacturing method of semiconductor substrate using SOQ substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007286101A JP5538673B2 (en) 2007-11-02 2007-11-02 Manufacturing method of semiconductor substrate using SOQ substrate

Publications (2)

Publication Number Publication Date
JP2009117460A JP2009117460A (en) 2009-05-28
JP5538673B2 true JP5538673B2 (en) 2014-07-02

Family

ID=40784290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007286101A Expired - Fee Related JP5538673B2 (en) 2007-11-02 2007-11-02 Manufacturing method of semiconductor substrate using SOQ substrate

Country Status (1)

Country Link
JP (1) JP5538673B2 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2841381B2 (en) * 1988-09-19 1998-12-24 セイコーエプソン株式会社 Method for manufacturing thin film transistor
JPH1152426A (en) * 1997-08-07 1999-02-26 Toshiba Corp Liquid crystal display device and its production
JP4653374B2 (en) * 2001-08-23 2011-03-16 セイコーエプソン株式会社 Manufacturing method of electro-optical device
JP2003142665A (en) * 2001-08-23 2003-05-16 Seiko Epson Corp Method for manufacturing semiconductor substrate, semiconductor substrate, electrooptic device and electronic apparatus
JP4307195B2 (en) * 2003-09-17 2009-08-05 京セラ株式会社 Electrostatic chuck

Also Published As

Publication number Publication date
JP2009117460A (en) 2009-05-28

Similar Documents

Publication Publication Date Title
KR100643746B1 (en) Semiconductor substrate, semiconductor device, and manufacturing methods for them
US7691730B2 (en) Large area semiconductor on glass insulator
JPH01315159A (en) Dielectric-isolation semiconductor substrate and its manufacture
JP3176072B2 (en) Method of forming semiconductor substrate
US20070278494A1 (en) Single-crystal layer on a dielectric layer
US11127625B2 (en) Semiconductor structure and related method
JP2009081352A (en) Manufacturing method for semiconductor substrate, and semiconductor substrate
JP3253099B2 (en) Manufacturing method of semiconductor substrate
JP2004228206A (en) Substrate for element formation and its manufacturing method, and semiconductor device
JP2824818B2 (en) Active matrix liquid crystal display
JP2005082870A (en) Method for washing stacked substrate, and method for sticking substrate
JP5538673B2 (en) Manufacturing method of semiconductor substrate using SOQ substrate
WO2015074480A1 (en) Method for preparing semiconductor substrate with smooth edges
JP2763107B2 (en) Dielectric-isolated semiconductor substrate and method of manufacturing the same
JPH10293322A (en) Liquid crystal display and manufacture therefor
JPH0488657A (en) Semiconductor device and manufacture thereof
JP5231772B2 (en) Method for manufacturing transmissive liquid crystal display element substrate
JPH06214241A (en) Liquid crystal display device
JPH02219252A (en) Manufacture of semiconductor device
JP3154100B2 (en) Manufacturing method of liquid crystal image display device
JP3109121B2 (en) Semiconductor substrate manufacturing method
JP2001320033A (en) Semiconductor member and method for manufacturing the same and semiconductor device using the method
JPS62203364A (en) Manufacture of semiconductor device
JPS61144036A (en) Semiconductor device and manufacture thereof
US20080227273A1 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101027

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130422

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130617

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20131213

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140124

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140409

R150 Certificate of patent or registration of utility model

Ref document number: 5538673

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140430

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees