JPH06214241A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To obtain the liquid crystal display device which is uniform in liquid crystal cell gap, free from an increase in chip size, and superior in productivity by providing with a liquid crystal seal area on a specific circuit element. CONSTITUTION:The liquid crystal display device consists of a pixel area 1 where signal lines are arranged longitudinally, gate lines are arranged horizontally, and transistor(TR) switches for transferring signals to respective pixel electrodes are arrayed at their intersections in two dimensions, a horizontal scanning circuit 2, a vertical scanning circuit 3, a horizontal dummy circuit 4, a vertical dummy circuit 5, and a liquid crystal seal area 6. Patterns 2-5 having the same steps are arranged at four sides at the periphery of the pixel area 1 on a semiconductor substrate and the liquid crystal seal area 6 is provided thereupon, so the liquid crystal cell gap becomes uniform. Further, the liquid crystal seal area 6 is arranged on the peripheral scanning circuits 2 and 3, so the chip size is reducible. Further, the dummy circuits 4 and 5 can be formed in the same process as the peripheral operation circuits 2 and 3, so the productivity superior.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device. More specifically, it relates to a liquid crystal display device having a uniform liquid crystal cell gap.

[0002]

2. Description of the Related Art In general, a liquid crystal display device is provided with a liquid crystal layer between two opposing substrates each having an electrode on its inner surface, and the substrates are bonded together to drive a liquid crystal element around a pixel region. Peripheral circuits are provided.

Conventionally, when both substrates are bonded together, if a seal region 32 is provided on the peripheral circuit 31 as shown in FIG. 5, a liquid crystal gap distribution occurs, and if it exceeds ± 0.1 μ, color unevenness occurs. was there.

In order to avoid this, if a seal region 32 is provided outside the peripheral circuit 31 as shown in FIG. 6, the chip size becomes large, and particularly a liquid crystal display device such as a viewfinder which requires a very small cell size. Then it becomes a big problem.

There is also a method of providing a flattening film 34 made of an insulating layer as shown in FIG. 7, but an extra process of forming the flattening film 34 is required, and the insulating layer on the pixel electrode 35 is thick. Then, there is a problem that the applied voltage must be increased. Further, when amorphous silicon or polysilicon is used as the semiconductor substrate, the step difference in the peripheral circuit portion 31 is small and easy to flatten, but when single crystal silicon is used, the step difference is large. However, there is a problem in that the film thickness of the flattening film 34 must be increased.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art and to provide a liquid crystal display device having a uniform liquid crystal cell gap, no increase in chip size, and excellent productivity. And

[0007]

That is, the present invention is characterized in that a circuit element having the same step is provided around at least two opposite sides of a pixel area, and a liquid crystal seal area is provided on the circuit element. It is a display device.

[0008]

The present invention will be described in detail below with reference to examples.

(Embodiment 1) FIG. 1 is a top view of a liquid crystal display device of this embodiment, and FIG. 2 is a sectional view taken along the line AA 'of FIG. Figure 1
In FIG. 2, 1 is a pixel region in which signal lines are arranged in the vertical direction and gate lines are arranged in the horizontal direction, and transistor switches for transferring signals to respective pixel electrodes are two-dimensionally arranged at the intersections thereof.
Is a horizontal scanning circuit, 3 is a vertical scanning circuit having the same step as the horizontal scanning circuit 2, 4 is a horizontal dummy circuit having the same step as the horizontal scanning circuit 2, and 5 is a vertical dummy having the same step as the horizontal scanning circuit 2. A circuit, 6 is a liquid crystal seal region, 7 is a liquid crystal, 8 is a semiconductor substrate, and 9 is a counter substrate.

The semiconductor substrate 8 is a Si substrate manufactured by the method shown in FIG. The Si substrate is a Si single crystal substrate which is excellent in economy and has an extremely excellent crystallinity which is uniform and flat over a large area, and a semiconductor active element is formed on a Si single crystal layer having a significantly small number of defects. Therefore, the stray capacitance of the semiconductor element is reduced, high-speed operation is possible, and a high-performance liquid crystal in which elements and circuits excellent in radiation resistance without latch-up phenomenon are integrated on the same substrate as the liquid crystal image display pixel. A display can be provided.

An example of a method for manufacturing a Si substrate will be described below with reference to FIG.

A P-type (10
0) A single crystal Si substrate is anodized in an HF solution to form a porous Si substrate.

The anodizing conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ^-2 ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1:
1: 1 time: 2.4 (hour) Porous Si thickness: 300 (μm) Porosity: 56 (%) P-type (100) porous Si substrate 101 thus obtained
The Si epitaxial layer 102 is formed on the upper surface by low pressure CVD.
Are grown with a layer thickness of 1.0 micron. The deposition conditions are as follows.

Source gas: SiH ₄ carrier gas: H ₂ Temperature: 850 ° C. Pressure: 1 × 10 ^-2 Torr Growth rate: 3.3 nm / sec Next, an oxide layer 103 of 1000 Å is formed on the surface of the epitaxial layer 102. Forming an oxide layer 104 of 5000 angstroms on the surface,
The other Si substrate 107 on which the nitride layer 105 of 1000 angstrom is formed is laid on top of one another and placed in a nitrogen atmosphere for 8 hours.
By heating at 00 ° C. for 0.5 hour, the two Si substrates are firmly bonded together.

Thereafter, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide solution (10:
Selective etching was carried out in a 6:50) without stirring.
After 65 minutes, only the non-porous Si layer remained without being etched, and the porous Si substrate 101 was selectively etched using single crystal Si as an etching stop material and completely removed. The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, the etching layer is 50 angstroms or less even after 65 minutes, and the selectivity with the etching rate of the porous layer reaches 10 5 or less,
The etching amount (tens of angstroms) in the non-porous layer is practically negligible. In this way, porous Si having a thickness of 200 microns is obtained.
Substrate 101 was removed and 1.0 μ on SiO ₂ 103
A single crystal Si layer 102 having a thickness of m can be formed. When SiH ₂ Cl is used as the source gas, it is necessary to raise the growth temperature by several tens of degrees, but the enhanced etching characteristic peculiar to the porous substrate is maintained.

A TFT is formed on the single crystal silicon thin film 102, and thereafter, the Si substrate side is covered with a hydrofluoric acid-resistant rubber except under the liquid crystal pixel portion, and a mixed solution of hydrofluoric acid, acetic acid, and nitric acid is used. The light transmitting portion 110 is formed by partially removing the silicon substrate up to the insulating layer. Thus, a substrate with TFT as shown in FIG. 5D is prepared.

Although quartz glass can be used as the semiconductor substrate 8 in addition to the Si wafer, the present invention is particularly effective when a single crystal Si substrate, which is difficult to flatten as described above, is used.

According to the present embodiment, since the patterns 2 to 5 having the same step are arranged on the four sides around the pixel region 1 on the semiconductor substrate 8 and the liquid crystal seal region 6 is provided thereon, the liquid crystal cell gap is reduced. Becomes uniform. In addition, the peripheral scanning circuit 2,
Since the liquid crystal seal area 6 is arranged on the chip 3, the chip size can be reduced. Furthermore, since the dummy circuits 4 and 5 can be formed in the same process as the peripheral operation circuits 2 and 3, the productivity is excellent.

(Embodiment 2) FIG. 3 is a top view of a liquid crystal display device of this embodiment. In FIG. 3, 11 is a signal line in a vertical direction, a gate line is in a horizontal direction, a pixel area in which transistor switches for transferring signals to each pixel electrode are two-dimensionally arranged at an intersection thereof, and 12 is an image in an odd signal line. A horizontal scanning circuit for inputting a signal, a horizontal scanning circuit for inputting a video signal on an even signal line, a vertical scanning circuit for inputting a gate signal on an odd gate line, and a vertical scanning circuit for inputting a gate signal on an even gate line. The scanning circuit 16 is a liquid crystal seal area,
The scanning circuits 12 to 15 have the same step.

In the present embodiment, the patterns 12 to 15 having the same step are arranged on the four sides around the pixel area 11, and all of them are used as a peripheral scanning circuit. In this embodiment, as in the first embodiment, the peripheral scanning circuit 12 having the same step difference is provided.
Since the liquid crystal seal region 16 is disposed on the upper surfaces 15 to 15, the liquid crystal cell gap can be made uniform and the chip size can be reduced.

(Embodiment 3) FIG. 4 is a top view of a liquid crystal display device of this embodiment. In FIG. 4, reference numeral 21 is a vertical signal line, a horizontal gate line, and a pixel region in which transistor switches for transferring signals to respective pixel electrodes are two-dimensionally arranged at the intersections thereof, 22 is a horizontal scanning circuit, and 23 is a horizontal scanning circuit. Is a vertical scanning circuit for inputting a gate signal to an odd gate line, 24 is a vertical scanning circuit for inputting a gate signal to an even gate line having the same step as the vertical scanning circuit 23, and 25 is a liquid crystal seal region.

As in this embodiment, at least the pixel region 21
By arranging the patterns 23 and 24 having the same level difference on the two opposite sides and providing the liquid crystal seal region 25 on the patterns 23 and 24, the liquid crystal cell gap can be sufficiently made uniform. Also, FIG.
As is clearer, the chip size can be further reduced.

[0024]

As described above, according to the present invention, a liquid crystal display device having a uniform cell gap and no color unevenness can be provided without enlarging the chip size and without adding extra steps. Obtainable.

[Brief description of drawings]

FIG. 1 is a top view of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line A-A ′ in FIG.

FIG. 3 is a top view of the liquid crystal display device according to the second embodiment of the present invention.

FIG. 4 is a top view of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a method of manufacturing a semiconductor substrate.

FIG. 6 is a sectional view of a conventional liquid crystal display device.

FIG. 7 is a cross-sectional view of a conventional liquid crystal display device.

FIG. 8 is a sectional view of a conventional liquid crystal display device.

Claims (1)

[Claims] 1. A liquid crystal display device comprising: a circuit element having the same level difference around at least two opposite sides of a pixel area; and a liquid crystal seal area provided on the circuit element.