JPH05210110A - Active matrix liquid crystal display device - Google Patents

Abstract

PURPOSE:To obscure gate lines even if these lines are provided and to obviate the generation of the deviation in timing for driving by constituting all the contours of picture elements of diagonal lines and disposing these picture elements at equal intervals longitudinally and transversely in series. CONSTITUTION:Signal lines 2 and the gate lines 3 are formed zigzag along the spaces between the picture elements 1. The signal lines 3 are formed along the space lines of every other column with the space lines between the picture elements 1 continuing zigzag in the longitudinal direction as one column of the space lines. The picture elements 1 existing zigzag along one signal line 2 on both sides thereof are connected to the same signal line 2. The gate lines 3 are formed along the space lines of the respective rows with the space lines between the picture elements 1 continuing zigzag in the transverse direction as one row of the space lines. The picture elements 1 existing along one piece of the gate line 3 on one side thereof are connected to the same gate line 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal display device, and more particularly to the shape of each pixel and its arrangement state.

[0002]

2. Description of the Related Art Conventionally, as shown in FIGS. 8 and 9, a pixel and its arrangement state in an active matrix liquid crystal display device have been generally used.

In the structure shown in FIG. 8, pixels 101 each having a substantially rectangular shape are arranged in series vertically and horizontally at equal intervals.

The pixel shown in FIG. 9 also uses a substantially rectangular pixel 101. In the pixel shown in FIG. 9A, the pixel 101 in the nth row is different from the pixel 1 in the n + 1th row.
01 are arranged laterally offset by 1/2 pitch, and in the example shown in FIG.
01 of the pixel 101 in the (m + 1) th column is 1/2 in the vertical direction.
The pitch is shifted. In either case, the pixels 101 are arranged in a vertical and horizontal direction in series, and in a zigzag manner in the other direction, at equal intervals.

Incidentally, 102 and 103 in FIG. 8 and FIG.
Indicates a signal line and a gate line, respectively.

[0006]

By the way, each pixel 10
Between 1 and 2, a light-shielding portion is provided in order to obtain a clear image with clear contrast. Also usually
The signal line 102 and the gate line 103 are formed between the pixels 101, and in general, the gate line 103 is often an opaque wiring.

However, in the case of the above-described conventional pixel 101 and its arrangement, the space between the pixels 101 is an extremely regular space composed of only horizontal lines and vertical lines, so that the light-shielding portion and the opaque gate line 103 are formed. Each pixel 1
If it is formed along the interval 01, these are also composed only of horizontal lines and vertical lines, and there is a problem that they are easily noticeable on the display screen.

Further, in particular, the pixel 10 shown in FIG.
When the gate line 103 is formed in the horizontal direction as usual in 1 and its arrangement state, the driving timing of the pixels 101 connected to one gate line 103 is shifted by ½ pitch for each row, There is also a problem that the circuit for the adjustment becomes complicated.

The present invention is an active matrix liquid crystal display device in which even if a light-shielding portion is formed between pixels or a gate line is provided as an opaque wiring, these are not conspicuous and the drive timing does not deviate as described above. The purpose is to

[0010]

The means taken by the present invention for this purpose will be described with reference to FIG. 1 corresponding to an embodiment of the present invention. In the present invention, each pixel 1 has a contour including a diagonal line. The existing active matrix liquid crystal display device is used.

[0011]

1 and 2 show a first embodiment of the present invention. As is apparent from FIG. 1, a pixel 1 in this embodiment has a substantially rhombic shape. All of the contours of No. 1 are formed by diagonal lines and are arranged in a vertical and horizontal series at equal intervals. Further, the space between the pixels 1 is formed by being sandwiched by the substantially diamond-shaped pixels 1 described above, so that the space is formed as a downward-sloping diagonal line and a downward-sloping diagonal line that intersect with each other as a whole. There is. Further, when the space between the pixels 1 is viewed as vertical and horizontal lines, it can be said that it has a shape in which triangles are arranged in zigzag.

As shown in FIG. 2, the signal line 2 and the gate line 3 are formed in a zigzag pattern along the space between the pixels 1. The signal line 3 is a pixel 1 that is arranged in a zigzag pattern in the vertical direction.
The space line between them as one space line, 1
Pixels 1 that are formed along every other space line and that are present in a staggered manner on both sides of one signal line 2 are connected to the same signal line 2. Further, the gate lines 3 are formed along the space lines of each row with the space lines between the pixels 1 which are arranged in a zigzag pattern in the horizontal direction as one space line, and are present on one side along one of the gate lines 3. Pixel 1 is connected to the same gate line 3.

In the present invention, the pixel 1 means a portion sandwiched between the pixel electrode 4 and a counter electrode (not shown), and the contour of the pixel 1 is sandwiched between the pixel electrode 4 and the counter electrode. The outer peripheral line of the flat area. Also, FIG.
5 is a switching element.

As described above, since the spaces between the pixels 1 in this embodiment are all obliquely formed, even if the light-shielding portion or the gate line 3 as an opaque wiring is provided along this space, the conventional structure has been adopted. Unlike the above, it is not composed of only vertical and horizontal lines, and is composed of diagonal lines, which makes it visually inconspicuous.

By the way, in the present invention, the light-shielding portion means a member forming a non-display portion on the display surface, and it may be specially provided separately. For example, when an opaque gate line 3 is formed between the pixels 1. The gate line 3 also serves as a light shielding portion. When the opaque signal line 2 is formed between the pixels 1, the signal line 2 also serves as a light shielding portion.

On the other hand, since the pixels 1 connected to one gate line 3 are arranged in series in the lateral direction, when driving the pixels 1 connected to one gate line 3, there is a difference in driving timing. It can be driven without occurring.

In this embodiment, the signal line 2 is formed in the vertical direction and the gate line 3 is formed in the horizontal direction. However, the state of FIG. 2 is rotated by 90 degrees, that is, the gate line 3 and the horizontal line are formed in the vertical direction. The same applies when the signal line 2 is formed in the direction.

FIGS. 3 and 4 show a second embodiment of the present invention. In FIGS. 1 and 2, except that the gate line 3 is provided as a transparent wiring in a straight line in the lateral direction. It is similar to that described. The connection state between the signal line 2 and the gate line 3 in each pixel 1 is as shown in FIG.

In this way, the same advantages as those described with reference to FIGS. 1 and 2 can be obtained, and the gate line 3 itself does not function as a light-shielding portion, but is transparent, so that the display surface can be obtained. The aperture ratio can be improved.

FIG. 5 shows a third embodiment of the present invention. Contrary to the above-described second embodiment, FIG. 5 is different from FIG. 1 except that the signal line 2 is provided as a transparent wiring in a straight line in the vertical direction. And similar to those described with reference to FIG. 2, and in this way the same benefits as described with reference to FIGS. 1 and 2 can be obtained.

FIG. 6 shows a fourth embodiment of the present invention, in which each pixel 1 has a substantially octagonal shape and is arranged in series in the lateral direction, and the pixel 1 in the n-th row is arranged in series. n + 1
Pixels 1 in a row are laterally displaced by 1/2 pitch. Therefore, the space between the pixels 1 viewed as lines in the vertical and horizontal directions has a shape in which zigzags are arranged in a mountain shape, and although some of them have vertical or horizontal line portions, most of them are shaded portions.

The signal lines 2 and the gate lines 3 are formed in zigzag along the spaces between the pixels 1. The signal line 3 is a space line between the pixels 1 that are arranged in a zigzag pattern in the vertical direction.
Pixels 1 that are formed along every other column as space lines of columns and that are present in a zigzag pattern on both sides of one signal line 2 are connected to the same signal line 2. Further, the gate line 3 has a space line between the pixels 1 which are arranged in a zigzag pattern in the horizontal direction as one space line,
Pixels 1 that are formed along the space lines of each row and that are present on one side along one gate line 3 are connected to the same gate line 3.

In this way, although there are vertical and horizontal line portions in a part of the space between the pixels 1, they are mixed with the diagonal line portions, and therefore, as a whole as described with reference to FIGS. 1 and 2. You can get similar benefits.

FIG. 7 shows a fifth embodiment of the present invention, which is particularly adapted to color display. In this embodiment as well, the shape of the pixel 1 is the same as that of the fourth embodiment of FIG. 6, but the pixel 1 connected to one signal line 2 is the (n + 1) th pixel with respect to the nth row pixel 1. This is different from the fourth embodiment in FIG. 6 in that the pixels 1 in the row are laterally displaced by 1.5 pitches. Also, R, G, B shown in the figure are red, green,
1 shows a pixel 1 having filters of three primary colors of blue.

As described above, even in the case where the pixels are arranged with a shift of 1.5 pitches between the rows and the pixels 1 of the same color are not adjacent to each other to improve the resolution, the fourth arrangement described with reference to FIG. Similar to the embodiment, the same benefits as those described in FIGS. 1 and 2 can be obtained.

By the way, as the switching element 5 in each of the above-mentioned embodiments, an FET is generally used, and the FET having its active layer made of a single crystal material is most preferable. Further, in the case of this single crystal material, since the carrier mobility is high and the electric resistance is low, the signal line 2 is connected to the FET.
It is possible to use the same material at the same time as the active layer. When the signal line 2 is made of a single crystal material, the signal line 2 can also serve as a light shielding portion, and the inconspicuous signal line 2 and light shielding portion according to the present invention can be used as an FET with excellent performance.
At the same time, there are benefits that can be formed.

In this embodiment, the active layer may be made of a non-single crystal material when the resistance of the signal line does not matter, such as when the number of pixels is small. Needless to say, the effect of the present invention is also effective in this case.

Particularly, when the active layer of the FET and the signal line 2 are made of single crystal silicon, it is easily performed by forming the single crystal silicon layer using a temporary substrate of porous silicon obtained by making the single crystal silicon porous. be able to.

According to observation with a transmission microscope, pores having an average of about 600 Å are formed on the temporary substrate of porous silicon, and the density thereof is less than half that of single crystal silicon. However, its single crystallinity is maintained, and single crystal silicon can be epitaxially grown on the upper part of the porous layer. However, at 1000 ° C. or higher, rearrangement of internal holes occurs, and the characteristics of enhanced etching are impaired. Therefore, for the epitaxial growth of the silicon layer, the molecular beam epitaxial growth method, plasma CV
Low temperature growth such as D method, thermal CVD method, photo CVD method, bias sputtering method, liquid crystal growth method, etc. is suitable.

Here, a method for epitaxially growing a single crystal layer after making P-type silicon porous will be described.

First, a temporary silicon single crystal substrate is prepared, and this is made porous by an anodization method using an HF solution.

The density of single crystal silicon is 2.33 g / cm.
² , the density of the porous silicon is 0.6-1.1 g / c by changing the concentration of the HF solution to 20-50%.
It can be changed to m ² . The porous layer is easily formed on the P-type silicon temporary substrate for the following reason.

Porous silicon was discovered in 1956 in the course of research on electropolishing of semiconductors. Further, it has been reported from the research on the dissolution reaction of silicon in the anodization that holes are necessary for the anodic reaction of silicon in the HF solution, and the reaction is as follows.

Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + n
e ⁻ SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4-λ) e ⁺ → SiF ₄ + 4H ⁺ + λ
e ⁻ SiF ₄ + 2HF → H ₂ SiF ₆ Here, e ⁺ and e ⁻ represent holes and electrons, respectively.
Further, n and λ are the numbers of holes required for dissolving one atom of Si, respectively, and porous silicon is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, it can be said that P-type silicon in which holes are present is likely to be made porous. The selectivity in this porosification is a matter already demonstrated.

On the other hand, it has been reported that high-concentration N-type silicon can also be made porous. Therefore, porosity can be achieved regardless of whether it is P-type or N-type.

Further, since the porous layer has a large amount of voids formed therein, the density thereof is reduced to less than half.
As a result, the surface area is drastically increased compared to the volume, so that the chemical etching rate is significantly increased as compared with the etching rate of a normal single crystal layer.

An example of conditions for making single crystal silicon porous by anodization is shown below. The starting material of the porous silicon formed by anodization is not limited to single crystal silicon, but silicon of other crystal structure may be used.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1:
1: 1 time: 2.4 (hour) Thickness of porous silicon: 300 (μm) Porosity: 56% Single crystal silicon thin film obtained by epitaxially growing silicon on the temporary substrate of porous silicon thus formed. To form. The thickness of the single crystal silicon thin film is preferably 50 μm or less, more preferably 20 μm or less.

Next, the surface of the single crystal silicon is attached to a substrate used for a liquid crystal display device. This bonding is preferably performed after oxidizing the surface of the single crystal silicon. This is because, for example, when a glass plate is used as the substrate, the interface level generated by the underlying interface of the silicon active layer can be lower in the oxide film interface than in the glass interface, and the characteristics of the electronic device are significantly reduced. This is because it can be improved. Further, it is also possible to bond only a thin film of single crystal silicon obtained by etching away the temporary substrate of porous silicon by selective etching described later to the substrate.

The bonding is carried out by simply contacting each surface at room temperature after washing, and by Van den Waals force.
It can be adhered so that it cannot be easily peeled off, but this is further 200 to 900 ° C., preferably 600
It is preferable to heat-treat at a temperature of up to 900 ° C. in a nitrogen atmosphere to completely bond them.

Si is formed on the above-mentioned bonded temporary substrate and the entire substrate.
_{A 3} N ₄ layer is deposited as an etching preventive film, and only the Si ₃ N ₄ layer on the surface of the temporary substrate of porous silicon is removed. Apizone wax may be used instead of the Si ₃ N ₄ layer.

Thereafter, the temporary substrate made of porous silicon is entirely removed by a method such as etching to obtain a substrate having a single crystal silicon layer.

A selective etching method for electroless wet etching only the temporary substrate of porous silicon will be described below.

As an etching solution which does not have an etching action on crystalline silicon and can selectively etch only porous silicon, hydrofluoric acid and ammonium fluoride (NH
₄ F) or buffered hydrofluoric acid such as hydrogen fluoride (HF), hydrofluoric acid containing hydrogen peroxide or a mixed solution of buffered hydrofluoric acid, hydrofluoric acid containing alcohol or a mixed solution of buffered hydrofluoric acid, A mixed solution of hydrofluoric acid or buffered hydrofluoric acid to which hydrogen peroxide solution and alcohol are added is preferably used. Etching is performed by moistening a temporary substrate on which a single crystal silicon layer is formed or a laminate of the temporary substrate and the substrate in these solutions.

The etching rate depends on the solution concentration and temperature of hydrofluoric acid, buffered hydrofluoric acid and hydrogen peroxide. By adding hydrogen peroxide solution, the oxidation of silicon can be accelerated, and the reaction rate can be increased as compared with the case of no addition.
Further, the reaction rate can be controlled by changing the ratio of the hydrogen peroxide solution. Further, by adding alcohol, the bubbles of the reaction product gas due to the etching can be instantaneously stirred and removed from the etching surface, and the porous silicon can be uniformly and efficiently etched.

The HF concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 1 to 85% by weight, still more preferably 1 to 70% by weight with respect to the etching solution. The NH ₄ concentration in the buffered hydrofluoric acid is preferably 1 to 95% by weight with respect to the etching solution,
More preferably 5 to 90% by weight, still more preferably 5 to 8
It is set in the range of 0% by weight.

The HF concentration is preferably 1 to 95% by weight, more preferably 5 to 90% by weight, based on the etching solution.
More preferably, it is set in the range of 5 to 80% by weight.

The H ₂ O ₂ concentration is preferably 1 to 95% by weight, more preferably 5 to 90% by weight, and even more preferably 10 to 80% by weight, based on the etching solution, to obtain the above effect of the hydrogen peroxide solution. It is set within the playing range.

The alcohol concentration is preferably 80% by weight or less, more preferably 60% by weight, based on the etching solution.
Hereafter, it is more preferably set to 40% by weight or less and within the range in which the effect of the above alcohol is exhibited. It should be noted that the alcohol may be ethyl alcohol, isopropyl alcohol, or the like as long as it has no practical problem in the production process and the effect of adding the alcohol can be expected.

The temperature is preferably set in the range of 0 to 100 ° C, more preferably 5 to 80 ° C, further preferably 5 to 60 ° C.

The semiconductor substrate thus obtained has a single-crystal silicon flat and uniformly thinned over the entire surface of the substrate, like a normal silicon wafer. Therefore, by using the substrate having this single crystal silicon, the active layer of the FET and the signal line 2 can be easily formed simultaneously with the single crystal silicon.

Although the single crystal silicon has been described as an example, the active layer of the FET and the signal line 2 can be simultaneously formed of single crystal gallium-arsenide. In this case, after the single crystal silicon layer is formed on the temporary substrate by the procedure described above, the single crystal gallium-arsenic is epitaxially grown on the single crystal silicon layer, and the single crystal gallium-arsenic layer is bonded to the substrate. The temporary substrate and the single crystal silicon layer may be selectively removed by etching.

[0054]

The present invention is as described above, and when a signal line or a gate line is provided as an opaque wiring or a light shielding layer is provided, these are made inconspicuous and a good image is obtained. In addition, it becomes easier and does not cause inconvenience such as deviation of driving timing between pixels connected to the same gate line.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a pixel shape and its arrangement in a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a connection state of pixels, signal lines, and gate lines in FIG.

FIG. 3 is an explanatory diagram of a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a connection state between a pixel, a signal line, and a gate line in FIG.

FIG. 5 is an explanatory diagram of a third embodiment of the present invention.

FIG. 6 is an explanatory diagram of a fourth embodiment of the present invention.

FIG. 7 is an explanatory diagram of a fifth embodiment of the present invention.

FIG. 8 is an explanatory diagram of a conventional technique.

FIG. 9 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 1 Pixel 2 Signal line 3 Gate line 4 Pixel electrode 5 Switching element

Claims (3)

[Claims] 1. An active matrix liquid crystal display device, wherein each pixel has a contour including a diagonal line. 2. The active matrix liquid crystal display device according to claim 1, wherein at least a part of the light-shielding portion formed between the pixels is formed in a slanting line shape along a slanting line portion of an outline of the pixel. .. 3. The switching element of each pixel is a FET,
3. The active matrix liquid crystal display device according to claim 2, wherein the active layer and the signal line are made of the same crystal material, and the signal line also serves as a light shielding portion.