JP3375814B2 - Active matrix display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix display device such as a liquid crystal display device, a plasma display device and an EL display device.

[0002]

2. Description of the Related Art FIG. 2A shows a schematic view of a conventional example of an active matrix display device. A region 104 surrounded by a broken line in the drawing is a display region, and the thin film transistors 101 are arranged in a matrix therein. The source electrode of the thin film transistor 101 has an image (data) signal line 1
A gate (selection) signal line 105 is connected to the gate electrode of the thin film transistor 101. A plurality of gate signal lines 105 and image signal lines 106 are arranged so as to be substantially perpendicular to each other.

The auxiliary capacitance 102 is a capacitor for reinforcing the capacitance of the pixel cell 103 and is used for holding image data. The thin film transistor 101 is used to switch the image data of the voltage applied to the pixel cell 103.

It is generally known that in a thin film transistor, when a reverse bias is applied to the gate, a leak current (referred to as an OFF current) flows instead of a state in which no current flows (OFF state) between the source and the drain. It was There has been a problem that the potential of the pixel cell fluctuates due to such a leak current.

In the case of an N-channel type thin film transistor, when the gate is negatively biased, a PN junction is formed between the P-type layer induced on the surface of the semiconductor thin film and the N-type layers of the source region and the drain region. However, since many traps exist in the semiconductor thin film, this PN junction is incomplete and a junction leak current easily flows. The OFF current increases as the gate electrode is biased more negatively because the carrier concentration of the P-type layer formed on the surface of the semiconductor thin film increases and the width of the energy barrier of the PN junction narrows.
This is because the electric field is concentrated and the junction leak current is increased.

The OFF current thus generated largely depends on the source / drain voltage. For example, it is known that the OFF current dramatically increases as the voltage applied between the source / drain of the thin film transistor increases. That is, 5 between the source and drain
In the case where the voltage of V is applied and the case where the voltage of 10 V is applied, the OFF current of the latter may be 10 times or 100 times as large as that of the former. Further, such non-linearity also depends on the gate voltage. Generally, when the reverse bias value of the gate electrode is large (a large negative voltage in the N-channel type), the difference between the two is remarkable.

In order to solve this problem, for example, a method of connecting thin film transistors in series (multigate method) has been proposed, as described in JP-B-5-44195 and JP-B-5-44196. . This is intended to reduce the OFF current of each thin film transistor by reducing the voltage applied to the source / drain of each thin film transistor. For example, as shown in FIG. 2B, two thin film transistors 111
When 112 and 112 are connected in series, the voltage applied to the source / drain of each thin film transistor is halved.
If the voltage applied to the source / drain is halved, the OFF current becomes 1/10 or 1/100 from the above discussion. Note that in FIG. 2B, 113 is an auxiliary capacitor,
Reference numeral 114 is a pixel cell, and 115 is a gate signal line.

[0008]

However, when the characteristics required for displaying an image on a liquid crystal display become strict, it becomes difficult to reduce the OFF current as much as necessary even in the above multigate method. That is, even if the number of gate electrodes (number of thin film transistors) is increased to 3, 4, and 5, the voltage applied to the source / drain of each thin film transistor is 1/3, 1/4, 1/5. This is because it decreases only slightly. Further, there is also a problem that the circuit is complicated and the occupied area becomes large.

The present invention has been made in view of the above problems, and the voltage applied to the source / drain of the thin film transistor connected to the pixel electrode is not more than 1/10 of that in the usual case, preferably 1 It is to provide a pixel circuit having a structure that reduces the OFF current by setting the ratio to / 100 or less.

[0010]

One of the inventions disclosed in this specification is to provide an image signal line and a gate signal line arranged in a matrix and an area surrounded by the image signal line and the gate signal line. In the active matrix display device having the arranged pixel electrode, n thin film transistors (n is a natural number except zero) of the same conductivity type are arranged in series adjacent to the pixel electrode. In the n thin film transistors connected in series, the source or drain region of the n = 1th thin film transistor is connected to the image signal line, the drain or source region of the nth thin film transistor is connected to the pixel electrode, and m
The potentials of the gate electrodes of the thin film transistors (n> m, m is a natural number) are different from those of the m thin film transistors because the channel formation region is fixed to the same conductivity type as the source and drain regions. The gate electrodes of the thin film transistors are commonly connected to the gate signal line, and at least one of the two regions adjacent to the channel formation region has a low concentration of impurities imparting a conductivity type to the source or drain region. An active matrix display device characterized by being an impurity region.

In the above structure, n and m are natural numbers except 0. N = 5 to obtain the desired effect
The above is preferable.

FIG. 2C shows a concrete example of the above structure. In the structure shown in FIG.
N = 5 thin film transistors indicated by 5 are arranged. In the configuration shown in FIG. 2C, n = 5 and m =
It becomes 2.

The n = 1th thin film transistor 1
21 source regions are connected to the image signal line 129. In addition, the n-th (fifth) thin film transistor 123
Of the pixel cell 127 is connected to one electrode (pixel electrode) of the pixel cell 127 and the auxiliary capacitance 126.

The gate electrodes of the n-m (n> m) thin film transistors 121, 122 and 123 are connected to the common gate signal line 128, and the present invention has an LDD structure and an offset structure. ing. On the other hand, the gate electrodes of the m thin film transistors 124 and 125 are connected to the common capacitance line 130.
The configuration is such that 0 is maintained at an appropriate potential.

The basic idea of the invention disclosed in this specification is, as shown in FIG.
1, 122, 123, 124, 125 are connected in series,
Of these, the gates of the thin film transistors 121 to 123 are connected to the gate signal line 128, and the other thin film transistors 1 are connected.
To connect the gates 24 and 125 to the capacitance line 130. Then, in the time for holding the potential of the pixel,
By holding the capacitance line at an appropriate potential, a capacitance is formed between the channels of the thin film transistors 124 and 125 and the gate electrodes.

Then, the thin film transistors 122 and 123
The voltage appearing between the source and drain of the
The OFF current of these thin film transistors can be reduced. Although the auxiliary capacitance 126 is also shown in the figure, this is not always necessary. Rather, since it increases the load at the time of writing, it may be preferable that the ratio of the capacitance of the pixel cell 127 and the capacitance generated in the thin film transistors 124 and 125 is not optimum if it is not optimal.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION A specific operation will be described with reference to FIG. When the selection signal is sent to the gate signal line 128, all the thin film transistors 121 to 123 are turned on. At this time, the thin film transistor 1
It is necessary to apply a signal to the capacitance line 130 so that 24 and 125 are also turned on. As a result, the pixel cell 127 is charged according to the signal of the image signal line 129, but at the same time, the thin film transistors 124 and 125 are also charged.
At the fully charged (equilibrium) stage, the source / drain voltages of the thin film transistors 122 and 123 are substantially equal.

When the selection signal is turned off in this state, all the thin film transistors 121 to 123 are turned off. However, at this stage, the thin film transistors 124 and 125 are
Is still in the ON state. After that, the image signal line 12
Since signals of other pixels are applied to the thin film transistor 9 and the thin film transistor 121 has a finite OFF current, the charges charged in the thin film transistor 124 are discharged, and the voltage drops. However, this speed progresses at the same speed as the voltage drop of the capacitor 102 of the normal active matrix circuit shown in FIG.

On the other hand, regarding the thin film transistor 122, since the voltage between the source and the drain was almost 0 at the beginning, the OFF current was extremely small, but after that,
Since the voltage of the thin film transistor 124 drops, the voltage between the source and the drain gradually increases, and therefore the OF
The F current will also increase. Similarly, the OFF current of the thin film transistor 123 also gradually increases, but needless to say, the speed thereof is smaller than that of the thin film transistor 122. From the above, the pixel cell 12 due to the increase in the OFF current of these thin film transistors
It goes without saying that the voltage drop of 7 is much slower than that in the normal active matrix circuit shown in FIG.

Further, in the present invention, since the LDD regions and the offset regions are formed in the channels of the thin film transistors 121 to 125, these regions become the drain resistance and the source resistance, so that the electric field strength of the drain junction is relaxed and the OFF current is further reduced. Can be reduced. Such a circuit has a gate signal line 128 and a capacitance line 130 in a substantially M-shaped semiconductor region 100 as shown in FIG.
The degree of integration can be increased by adopting a circuit arrangement such that they are stacked. FIGS. 1B to 1D show possible combinations in that case, and the same effect can be obtained by adopting any of them.

FIG. 1B shows the most orthodox shape, and the thin film transistor 121 is formed by intersecting the semiconductor region 100 with the gate signal line 128 and the capacitance line 130.
.About.125 are formed at the intersections (3 intersections with the gate signal line, 2 intersections with the capacitance line, 5 in total). In the semiconductor region, there are N-type or P-type regions in the regions separated (sandwiched) by the gate signal line and the capacitance line (four in FIG. 1B) and the regions at both ends of the semiconductor region. Impurities are introduced to serve as the source / drain of the thin film transistor. In particular, a low concentration impurity region, so-called L, is formed in the source / drain of a thin film transistor using a gate signal line as a gate electrode.
By forming DD, the OFF current can be further reduced. Note that the image signal line and the pixel electrode may be formed so as to be connected to either end of the semiconductor region.

As shown in FIG. 1C, the points a and b are connected to the capacitance line 1
It is possible if 30 is not covered. This is because it is sufficient for the thin film transistors 124 and 125 to function only as capacitors. In addition, as shown in FIG. 1D, with respect to the semiconductor region 100, the gate signal line 128 is crossed at four points and the capacitance line 130 is crossed at two points, so that six series-connected thin film transistors 131 to 131 are connected. It is also possible to configure 136. The equivalent circuit diagram in this case is shown in FIG.
2C, which corresponds to the circuit illustrated in FIG. 2D and includes two thin film transistors 132 in which the thin film transistor 122 illustrated in FIG.
This is equivalent to the one replaced by 133, and the OFF current can be reduced as compared with the circuit in FIG.

[0023]

【Example】

Example 1 In this example, an offset gate and an LDD are formed by anodizing the gate electrode, and O
The feature is that the FF current is further reduced. A technique for anodizing the gate electrode is disclosed in Japanese Patent Laid-Open No. 5-267667. FIG. 1 shows a top view of the circuit of this embodiment, and FIG. 3 shows a cross-sectional view of the manufacturing process. In FIG. 3, the left side shows a cross-sectional view taken along the dashed-dotted line X-Y in FIG.
On the right side, a cross-sectional view taken along the dotted line X'-Y 'in the figure is shown.
However, it should be noted that the dashed-dotted lines X-Y and X'-Y 'are drawn adjacent to each other in FIG. 3, but are not actually on the same straight line.

First, the substrate 301 (Corning 7059,
100 mm × 100 mm) and a silicon oxide film 302 as a base film with a thickness of 1000 to 5000 Å, for example, 3
A film was formed at 000Å. This silicon oxide film 302 is TEOS
Is decomposed and deposited by a plasma CVD method to form a film.
Alternatively, the film may be formed by a sputtering method.

After that, an amorphous silicon film of 300 to 1500 Å is formed by plasma CVD method or LPCVD method.
To the thickness of, for example, 500 Å
Let it stand in an atmosphere of 600 ° C. for 8 to 24 hours for crystallization. At that time, if a small amount of nickel is added to the amorphous silicon film, crystallization is promoted. JP-A-6-24
No. 4104 and the like disclose a technique for promoting crystallization by adding a catalytic metal element such as nickel, thereby lowering / shortening the crystallization temperature / crystallization time. The crystallization process may be performed by combining optical annealing such as laser irradiation, thermal annealing and optical annealing.

Then, the crystallized silicon film is etched to form an approximately M-shaped island-shaped region 10 shown in FIG.
Form 0. Further, a thickness of 700 to 1500 is formed on the island region 100 by the plasma CVD method or the sputtering method.
A Å, for example, 1200 Å silicon oxide film 303 is formed. (Fig. 1 (A), Fig. 3 (A))

Thereafter, 1 wt% of Si or 0.1
An aluminum film containing 0.3 wt% of Sc is formed by a sputtering method with a thickness of 1000Å to 3 µm, for example, 5000Å. Next, in an ethylene glycol solution containing 3% tartaric acid, an aluminum film was used as an anode and a voltage of 10 to 30 V was applied by an anodic oxidation method, and a dense film with a film thickness of several hundred Å, here 200 Å, was formed. An anodized layer 304 of aluminum oxide is formed. The anodic oxide layer 304 is for ensuring good adhesion of the photoresist.

Next, a photoresist mask 305 is formed, and the aluminum film is etched using this mask 304 to form gate electrodes 306 to 309.
In FIG. 1B, the gate electrodes 306 and 307 correspond to the gate signal line 128, and the gate electrodes 308 and 309 correspond to the capacitance line 130. (Fig. 3 (A))

At this time, as shown in FIG. 9, the aluminum film region 802 is left around the active matrix region 805 on the substrate 806, and the gate signal line 128 and the capacitance line 13 (corresponding to the aluminum wiring 801 in FIG. 9). .)
Are preferably etched so that they are all connected to the aluminum film region 802. However, in this case, the peripheral circuits, that is, the gate driver 803 and the source driver 80
If the aluminum wiring such as the gate electrode of No. 4 is designed so that the aluminum film region 802 is insulated from the aluminum film region 802, the aluminum wiring of the peripheral circuit does not have to be anodized, so that the degree of integration can be improved. .

As shown in FIG. 3 (B), the gate electrode 306, with the photoresist 305 mask attached,
307, that is, only the gate signal line 128 is anodized,
A porous anodic oxide 310 is formed. In this process, 3
In an acidic aqueous solution of ˜20% citric acid or oxalic acid, phosphoric acid, chromic acid sulfuric acid, etc., only the gate electrodes 306 and 307, that is, only the gate signal line 128 shown in FIG. A voltage may be applied. In this example, a voltage of 10 V is 20 to 20 in an oxalic acid solution (30 ° C.).
Apply for 40 minutes. The thickness of the porous anodic oxide 310 can be controlled by the anodic oxidation time, and the porous anodic oxide 3 can be controlled.
A thickness of 10 determines the length of the LDD region.

At this time, forming the anodic oxide layer 304 in advance means that the porous anodic oxide is used as the gate electrodes 306 and 30.
It is extremely effective to form only on the side surface of 7. This is because the photoresist mask 305 is brought into close contact with the anodic oxide layer 304, so that the photoresist mask 30 is used.
This is because the current can be prevented from leaking from 5.

As shown in FIG. 3C, after removing the photoresist mask 305, the gate electrodes 306 to 309 are formed again in the electrolytic solution, that is, the gate signal line 128 shown in FIG. A current is applied to the wire 130 to anodize it to form anodized oxides 311 and 312 having a thickness of 500 to 250.
Form 0Å. At this time, the electrolytic solution is prepared by diluting L-tartaric acid with ethylene glycol to a concentration of 5% and adjusting the pH to 7.0 ± 0.2 with ammonia. The substrate is immersed in the solution, the + side of the constant current source is connected to the gate electrode on the substrate, the platinum electrode is connected to the-side, and voltage is applied at a constant current of 20 mA until 150V is reached. Oxidation was continued. Further, oxidation was continued at a constant voltage of 150 V until the current became 0.1 mA or less.

As a result, the gate signal line 128 (gate electrodes 306 and 307) and the capacitance line 130 (gate electrode 3).
08, 309) and anodic oxides 311 and 312 having a dense crystal structure with a thickness of 2000 Å are obtained on the upper and side surfaces thereof. The film thickness of the anodic oxides 311 and 312 may be determined by the length of the offset, and these film thicknesses are proportional to the applied voltage.

Next, as shown in FIG. 3D, the silicon oxide film 303 is etched by using the anodic oxides 311 and 312 around the gate electrodes 306 to 309 as a mask to etch the gate insulating films 313 and 314. To form. In this case, it is necessary to use an etching gas or etching solution having a sufficiently large selection ratio of silicon and silicon oxide.

As shown in FIG. 3 (E), the porous anodic oxide 310 is removed, and the gate electrode portions (gate electrodes 306 to 3-6) are formed on the island region 100 by the ion doping method.
09 and its surrounding anodic oxides 310 to 312) and the gate insulating film 313 are used as masks to implant impurities (here, phosphorus) in a self-aligned manner to form N-type impurity regions 317 to 324. Here, phosphine (PH ₃ ) was used as the doping gas. The dose amount in this case is 5 × 10 ^14.
〜5 × 10 ¹⁵ atoms / cm ² , accelerating voltage 60 ~ 90k
V, for example, the dose amount was 1 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 80 kV. As a result, the gate insulating film 313
Functions as a semi-transparent mask to form high-concentration impurity regions (source / drain) 317 to 320 and low-concentration impurity regions 321 to 324, respectively.

Further, a KrF excimer laser (wavelength 248) nm, pulse width 20 nsec) is irradiated to activate the doped high concentration impurity regions 317 to 320 and low concentration impurity regions 321 to 324. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . This step may be performed by thermal annealing. In particular, it contains a catalytic element (nickel) and can be activated by low-temperature thermal annealing as compared with the usual case (Japanese Patent Laid-Open No. 6-267).
989).

Next, as shown in FIG. 3E, a silicon oxide film having a thickness of 5000 Å was formed as an interlayer insulating film 325 by a plasma CVD method. At this time, the source gas is T
EOS and oxygen were used. Then, the interlayer insulating film 325 is etched to form the high concentration impurity region 317, that is, as shown in FIG.
A contact hole was formed in the source of the thin film transistor 121 in (C), an aluminum film was formed by a sputtering method, and a source electrode / wiring 326 was formed by etching. The source electrode / wiring 326 is an extension of the image signal line 129.

As shown in FIG. 3F, a passivation film 327 is formed. Here, NH ₃ / SiH ₄ /
A silicon nitride film is formed to a film thickness of 2000 to 8000Å, for example, 4000Å by a plasma CVD method using H ₂ mixed gas to form a passivation film 327. Then, the passivation film 327 and the interlayer insulating film 325 are etched to form a high concentration impurity region 320, that is, as shown in FIG.
A contact hole for the drain of the thin film transistor 123 in (C) was formed. Then, an indium tin oxide (ITO) film was formed by a sputtering method, and this was etched to form a pixel electrode 328. The pixel electrode 328 is one of the electrodes of the pixel cell 127.

Through the above steps, the switching circuit having the N-channel type thin film transistors 121 to 125 was formed. The switching circuit of this embodiment corresponds to the switching circuit shown in FIG. 2C from which the auxiliary capacitance 126 is removed. Note that the thin film transistor 122 is not illustrated in FIG.

In the present embodiment, the thin film transistor 12
1, 122 and 123 are porous anode aluminum films 31
The low-concentration impurity regions corresponding to the thickness of 1 are the gate electrodes 306, 3
It has a so-called offset gate structure far from 07,
Moreover, since the low-concentration impurity regions 321 to 324 are formed between the channel formation region and the source / drain so as to have an LDD structure, an OFF current can be reduced, which is suitable as an element arranged in a pixel matrix. Is. It is sufficient that the thin film transistors 124 and 125 function only as capacitors, and thus may not have an LDD structure.

[Embodiment 2] This embodiment is the same as L of Embodiment 1.
This is a modified example of the method for manufacturing the DD structure, and FIG. 1 shows a drawing of the circuit of this embodiment seen from above, and FIG. In FIG. 4, as in FIG. 3, the left side of FIG.
A cross-sectional view taken along the dashed-dotted line X-Y in FIG. 1A is shown, while a cross-sectional view taken along the dashed-dotted line X′-Y ′ in FIG. Although drawn adjacently in FIG. 4, X-Y and X'-
Note that Y'is not on the same line.

First, as shown in FIG. 4A, the substrate 40
1 (Corning 7059, 100 mm × 100 mm) on which a silicon oxide film as a base film 402 is 1000 to 500
A film is formed to a thickness of 0Å, for example, 3000Å. This silicon oxide film decomposes TEOS by the plasma CVD method.
Deposit and form a film. Alternatively, the film may be formed by a sputtering method.

After that, an amorphous silicon film is formed in a thickness of 300 to 1500 Å by plasma CVD method or LPCVD method.
To the thickness of 500 Å, for example,
It is left to stand in an atmosphere of 00 ° C. for 8 to 24 hours to be crystallized. At that time, if a small amount of nickel is added to the amorphous silicon film, crystallization can be promoted. The crystallization process may be performed by combining optical annealing such as laser irradiation, thermal annealing and optical annealing.

Then, the crystallized silicon film is etched to form a substantially M-shaped island-shaped region 10 shown in FIG.
Form 0. Further, a thickness of 700 to 1500 is formed on the island region 100 by the plasma CVD method or the sputtering method.
A Å, for example, 1200 Å silicon oxide film 403 is formed.

Thereafter, 1 wt% of Si or 0.1
An aluminum film containing 0.3 wt% of Sc is formed by a sputtering method with a thickness of 1000Å to 3 µm, for example, 5000Å. Next, in an ethylene glycol solution containing 3% tartaric acid, an aluminum film was used as an anode and a voltage of 10 to 30 V was applied by an anodic oxidation method, and a dense film having a film thickness of about several hundred Å, here, 200 Å. Forming an anodized layer 404 of aluminum oxide. This anodic oxide layer 404 is for ensuring good adhesion of the photoresist.

Next, a photoresist mask 405 is formed, and the aluminum film is etched using this mask 405 to form gate electrodes 406 to 409.
In FIG. 1B, the gate electrodes 406 and 407 correspond to the gate signal line 128, and the gate electrodes 408 and 409 correspond to the capacitance line 130. (Fig. 4 (A))

As shown in FIG. 4B, the gate electrode 406, with the photoresist mask 405 attached,
407 is anodized to form a porous anodic oxide 410. In the oxalic acid solution (30 ° C.), a voltage of 10 V is applied for 20 to 40 minutes only to the gate signal line 128 shown in FIG. 1 (B). The thickness of the porous anodic oxide 410 can be controlled by the anodic oxidation time, and by the thickness of the porous anodic oxide 410,
The length of the LDD region is determined. At this time, since the photoresist mask 305 is in close contact with the anodized layer 304, current can be prevented from leaking from the photoresist mask 405. Therefore, the porous anodic oxide is used as the gate electrode 406. , 407 can be formed only on the side surface.

Next, as shown in FIG. 4C, the silicon oxide film 403 is etched using a photoresist mask 405 to form gate insulating films 411 and 412.

As shown in FIG. 4D, after the photoresist mask 405, the porous anodic oxide 410 and the dense anodic oxide layer 404 are sequentially removed, the gate electrodes 406 to 409 are formed by ion doping. Using the gate insulating film 411 as a mask, impurities (here, phosphorus) are implanted into the island-shaped region 100 to form the N-type impurity regions 413 to 320 in a self-aligned manner. Here, phosphine (PH ₃ ) was used as the doping gas. In this case, the dose amount is 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage is 60 to 90 kV. For example, the dose amount is 1 × 10 ¹⁵ atoms / cm ² .
cm ² , and the acceleration voltage is 80 kV. As a result, the gate insulating film 411 functions as a semi-transparent mask, and high-concentration impurity regions (source / drain) 413 to 416 and low-concentration impurity regions 417 to 420 are formed, respectively.

Furthermore, a KrF excimer laser (wavelength 248) nm and a pulse width of 20 nsec are irradiated to activate the doped high concentration impurity regions 413 to 416 and the low concentration impurity regions 417 to 420. The energy density of the laser was 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² . This step may be performed by thermal annealing. In particular, it contains a catalytic element (nickel) and can be activated by low-temperature thermal annealing as compared with the usual case (Japanese Patent Laid-Open No. 6-267).
989).

Next, as shown in FIG. 4E, a silicon oxide film having a thickness of 5000 Å was formed as an interlayer insulating film 421 by a plasma CVD method. At this time, the source gas is T
EOS and oxygen were used. Then, the interlayer insulating film 421 is etched to form the high-concentration impurity region 413, that is, in FIG.
A contact hole for the source of the thin film transistor 121 shown in (C) is formed, an aluminum film is formed by a sputtering method, and a source electrode / wiring 422 is formed by etching. The source electrode / wiring 422 is an extension of the image signal line 129.

As shown in FIG. 4F, a passivation film 423 is formed. Here, NH ₃ / SiH ₄ /
A silicon nitride film having a film thickness of 2000 to 8000 Å, for example, 4000 Å was formed by a plasma CVD method using H ₂ mixed gas to form a passivation film 423. Then, the passivation film 423 and the interlayer insulating film 421 are etched to form a high concentration impurity region 416, that is, as shown in FIG.
A contact hole for the drain of the thin film transistor 123 in (C) is formed. Then, an indium tin oxide (ITO) film was formed by a sputtering method, and this was etched to form a pixel electrode 424. The pixel electrode 424 corresponds to one of the electrodes of the pixel cell 127.

Through the above steps, a switching circuit having N-channel thin film transistors 121 to 125 shown in FIG. 2C is formed. The thin film transistor 1
22 is not shown in FIG. 4 (F). The switching circuit of this embodiment corresponds to the switching circuit shown in FIG. 2C from which the auxiliary capacitance 126 is removed.

In this embodiment, the thin film transistors 121 to 121
In 123, low-concentration impurity regions 417 to 420 are formed between the channel formation region and the source / drain, and LD
Since the D structure is used, the OFF current can be reduced, and thus the thin film transistors 121 to 123 are suitable as elements arranged in a pixel matrix. It is sufficient that the thin film transistors 124 and 125 function only as capacitors, and thus may not have an LDD structure.

[Embodiment 3] FIG. 5 shows a process of forming a circuit by using the present invention. A publicly known technique or a technique shown in Embodiments 1 and 2 may be used for a specific process, and thus a detailed description thereof will not be given here. Note that FIG.
Is a cross-sectional view taken along the capacitance line 207 in FIG. 5C, and FIG. 7 is an equivalent circuit diagram of the circuit in FIG. 5C.

First, Examples 1 and 2 (or FIG. 1)
The substantially M-shaped semiconductor regions (active layers) 201 and 202 as described in (A)) were formed. After that, the gate insulating film 240 shown in FIG. 6 was formed, and further the gate signal lines 203 to 205 and the capacitance lines 206 to 208 were formed.
Here, the gate signal lines 203 to 205 and the capacitance line 206 to
The positional relationship between 208 and the active layers 201 and 202 was the same as in the first embodiment. Further, an anodic oxide 241 is formed around it as shown in FIG. (Figure 5 (A))

Then, after doping the active layers 201 and 202, an interlayer insulator 242 shown in FIG. 6 is formed, and further, contact holes 210 and 211 are formed at one end of each active layer 201 and 202 to form an image. The signal line 209 was formed. (Fig. 5 (B))

As shown in FIG. 6, the passivation film 24
After forming 3, the pixel electrodes 212, 213, and 214 were formed in the region surrounded by the gate signal lines 203 to 205 and the image signal line 209 as shown in FIG.
In this way, a switching element composed of a thin film transistor of the active matrix circuit is formed. Note that in FIG. 7, thin film transistors 221-225, 226-23 connected in series to the pixel electrodes 213, 214.
0 corresponds to thin film transistors formed on the active layers 201 and 201, respectively.

In this embodiment, as shown in FIG. 5C, the capacitance line 206 is arranged so as not to overlap the pixel electrode 213 in the row but to overlap the pixel electrode 212 in the row above.
Therefore, a capacitor 215 corresponding to the auxiliary capacitor 126 in FIG. 2C can be formed between the capacitor line 207 and the pixel electrode 212. The same applies to the other rows.

In this way, by arranging the gate signal line and the pixel electrode one row above (or below) the row concerned, the circuit as shown in FIG.
The numeral 15 is formed on the capacitance line, and the capacitance can be added without substantially lowering the aperture ratio, which is effective in improving the degree of integration of the circuit.

In order to make the capacitance 215 larger, the interlayer insulating material 242 in this overlapping portion may be etched.
By doing so, the distance between the electrodes 207 and 213 can be reduced and the capacitance 215 can be increased. For that purpose, when the surface of the capacitance line 207 is covered with the anodic oxide 241, the anodic oxide 241 can function as a dielectric. Therefore, as shown in FIG. 6, the entire interlayer insulating film 242 on the surface of the anodic oxide 241 can be removed, which is preferable in that the capacitance 215 can be further increased.

Thus, the etching of the portion for the capacitance 215 does not increase the number of steps. That is, the interlayer insulator 241 is etched,
Contact holes 210, 211 or pixel electrode 21
Capacitor line 2 is formed at the same time when the contact hole 3 is formed.
A hole may be formed also on 07. What is shown in FIG. 6 is an example of the latter. Under proper etching conditions,
Since the aluminum anodic oxide 241 and the like are not etched at all (for example, dry etching conditions for etching silicon oxide), the etching can be continued until the opening of the contact hole is completed.

As shown in FIGS. 5D to 5F,
In the semiconductor region 216, the capacitance line 21 is formed in the same manner as in the above embodiment.
7. The gate signal line 218 is arranged, and the semiconductor region 21
The aperture ratio can be further improved by forming the image signal line 219 so as to cover all one side of No. 6. Figure 5
In the state of (F), the thin film transistor 22 shown in FIG.
Part of 1 and 224 and the pixel signal line 219 will overlap.

Further, as shown in FIG. 8A, the island-shaped semiconductor region 701 is bent more and more complicatedly.
As shown in (B), more transistors can be formed by overlapping the gate signal line 702 and the capacitor line 703 on the island-shaped semiconductor region 701. As a result, it becomes possible to further reduce the OFF current.

[Embodiment 4] This embodiment is based on FIG.
It is a modification of Example 3 which shows the manufacturing process in (C).
FIG. 10 shows an outline of this embodiment. 11 shows an equivalent circuit of the configuration shown in FIG. 10, and in FIG. 11, the same reference numerals as those in FIG. 10 indicate the same members. The configuration shown in FIG. 10 is characterized in that a thin film transistor group arranged in two adjacent pixels in the gate signal line direction has a common capacitance line.

As shown in FIG. 10, adjacent pixel electrodes 90
Gate signal lines 902 and 904 are arranged between the gate signal lines 5 and 906, and a capacitance line 903 is further arranged between the gate signal lines 902 and 904. One ends of the M-shaped island-shaped semiconductor regions 907 and 908 have pixel electrodes 905 and 90, respectively.
Connected to 6.

M-shaped island-shaped semiconductor regions 907 and 908
Is composed of a crystalline silicon film and constitutes an active layer of a thin film transistor. In the semiconductor regions 907 and 908, the thin film transistors 911 to 913 and 9 shown in FIG. 11 are formed in three regions where the gate signal lines 902 and 904 cross each other.
16 to 918 are formed, and these thin film transistors may be formed with an offset region and an LDD region as shown in Examples 1 and 2. On the other hand, the thin film transistor 91 shown in FIG.
4, 915, 919, and 920 are formed, and these thin film transistors function as capacitors.

In the present embodiment, a pair of pixel electrodes 90
Since one capacitance line 903 is commonly used for the pixels 5 and 906, the number of capacitance lines 903 can be halved, and the aperture ratio of the pixel can be increased. Although only the minimum configuration is shown in FIG. 10, in an actual liquid crystal display, a configuration in which the configurations shown in FIG. 10 are repeatedly combined in the number of several hundreds × several hundreds is adopted. .

[Embodiment 5] This embodiment relates to a structure obtained by further modifying the structure shown in FIG. FIG. 12 is a plan view showing the schematic configuration of this embodiment, and FIG.
The same reference numerals as 0 indicate the same members. The equivalent circuit of the configuration of FIG. 12 corresponds to FIG. The configuration shown in FIG. 12 is characterized by a common capacitance line 90 in two pixels.
3 is used, which is clear when compared with the configuration shown in FIG.

An equivalent circuit of the configuration of this embodiment is shown in FIG. That is, the equivalent circuit of the configuration shown in FIG. 12 is the same as that shown in FIG. By adopting the configuration as shown in this embodiment, the aperture ratio can be increased.

[Embodiment 6] This embodiment relates to a configuration obtained by further modifying the configuration shown in FIG. FIG. 13 shows a schematic configuration of this embodiment. In FIG. 13, the same reference numerals as those in FIG. 10 denote the same members, and the equivalent circuit of this embodiment is shown in FIG. When the structure of this embodiment is adopted, a high aperture ratio can be obtained.

[0072]

As described above, by connecting the gates of a plurality of thin film transistors to the gate signal line and the capacitance line as shown in the present invention, the voltage drop of the liquid crystal cell can be suppressed. In general, the deterioration of the thin film transistor depends on the voltage between the source and the drain, but in the present invention, the source / drain of the thin film transistors 122 and 123 of FIG.
The voltage between the drains is kept low during the whole driving process, and these thin film transistors 122, 123,
Since the LDD is formed in 124, deterioration can be prevented by utilizing the present invention.

The present invention is effective in applications in which higher image display is required. That is, in the case of expressing extremely delicate shades of 256 gradations or more, it is necessary to suppress the discharge of the liquid crystal cell to 1% or less during one frame. In the conventional method, neither of FIGS. 2A and 2B is suitable for this purpose.

The present invention is also suitable for an active matrix display device using a thin film transistor of a crystalline silicon semiconductor, which is particularly suitable for the purpose of displaying a matrix having a large number of rows. Generally, in a matrix having a large number of rows, the selection time per row is short, and therefore an amorphous silicon semiconductor thin film transistor is not suitable for use.

However, there is a problem that a thin film transistor using a crystalline silicon semiconductor has a large OFF current. Therefore, the present invention capable of reducing the OFF current can make a great contribution also in this field. Needless to say, the thin film transistor using an amorphous silicon semiconductor is also effective.

In the embodiments, the structure of the thin film transistor has been described centering on the top gate type.
It goes without saying that the effects of the present invention are invariable even if the structure is a bottom gate type or other structure. The present invention can obtain the maximum effect with the minimum change. Particularly in a top-gate type thin film transistor, the thin semiconductor region (active layer) has a complicated shape, while the gate electrode and the like have an extremely simple shape, so that disconnection of the upper wiring can be prevented. On the contrary, if the gate electrode has a complicated shape, it will be a cause of lowering the aperture ratio. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

FIG. 1 shows an arrangement example of a semiconductor region, a gate signal line, and a capacitance line of the present invention.

FIG. 2 is a schematic diagram of conventional and present invention active matrix circuits.

FIG. 3 shows a manufacturing process (cross section) of the switching element in the first embodiment.

FIG. 4 shows a manufacturing process (cross section) of a switching element according to a second embodiment.

FIG. 5 shows a manufacturing process (upper surface) of a switching element according to a third embodiment.

FIG. 6 shows a cross-sectional view of a switching element according to a third embodiment.

FIG. 7 shows a circuit diagram of a switching element according to a third embodiment.

FIG. 8 shows an arrangement example of a semiconductor region, a gate signal line, and a capacitance line of Example 3.

FIG. 9 shows an arrangement example of a gate signal line, a capacitance line and the like and peripheral circuits according to the third embodiment.

FIG. 10 shows a schematic state of the pixel region of Example 4 as viewed from above.

FIG. 11 shows an equivalent circuit of the configuration shown in FIG.

FIG. 12 shows a schematic state of the pixel region of Example 5 as viewed from above.

FIG. 13 shows a schematic state of the pixel region of Example 6 as viewed from above.

[Explanation of symbols]

100 ・ ・ ・ ・ Semiconductor area 121-125 ... Thin film transistor 126 .... Auxiliary capacity 127 ... Pixel cell 128 --- Gate signal line 129 ... Image signal line 130 ... Capacitance line 201, 202 ... Active layer 203-205 ... Gate signal line 206-209 ... Capacitance line 209 ... Image signal line 210, 211 ... Contact holes 212-214 ... Pixel electrodes 215 ... Capacity 221-230 ... Thin film transistor 240 .... Gate insulating film 241 ... Anodic oxide 242 ..... Interlayer insulating film 243 .... passivation film 901 ... Image signal line 902, 904 ... Gate signal line 903 ... Capacitance line 905, 906 ... Pixel electrode 907, 908 ... Active layer

─────────────────────────────────────────────────── --Continued front page (56) References JP-A-6-216386 (JP, A) JP-A-5-166837 (JP, A) JP-A-6-333948 (JP, A) JP-A-62- 92370 (JP, A) JP 63-151083 (JP, A) JP 8-46204 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21 / 336 G02F 1/1368

Claims (3)

(57) [Claims] [1 claim: a plurality of image signal lines, and a plurality of gate signal lines disposed substantially perpendicular to the image signal line, and the capacitor line disposed parallel to one by one between the gate signal line, the Provided in the area surrounded by the gate signal line and the image signal line.
A pixel electrode, an active matrix display device having a switching element connected to each of said pixel electrodes, each of the switching element has one semiconductor film, the semiconductor film, the gate signal line When a region overlapping at least three <br/> plants, the capacitance line and has a region overlapping with at least two places, in a region overlapping with both end portions and the capacitance line of said semiconductor film
A high-concentration impurity region is provided in each contacting area .
Is the the semiconductor film is in a region overlapping with the gate signal line
LDD regions are provided in contact with each other, and the LDD regions are in contact with the high-concentration impurity regions.
The high-concentration impurities provided at the both ends of the semiconductor film.
The pixel electrode is connected to one of the areas and the image signal line is connected to the other
Active matrix display device characterized by being connected . 2.pluralImage signal line,A plurality of units arranged substantially perpendicular to the image signal line Gate Shin
Line No.One is arranged in parallel between the gate signal lines. capacity
Lines and,Provided in the area surrounded by the gate signal line and the image signal line.
Was A pixel electrode, The pixel electrodeTo each ofConnectionWas doneSwitching elementAnd
In an active matrix display device having The switching elementEach ofIs a semi-conductor with a roughly M shape
Has one body coat,The above The semiconductor film is With the gate signal lineAt least 3Overlapping areas, With the capacitance lineAt least two placesOverlapping areas, Does not overlap with the gate signal line and the capacitance lineHigh concentration
Pure areaWhen, The area overlapping the gate signal line and theHigh concentration impurity region
Placed between andAnd a low concentration impurity region, High-concentration impurity regions provided at both ends of the semiconductor film
The pixel electrode is connected to one side and the image signal line is connected to the other side
Has been Active matrix display characterized by
apparatus. 3. A plurality of image signal lines, and a plurality of gate signal lines disposed substantially perpendicular to the image signal line, and the capacitor line disposed parallel to one by one between the gate signal line, the Provided in the area surrounded by the gate signal line and the image signal line.
In an active matrix display device having a pixel electrode, a switching element arranged in connection with each of the pixel electrodes, each of the switching element has one semiconductor film in which the outline M-shape, At both ends of the semiconductor film, contact with the image signal line
A region having a gate and a contact with the pixel electrode.
A region is provided, and in the semiconductor film, a region having a contact with the image signal line, a region having a contact with the pixel electrode, and a region separated into four or more by the capacitance line and the gate signal line. the impurity imparting conductivity, respectively, N-type or P-type and contain a high concentration, the the semiconductor film is in a region overlapping with the gate signal line
An active matrix display device, wherein LDD regions are provided in contact with each other .