JPH05216065A - Liquid crystal display device and production thereof - Google Patents

Abstract

PURPOSE:To arbitrarily and effectively impart a capacity by providing capacitors formed by coating both of the front surfaces and flanks of a conductive base layer with conductive surface layers via dielectric layers. CONSTITUTION:The capacitors 4 are formed on the same substrate 1 as the substrate of field effect transistors(FETs) 2. These capacitors 4 are constituted of the conductive base layers 5 on the substrate 1 and the conductive surface layers 7 coating the base layers 5 via the dielectric layers 11. Not only the front surfaces but the flanks as well of the base layers 5 in particular are coated with the surface layers 7 via the dielectric layers 11. The capacity is constituted of both of the front surfaces and the flanks. The capacitors 4 act to increase the three-dimensional capacity in such a manner and the large capacity is obtd. even with the small size. The active matrix liquid crystal display device having the capacitors 4 is obtd. simply by adding an etching stage to ordinary production stages.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device using an FET (field effect transistor). More specifically, it relates to an increase in capacity in the liquid crystal display device.

[0002]

2. Description of the Related Art An active matrix liquid crystal display device using a FET drives a liquid crystal by turning on a FET of a selected pixel, accumulates electric charges by using the capacitance of the FET and the capacitance of the liquid crystal, and re-writes the data. Display is performed by holding with this electric charge until is written. Therefore, the FET
In addition, in order to hold a sufficient charge in the liquid crystal and obtain a clear display image with clear contrast, it is preferable that the pixel capacity provided by the FET and the liquid crystal is large.

On the other hand, the image signal to each pixel is written in the data line by the sample holder of the built-in data driver, and when the TFT of the selected pixel is turned on, the liquid crystal is driven to hold the charge in the pixel. It will be.
Therefore, when the capacity of the sample holder is small, it is difficult to obtain a clear image because the capacity for driving the liquid crystal to hold the electric charge necessary for the pixel is insufficient, so that the capacity of the sample holder is preferably large.

Conventionally, the pixel capacity is FE as described above.
It is obtained by T and liquid crystal. Also, as a means for increasing the capacity of the sample holder, it has been proposed to widen the width of the data line and make the capacity of the sample holder by the liquid crystal layer between the data line and the common electrode (Japanese Patent Laid-Open No. 62-62-62).
105122).

[0005]

However, in general, in an FET, when a semiconductor is regarded as an electrode, the MOS structure constitutes a parallel plate capacitor having a metal electrode and a semiconductor as both electrodes, and the capacitance is two-dimensionally. It is fixed. Therefore,
When trying to increase the capacity of the FET, it is inevitable that the FET
There is a problem that the size itself becomes large and it becomes difficult to obtain a high-definition and high-density image display device. Further, since the capacitance of the liquid crystal is two-dimensional, which is determined by the area of the region sandwiched between the upper and lower electrodes (common electrode and pixel electrode), there is a similar problem.

On the other hand, if the capacity of the sample holder is increased by increasing the width of the data line, the expansion of the width of the data line is limited, so that there is a problem that the capacity is not effectively increased.

The present invention has been made in view of such conventional problems, and an object thereof is to make it possible to effectively and effectively increase the capacitance of a liquid crystal display device.

[0008]

The means taken for this purpose in the invention of claim 1 will be described with reference to FIGS. 1 and 2. The side surface and the upper surface of the conductive base layer 5 are formed on the substrate 1 by the dielectric layer 11. The liquid crystal display device has the capacitor 4 covered with the conductive surface layer 7 via the.

The means taken in the invention of claim 9 will be described with reference to FIG. 3. The semiconductor layer 13 provided on the substrate 1 will be described.
To form the FET semiconductor portion 14 and the capacitor semiconductor portion 15 and then form the separation layer 23 around the FET semiconductor portion 14 and the capacitor semiconductor portion 15 to form the active layer of the FET 2. Forming 3
After that, the insulating layer 6 and the base layer 5 of the capacitor 4 and the dielectric layer 11 are formed by oxidation, and the gate 8 is formed on the insulating layer 6 on the upper surface of the active layer 3, and the upper surface of the base layer 5 made of the same material as the gate 8 and The FET 2 and the capacitor 4 are simultaneously formed by forming the surface layer 7 by covering the side surface from above the dielectric layer 11.

[0010]

The capacitor 4 of the present invention has the capacitance layer 5 thereof.
Since not only the upper surface but also the side surfaces have a three-dimensional capacity increasing action that brings capacity, the capacity can be greatly increased even with a small size. Further, an active matrix liquid crystal display device having the capacitors 4 can be easily obtained by adding an etching process to the conventional manufacturing process.

[0011]

1 and 2 are a sectional view and a plan view showing a first embodiment of the present invention, showing a FET 2 provided for each pixel of a liquid crystal display device and driving a liquid crystal of the pixel. , And a capacitor 4 for increasing the capacitance of the FET 2.

First, the FET 2 will be described.
T2 itself is the same as the conventional one, that is, the semiconductor active layer 3 on the substrate 1, the insulating layer 23 separating the active layer 3, and the gate 8 formed on the thin insulating layer 6 on the active layer 3. , A source 9 and a drain 10 which are connected to the active layer 3 with the gate 8 interposed therebetween.

On the other hand, on the same substrate 1 as the FET 2,
The capacitor 4 is formed. This capacitor 4 is
The conductive base layer 5 on the substrate 1 and the dielectric layer 11
And a conductive surface layer 7 which is covered by
In particular, not only the upper surface but also the side surface of the base layer 5 is covered with the surface layer 7 via the dielectric layer 11, and the upper surface and the side surface both constitute a capacitance.

In particular, as clearly shown in FIG.
The second drain 10 is connected to the base layer 5 of the capacitor 4. Further, the surface layer 7 of the capacitor 4 is the common wiring 1
2 allows an appropriate electric potential (usually ground) to be applied. The connection between the FET 2 and the capacitor 4, that is, the connection of the capacitor 4 to the pixel is opposite to the one shown in the figure, in which the drain 10 of the FET 2 is connected to the surface layer 7 of the capacitor 4 and the base layer 5 of the capacitor 4 is connected. It may be performed by connecting to the common wiring 12.

Therefore, when the FET2 is turned on, the electric charge is held in the capacitor 4 together with the FET2, the capacity of the pixel is increased, and a clear display image with clear contrast is easily obtained. ..

The capacitor 4 has a base layer 5, a dielectric layer 11 and a surface layer 7 as an active layer 3 of an FET 2, an insulating layer 6 and an insulating layer 6, respectively.
It is preferable to form the same material as that of the gate 8. By doing so, the capacitor 4 can be formed simultaneously with the formation of the FET 2.

Further explaining this forming method with reference to FIG.
As shown in (a), first, the semiconductor layer 13 is formed on the substrate 1.
To form. As the semiconductor layer 13, single crystal silicon, amorphous silicon, polysilicon, gallium-arsenic, or the like is generally used, but a single crystal material is preferable.
As the substrate 1, for example, an insulating material such as glass is used.

Next, as shown in (b), the semiconductor layer 13 is etched to form a semiconductor portion 14 for FET and a semiconductor portion 15 for capacitor. FET semiconductor part 1
Reference numeral 4 is a portion where the FET 2 is formed, and the capacitor semiconductor portion 15 is a portion where the capacitor 4 is formed.

Thereafter, as shown in (c), the surfaces of the FET semiconductor portion 14 and the capacitor semiconductor portion 15 obtained by etching are oxidized to form an oxide layer 16. The oxide layer 16 formed on the FET semiconductor portion 14 is F
It becomes the insulating layer 6 of ET2, and this insulating layer 6 is the oxide layer 1
The portion covered with 6 becomes the active layer 3 of the FET 2. Also,
The oxide layer 16 formed on the capacitor semiconductor portion 15 serves as the dielectric layer 11, and the portion covered by the oxide layer 16 serving as the dielectric layer 11 serves as the base layer 5 of the capacitor 4.

Further, as shown in (d), the gate 8 of the FET 2 is formed on the insulating layer 6 on the upper surface of the active layer 3. Polysilicon is generally used as the gate 8,
Other conductive materials may be used. At the same time, the side surface and the upper surface of the base layer 5 are covered with the same material as that of the gate 8 from above the dielectric layer 11 covering the surface thereof to form the surface layer 7 of the capacitor 4.

Not only the active layer 3 of the FET 2 but also the base layer 5 of the capacitor 4 is preferably made of a single crystal material. Particularly, when the active layer 2 of the FET 2 and the base layer 5 of the capacitor 4 are made of single crystal silicon, it is easily performed by forming the single crystal silicon layer using a temporary substrate of porous silicon obtained by making the single crystal silicon porous. be able to.
According to observation with a transmission microscope, the provisional substrate of porous silicon has pores of about 600 Å on average, and its density is less than half that of single crystal silicon. Single crystallinity is maintained, and it is also possible to epitaxially grow single crystal silicon on top of the porous layer. However, at 1000 ° C. or higher, rearrangement of internal holes occurs, and the characteristics of enhanced etching are impaired. Therefore, for epitaxial growth of the silicon layer,
Molecular beam epitaxial growth method, plasma CVD method, thermal C
Low temperature growth such as VD method, photo CVD method, bias sputtering method, liquid crystal growth method and the like is preferable.

Here, a method for epitaxially growing a single crystal layer after making P-type silicon porous will be described.

First, a temporary silicon single crystal substrate is prepared, and this is made porous by an anodization method using an HF solution.

The density of single crystal silicon is 2.33 g / cm.
² , the density of the porous silicon is 0.6-1.1 g / c by changing the concentration of the HF solution to 20-50%.
It can be changed to m ² . The porous layer is easily formed on the P-type silicon temporary substrate for the following reason.

Porous silicon was discovered in 1956 in the course of research on electropolishing of semiconductors. Further, it has been reported from the research on the dissolution reaction of silicon in the anodization that holes are necessary for the anodic reaction of silicon in the HF solution, and the reaction is as follows.

Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + ne ⁻ SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4-λ) e ⁺ → SiF ₄ + 4H ⁺ + λe _{^{- SiF 4 + 2HF → H 2}} SiF 6 where e ^+, e ^- represent respectively a hole and an electron.
Further, n and λ are the numbers of holes required for dissolving one atom of Si, respectively, and porous silicon is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, it can be said that P-type silicon in which holes are present is likely to be made porous. The selectivity in this porosification is a matter already demonstrated.

On the other hand, it has been reported that high-concentration N-type silicon can also be made porous. Therefore, porosity can be achieved regardless of whether it is P-type or N-type.

Further, since the porous layer has a large amount of voids formed therein, the density thereof is reduced to less than half.
As a result, the surface area is drastically increased compared to the volume, so that the chemical etching rate is significantly increased as compared with the etching rate of a normal single crystal layer.

An example of conditions for making single crystal silicon porous by anodization is shown below. The starting material of the porous silicon formed by anodization is not limited to single crystal silicon, but silicon of other crystal structure may be used.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ^-2 ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1:
1: 1 time: 2.4 (hour) Thickness of porous silicon: 300 (μm) Porosity: 56% Single crystal silicon thin film obtained by epitaxially growing silicon on the temporary substrate of porous silicon thus formed. To form. The thickness of the single crystal silicon thin film is preferably 50 μm or less, more preferably 20 μm or less.

Next, the surface of the single crystal silicon is attached to the substrate. This bonding is preferably performed after oxidizing the surface of the single crystal silicon. This is because, for example, when a glass plate is used as the substrate, the interface level generated by the underlying interface of the silicon active layer can be lower in the oxide film interface than in the glass interface, and the characteristics of the electronic device are significantly reduced. This is because it can be improved. Also,
It is also possible to bond only the thin film of single crystal silicon obtained by etching away the temporary substrate of porous silicon by selective etching described later to the substrate.

The bonding is performed by simply contacting each surface at room temperature after cleaning, and by Van den Waals force,
It can be adhered so that it cannot be easily peeled off, but this is further 200 to 900 ° C., preferably 600
It is preferable to heat-treat at a temperature of up to 900 ° C. in a nitrogen atmosphere to completely bond them.

Si is formed on the temporary substrate and the entire substrate that are bonded together.
_{A 3} N ₄ layer is deposited as an etching preventive film, and only the Si ₃ N ₄ layer on the surface of the temporary substrate of porous silicon is removed. Apizone wax may be used instead of the Si ₃ N ₄ layer.

Thereafter, the temporary substrate made of porous silicon is entirely removed by means such as etching to obtain a substrate having a single crystal silicon layer.

The selective etching method for electroless wet etching only the temporary substrate of porous silicon will be described below.

As an etching solution which does not have an etching effect on crystalline silicon and can selectively etch only porous silicon, hydrofluoric acid and ammonium fluoride (NH
₄ F) or buffered hydrofluoric acid such as hydrogen fluoride (HF), hydrofluoric acid containing hydrogen peroxide or a mixed solution of buffered hydrofluoric acid, hydrofluoric acid containing alcohol or a mixed solution of buffered hydrofluoric acid, A mixed solution of hydrofluoric acid or buffered hydrofluoric acid to which hydrogen peroxide solution and alcohol are added is preferably used. Etching is performed by moistening a temporary substrate on which a single crystal silicon layer is formed or a laminate of the temporary substrate and the substrate in these solutions.

The etching rate depends on the solution concentration and temperature of hydrofluoric acid, buffered hydrofluoric acid and hydrogen peroxide solution. By adding hydrogen peroxide solution, the oxidation of silicon can be accelerated, and the reaction rate can be increased as compared with the case of no addition.
Further, the reaction rate can be controlled by changing the ratio of the hydrogen peroxide solution. Further, by adding alcohol, the bubbles of the reaction product gas due to the etching can be instantaneously stirred and removed from the etching surface, and the porous silicon can be uniformly and efficiently etched.

The HF concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 1 to 85% by weight, still more preferably 1 to 70% by weight with respect to the etching solution. The NH ₄ concentration in the buffered hydrofluoric acid is preferably 1 to 95% by weight with respect to the etching solution,
More preferably 5 to 90% by weight, still more preferably 5 to 8
It is set in the range of 0% by weight.

The HF concentration is preferably 1 to 95% by weight, more preferably 5 to 90% by weight, based on the etching solution.
More preferably, it is set in the range of 5 to 80% by weight.

The H ₂ O ₂ concentration is preferably 1 to 95% by weight, more preferably 5 to 90% by weight, still more preferably 10 to 80% by weight, based on the etching solution, to achieve the above effect of the hydrogen peroxide solution. It is set within the playing range.

The alcohol concentration is preferably 80% by weight or less, more preferably 60% by weight, based on the etching solution.
Hereafter, it is more preferably set to 40% by weight or less and within the range in which the effect of the above alcohol is exhibited. It should be noted that the alcohol may be ethyl alcohol, isopropyl alcohol, or the like as long as it has no practical problem in the production process and the effect of adding the alcohol can be expected.

The temperature is preferably set in the range of 0 to 100 ° C, more preferably 5 to 80 ° C, further preferably 5 to 60 ° C.

The semiconductor substrate thus obtained has a single-crystal silicon flattened and uniformly thinned over the entire surface of the substrate, similar to an ordinary silicon wafer. Therefore, using a substrate having this single crystal silicon,
By forming the FET and the capacitor in the same manner as described above, it is possible to easily obtain the FET including the active layer of single crystal silicon and the capacitor including the base layer of single crystal silicon. In particular, when the capacitor is formed by connecting to the data line between the data driver and the display unit as in the embodiment described later, this capacitor is connected to the F of the display unit.
There is an advantage that it can be simultaneously formed on the same substrate as ET and using single crystal silicon.

FIG. 4 shows a second embodiment of the present invention, in which 17 is a pixel electrode, 18 is a data line, 19 is a gate line, and the same reference numerals as those in FIGS. 1 and 2 represent the same members. It is a thing.

In this embodiment, the capacitor 4 is arranged in the peripheral portion of the pixel, the base layer 5 of the capacitor 4 is connected to the common wiring 12, and the surface layer 7 of the capacitor 4 is connected to the pixel electrode 17.

FIG. 5 shows an equivalent circuit of the pixel portion in the active matrix liquid crystal display device which does not have the capacitor 4 at the peripheral portion of the pixel, and FIG. 6 shows the equivalent circuit of this embodiment shown in FIG. In FIG. 5, C ₁ and C ₃ are capacitors around the pixel, C ₂ and C ₄ are capacitors near the center of the pixel, and C
You can see that ₁ is easily shaken. On the other hand, in the case of the present embodiment in which a large capacitance C ₀ is formed around the pixel by the capacitor 4, both C ₁ and C ₂ are less likely to be shaken due to the presence of C ₀ , and a clear image with clear contrast can be easily obtained. I understand.

FIG. 7 and FIG. 8 show a third embodiment of the present invention, in which the base layer 5 of the capacitor 4 is formed in a comb shape and the tooth portions thereof are arranged close to each other. ing. In this way, the gap between the base layers 5 covered with the dielectric layer 11 is filled with the surface layer 7, the upper surface can be planarized, and high integration can be achieved.

The spacing between the base layers 5 covered with the dielectric layer 11 is
When the formation thickness of the surface layer 7 is d, it is preferably 2d or less in order to obtain flatness of the upper surface.

9 and 10 show a fourth embodiment of the present invention, in which a dielectric layer 11 is interposed between the base layer 5 and the surface layer 7 on the base layer 5 side and the surface layer 7 side, respectively. To form a capacitor 4 by providing a conductive intermediate layer 20,
The base layer 5 and the surface layer 7 are connected and have the same potential. By doing so, the capacitance of the capacitor 4 can be further increased. In addition, in the illustrated example, one intermediate layer 2
Although it is 0, the intermediate layer 20 may be composed of two or more layers.

FIG. 11 and FIG. 12 show a fifth embodiment of the present invention. In a liquid crystal display device having a data driver 21 incorporated therein, a capacitor 4 is provided and a data line between the data driver 21 and the display unit 22 is provided. It is formed by connecting to 18. To explain further, the base layer 5 of the capacitor 4 in this embodiment is connected to the data line 18, and the surface layer 7 of the capacitor 4 is connected to the common wiring 12.

When such a capacitor 4 is provided, the capacity of the sample holder of the data driver 21 is increased, and as a result, a clear image with clear contrast can be easily obtained.

In the above embodiments, an oxide film is formed on the surface of the semiconductor layer and a conductive film is attached on the oxide film to form a capacitor. For example, a metal such as Ta is formed in an island shape and the surface is formed. A three-dimensional effect can be expected even if a capacitor is formed by oxidizing or attaching an insulating film and further forming a conductive film.

[0054]

As described above, according to the present invention, the capacity of the liquid crystal display device can be arbitrarily and effectively increased, and as a result, a clear display image with clear contrast can be obtained. Further, the formation of the capacitor 4 for obtaining this capacitance can be performed only by adding an etching process to the conventional manufacturing process of the liquid crystal display device.

[Brief description of drawings]

1 is a cross-sectional view taken along the line AA of FIG.

FIG. 2 is a plan view showing a first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing method of the present invention.

FIG. 4 is a plan view showing a second embodiment of the present invention.

FIG. 5 is an equivalent circuit in the case where a capacitor is not provided in the peripheral portion of a pixel.

FIG. 6 is an equivalent circuit of the second embodiment of the present invention.

FIG. 7 is a plan view of the third embodiment of the present invention.

8 is a sectional view taken along line BB of FIG.

FIG. 9 is a plan view showing a fourth embodiment of the present invention.

10 is a sectional view taken along line CC of FIG.

FIG. 11 is a plan view showing a fifth embodiment of the present invention.

FIG. 12 is an enlarged view of the vicinity of the capacitor of FIG.

[Explanation of symbols]

 1 Substrate 2 FET 3 Active Layer 4 Capacitor 5 Base Layer 6 Insulating Layer 7 Surface Layer 8 Gate 9 Source 10 Drain 11 Dielectric Layer 12 Common Wiring 13 Semiconductor Layer 14 FET Semiconductor Part 15 Capacitor Semiconductor Part 16 Oxide Layer 17 Pixel Electrode 18 Data Line 19 Gate line 20 Intermediate layer 21 Data driver 22 Display section 23 FET separation section 24 Drain wiring 25 Source wiring

Claims (10)

[Claims] 1. A liquid crystal display device comprising a substrate, and a capacitor having a side surface and an upper surface of a conductive base layer covered with a conductive surface layer via a dielectric layer. 2. The liquid crystal display device according to claim 1, wherein the capacitance of the pixel is increased by connecting the capacitor to the pixel electrode. 3. The liquid crystal display device according to claim 2, wherein the capacitor is formed on the periphery of the pixel. 4. The liquid crystal display device according to claim 1, wherein the base layer of the capacitor is formed in a comb shape. 5. A liquid crystal display device, wherein the materials of the base layer, dielectric layer and surface layer of the capacitor are the same as those of the active layer, insulating layer and gate of the FET, respectively. 6. The liquid crystal according to claim 1, wherein the capacitor has a conductive intermediate layer between the base layer and the surface layer, with a dielectric layer interposed between the base layer side and the surface layer side. Display device. 7. The sample holder capacitance of the data driver is increased by incorporating the data driver and forming the capacitor by connecting to the data line between the data driver and the display portion. The liquid crystal display device according to claim 1, 4, 5, or 6. 8. The liquid crystal display device according to claim 1, wherein the active layer of the FET and the base layer of the capacitor are made of single crystal silicon. 9. A semiconductor layer provided on a substrate is etched to form a semiconductor portion for a FET and a semiconductor portion for a capacitor, the active layer of the FET portion is separated, and then the active layer of the FET is formed. By forming an oxide layer around the upper surface and the semiconductor part for capacitors, a gate insulating layer, a base layer and a dielectric layer of the capacitor are formed, and a gate is further formed on the gate insulating layer, and a base layer made of the same material as this gate is formed. A method for manufacturing a liquid crystal display device, characterized in that an FET and a capacitor are simultaneously formed by forming a surface layer by covering an upper surface and a side surface from above the dielectric layer. 10. A substrate is obtained by epitaxially generating silicon on a porous silicon temporary substrate to form a single crystal silicon layer, bonding the single crystal silicon layer side to the substrate, and then removing the temporary substrate by etching. A single crystal silicon layer is provided on the FET
10. The method for manufacturing a liquid crystal display device according to claim 9, wherein a semiconductor part for capacitors and a semiconductor part for capacitors are formed.