JPS6390859A - Thin film transistor and manufacture thereof - Google Patents
Thin film transistor and manufacture thereofInfo
- Publication number
- JPS6390859A JPS6390859A JP61236217A JP23621786A JPS6390859A JP S6390859 A JPS6390859 A JP S6390859A JP 61236217 A JP61236217 A JP 61236217A JP 23621786 A JP23621786 A JP 23621786A JP S6390859 A JPS6390859 A JP S6390859A
- Authority
- JP
- Japan
- Prior art keywords
- source
- crystal
- substrate
- layer
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000002955 isolation Methods 0.000 claims description 18
- 239000010408 film Substances 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 3
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 10
- 238000009413 insulation Methods 0.000 abstract 5
- 239000010410 layer Substances 0.000 description 26
- 230000002093 peripheral effect Effects 0.000 description 5
- 239000011241 protective layer Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 239000003082 abrasive agent Substances 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体薄膜、特に単結晶Ｓｉを用いた液晶ディ
スプレイ等を駆動する薄膜トランジスタ及びその製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor thin film, particularly a thin film transistor for driving a liquid crystal display using single crystal Si, and a method for manufacturing the same.
近年、液晶フラットパネルディスプレイ、エレクトロル
ミセンスディスプレイ等の駆動デバイスとして使われる
薄膜トランジスタの研究開発が盛んに行われている。こ
の薄膜トランジスタに要求されていることは、
（１）透明絶縁性基板上に形成できること、（２）ＯＮ
電流が太きくＯＦＦ電流が十分小さいこと、
（３）大容量のトランジスタアレイが形成できるプロセ
スが可能なこと、
等があげられており、半導体薄膜として多結晶Ｓｉやア
モルファスＳｉを用いた薄膜トランジスタが研究開発さ
れている。ところが、多結晶ＳｉやアモルファスＳｉの
キャリア移動度は１〜２０ｃｒｉ／■・ｓｅｃと比較的
小さいため、この薄膜トランジスタを駆動させるための
周辺駆動ＩＣが必要となる。そのため、大容量の薄膜ト
ランジスタアレイと周辺駆動ＩＣとの端子接続が必要に
なり、装置の大型化、高コスト化、低信頼化をもたらし
てきた。In recent years, research and development has been actively conducted on thin film transistors used as driving devices for liquid crystal flat panel displays, electroluminescent displays, and the like. This thin film transistor is required to (1) be formed on a transparent insulating substrate, (2) ON
Thin film transistors using polycrystalline Si or amorphous Si as semiconductor thin films are being researched because of the following characteristics: (3) the ability to process large-capacity transistor arrays; being developed. However, since the carrier mobility of polycrystalline Si or amorphous Si is relatively small at 1 to 20 cr/sec., a peripheral driving IC is required to drive this thin film transistor. Therefore, a terminal connection between a large-capacity thin film transistor array and a peripheral drive IC has become necessary, leading to an increase in the size, cost, and reliability of the device.
一方、単結晶Ｓｉはトランジスタとしての前述の条件（
２）、 （３）の要求を満足し、移動度も高いため、
周辺駆動回路もトランジスタアレイ形成時に同時に同一
基板上に形成でき、周辺駆動回路との端子接続が不要に
なる利点が有る。第３図に単結晶Ｓｉを用いた液晶ディ
スプレイ用トランジスタの構造を示す〔たとえば、ササ
エティ オブ インフォーメーション ディスプレイ、
ダイジェスト オブ テクニカル ペイパー（Ｓｏｃｉ
ｅｔｙｏｆ Ｉｎｆｏｒｍａｔｉｏｎ Ｄｉｓｐｌａｙ
、Ｄｉｇｅｓｔ ｏｆ ＴｅｃｈｎｉｃａｌＰａｐａｒ
） 、 ｐ１５０−ｐ１５１．１９８３ ） 、図中、
１４はＳｉ基板、１５は素子分離用Ｓｉ層、７はドレイ
ン領域、８はソース領域、５は絶縁保護層、４はゲート
電極、１０はドレイン電極、１１はソース電極である。On the other hand, single-crystal Si can be used as a transistor under the above-mentioned conditions (
Since it satisfies the requirements of 2) and (3) and has high mobility,
The peripheral drive circuit can also be formed on the same substrate at the same time as the transistor array is formed, which has the advantage of eliminating the need for terminal connections with the peripheral drive circuit. Figure 3 shows the structure of a transistor for a liquid crystal display using single-crystal Si [for example, a society of information displays,
Digest of Technical Paper (Soci
etyof Information Display
, Digest of Technical Paper
), p150-p151.1983), in the figure,
14 is a Si substrate, 15 is a Si layer for element isolation, 7 is a drain region, 8 is a source region, 5 is an insulating protection layer, 4 is a gate electrode, 10 is a drain electrode, and 11 is a source electrode.
第３図に示した単結晶Ｓｉを用いた液晶ディスプレイ用
トランジスタは、基板として不透明の単結晶Ｓｉを使用
しているため、基板を透過する光を使う液晶ディスプレ
イには不適当であった。The liquid crystal display transistor using single-crystal Si shown in FIG. 3 uses opaque single-crystal Si as a substrate, and therefore is not suitable for a liquid crystal display that uses light that passes through the substrate.
一方、単結晶Ｓｉを薄膜化する技術としては、デバイス
基板を支持基板に張付けた後、研磨加工して薄膜化し、
再度所望の店仮に張付ける転写技術が知られており、３
次元ＩＣに応用されている〔ジャパニーズ ジャーナル
オブ アプライドフィジンクス（Ｊｐｎ、Ｊ、Ａｐｐ
ｌ、Ｐｈｙｓ、）２３． Ｌ８１５〜８１７゜１９８４
）。しかし、この技術は薄＜シたデバイスを所望の基板
に張付ける工程が必要であるため、工程が複雑で、歩留
り低下の原因であった。On the other hand, the technology for thinning single-crystal Si is to attach a device substrate to a supporting substrate and then polish it to make it thin.
A transfer technique is known in which the desired location is pasted again, and 3
Applied to dimensional IC [Japanese Journal of Applied Physics (Jpn, J, App
l, Phys, )23. L815-817゜1984
). However, this technique requires a step of attaching a thin device to a desired substrate, which makes the process complicated and causes a decrease in yield.
本発明の目的は、単結晶Ｓｉを薄膜化する技術を用い、
液晶ディスプレイに適した簡単なプロセスを存する薄膜
トランジスタの構造とその製造方法を堤供することにあ
る。The purpose of the present invention is to use technology to thin single crystal Si,
The object of the present invention is to provide a structure of a thin film transistor and a method for manufacturing the same, which has a simple process suitable for liquid crystal displays.
第１の本発明は、絶縁性基板上に設けられた薄膜トラン
ジスタにおいて、素子分離用絶縁層と、ソース、ドレイ
ン領域を有し前記素子分離用絶縁層と同一面内に設けら
れた島状の単結晶Ｓｉ部と、前記絶縁性基板と前記単結
晶Ｓｉ部との間に設けられたゲート絶縁膜１ゲート電極
、接着絶縁層と、前記島状の単結晶Ｓｉ部に対して前記
ゲート電極と反対側にソース、ドレイン領域と電気的に
接触せしめるように設けられたソース、ドレイン電極と
を有することを特徴としている。A first aspect of the present invention provides a thin film transistor provided on an insulating substrate, which includes an insulating layer for element isolation, and an island-shaped unit having source and drain regions and provided in the same plane as the insulating layer for element isolation. A gate insulating film 1 provided between a crystalline Si portion, the insulating substrate and the single crystal Si portion, a gate electrode, an adhesive insulating layer, and a gate electrode opposite to the gate electrode with respect to the island-shaped single crystal Si portion. It is characterized by having source and drain electrodes provided on the sides so as to be in electrical contact with the source and drain regions.
第２の本発明は、Ｓｉ基板上に素子分離用絶縁層を形成
する工程と、前記素子分離用絶縁層を部分的に除去して
絶縁層の窓を形成する工程と、形成された窓部分に島状
の単結晶Ｓｉ層を選択的に形成する工程と、前記島状の
単結晶ＳｉＦにこの層の厚さ以上の厚さを持つソース、
ドレイン領域を有するトランジスタを形成する工程と、
形成されたトランジスタ側に絶縁性基板を接着する工程
と、前記絶縁性基板の反対側から前記Ｓｉ基板を研磨加
工して前記素子分離用絶縁層と前記トランジスタを残し
て薄膜化する工程と、前記ソース。A second aspect of the present invention includes a step of forming an insulating layer for element isolation on a Si substrate, a step of partially removing the insulating layer for element isolation to form a window in the insulating layer, and a step of forming a window in the insulating layer. selectively forming an island-shaped single-crystal Si layer on the island-shaped single-crystal SiF layer;
forming a transistor having a drain region;
a step of adhering an insulating substrate to the side of the formed transistor; a step of polishing the Si substrate from the opposite side of the insulating substrate to leave the element isolation insulating layer and the transistor and thinning the Si substrate; sauce.
ドレイン領域と電気的接触せしめるようにソース。The source makes electrical contact with the drain region.
ドレイン電極を形成する工程とを含むことを特徴として
いる。The method is characterized in that it includes a step of forming a drain electrode.
第１の発明の薄膜トランジスタの構造を、第１図（ａ）
、 ｆｂ）に示す。（ａ）は断面図、（ｂ）は平面図で
ある。The structure of the thin film transistor of the first invention is shown in FIG. 1(a).
, fb). (a) is a sectional view, and (b) is a plan view.
３■々トランジスタが形成される単結晶Ｓ ｉ Ｆｉ
６及びドレイン、ソース領域７，８は素子分離用絶縁層
９と同一面内に形成されている。また、透明電極からな
る絵素電極１３はソース領域８と電気的にる。更にデバ
イス全体が透明接着材２によって透明絶縁性基板１に接
着されているため、透明絶縁性基板１から入射した光は
吸収がほとんどなく絵素電極１３に到達するため、透過
型液晶ディスプレイとして最適な構造である。Single crystal Si Fi in which 3 transistors are formed
6 and drain and source regions 7 and 8 are formed in the same plane as the element isolation insulating layer 9. Further, the picture element electrode 13 made of a transparent electrode is electrically connected to the source region 8. Furthermore, since the entire device is bonded to the transparent insulating substrate 1 with the transparent adhesive 2, the light incident from the transparent insulating substrate 1 reaches the pixel electrode 13 with almost no absorption, making it ideal for use as a transmissive liquid crystal display. It has a unique structure.
第２の発明である薄膜トランジスタの製造方法を、第２
図（ａ）〜（ｆ）に示す。Ｓｉ基板１４上に島状に窓が
あけられた素子分離用絶縁層９を形成し、島状の窓部に
単結晶Ｓｉ層６を選択的に形成する（第２図（ａ））。The method for manufacturing a thin film transistor, which is the second invention, is
Shown in Figures (a) to (f). An insulating layer 9 for element isolation having an island-shaped window is formed on the Si substrate 14, and a single-crystal Si layer 6 is selectively formed in the island-shaped window portion (FIG. 2(a)).
続いて通常のＭＯＳプロセスに従いＭＯＳＦＥＴを形成
する（第２図（ｂ））。このとき、ソース、ドレイン領
域８．７は通常イオン注入や不純物拡散等でつくられる
が、ソース、ドレイン領域の深さは素子分離用絶縁層９
や単結晶Ｓｉ層６とほぼ同じであるか深いように形成す
る。Subsequently, a MOSFET is formed according to a normal MOS process (FIG. 2(b)). At this time, the source and drain regions 8.7 are usually formed by ion implantation, impurity diffusion, etc., but the depth of the source and drain regions is determined by the element isolation insulating layer 9.
It is formed to have a depth that is approximately the same as or deeper than the single crystal Si layer 6.
これにより絶縁性基板１に張付けて化学研磨によりＳｉ
基板１４を除去した後、ドレイン、ソース領域が表面に
現れるようになる（第２図（ｄ））。その後、ドレイン
、ソース領域７，８と電気的接触せしめるようにドレイ
ン、ソース電極１０．１１を形成する（第２図（ｆ））
事により、簡単なプロセスで逆スタガード構造の単結晶
Ｓｉ薄膜トランジスタが形成される。この工程から分る
ように、従来の技術で行われた２回のデバイス転写が本
発明では１回で良くプロセスが簡単になっている。また
、ドレイン配線とゲート配線が比較的厚い素子分離用絶
縁膜によって簡単に多層配線されており、電極間の短絡
等の画素欠陥の恐れの少ない薄膜トランジスタアレイが
得られる。As a result, it is attached to the insulating substrate 1 and the Si is bonded by chemical polishing.
After removing the substrate 14, drain and source regions appear on the surface (FIG. 2(d)). Thereafter, drain and source electrodes 10 and 11 are formed so as to be in electrical contact with the drain and source regions 7 and 8 (FIG. 2(f)).
As a result, a single-crystal Si thin film transistor with an inverted staggered structure can be formed by a simple process. As can be seen from this step, in the present invention, device transfer is performed only once, instead of twice in the conventional technique, simplifying the process. In addition, the drain wiring and gate wiring are easily multilayered by using a relatively thick insulating film for element isolation, and a thin film transistor array can be obtained with less risk of pixel defects such as short circuits between electrodes.
本発明の実施例を図面を用いて説明する。 Embodiments of the present invention will be described using the drawings.
第１図は第１の発明の一実施例を示す断面図及び平面図
である。また第２図（ａ）〜（「）は第２の発明の薄膜
トランジスタの製造方法の一実施例を示す。FIG. 1 is a sectional view and a plan view showing an embodiment of the first invention. FIGS. 2(a) to 2(a) show an embodiment of the method for manufacturing a thin film transistor according to the second invention.
各製造工程での断面図である。なお、第２図に示す製造
方法は、第１図に示す薄膜トランジスタの製造方法を示
すものである。It is a sectional view in each manufacturing process. Note that the manufacturing method shown in FIG. 2 is a method for manufacturing the thin film transistor shown in FIG. 1.
第２図において、ｐ型Ｓｉ基板１４に素子分離用絶縁層
９として熱酸化膜を０．７ μｍ形成し、ドライエツチ
ング加工により島状の窓を形成する。この島状の窓部分
にＳ ｉＨｚ Ｃ（！ｚ Ｈ２ＨＣＩＣ方形を用いて
単結晶Ｓｉ層６を選択的に形成する（第２図（ａ））。In FIG. 2, a thermal oxide film with a thickness of 0.7 μm is formed as an element isolation insulating layer 9 on a p-type Si substrate 14, and an island-shaped window is formed by dry etching. A single-crystal Si layer 6 is selectively formed in this island-shaped window portion using a SiHz C (!z H2HCIC square) (FIG. 2(a)).
続いて、ゲート絶縁膜３として熱酸化膜を０．２μｍ形
成し、さらに１００ｋＶの加速電圧で５ＸＩＯＩ５ｃｍ
−”のほう素をマスクを用いて単結晶Ｓｉ層６に注入し
、９５０℃、１５０分間アニールして、約１μｍの深さ
にほう素を拡散しソース、ドレイン領域８，７を形成す
る。さらにゲート電極４として／ｌを０．３μｍ形成し
パターニングする。その後、第１の絶縁保護層５として
、ＣＶＤを用いて５ｉｎ２を０．６ ｐｍ形成し、ＭＯ
ＳＦＥＴが形成される（第２図（ｂ））。Subsequently, a thermal oxide film with a thickness of 0.2 μm was formed as the gate insulating film 3, and a 5×IOI of 5 cm was further formed at an accelerating voltage of 100 kV.
-'' boron is implanted into the single crystal Si layer 6 using a mask, and annealed at 950° C. for 150 minutes to diffuse boron to a depth of about 1 μm to form source and drain regions 8 and 7. Further, a gate electrode 4 of 0.3 μm /l is formed and patterned. Thereafter, a first insulating protective layer 5 of 5 in 2 is formed with a thickness of 0.6 pm using CVD, and MO
A SFET is formed (FIG. 2(b)).
更に絶縁性基板１上に透明接着材２（たとえばエポキシ
樹脂）を用いてＭＯＳ Ｆ ＥＴが形成されたＳｉ基板
を、ゲート電極４側が絶縁性基板１と貼り合わせられる
ように接着する（第２図（Ｃ））。Furthermore, the Si substrate on which the MOS FET is formed is bonded onto the insulating substrate 1 using a transparent adhesive 2 (e.g., epoxy resin) so that the gate electrode 4 side is bonded to the insulating substrate 1 (see FIG. 2). (C)).
この後、Ｓｉ基板１４は化学研磨を用いて除去、薄膜化
する（第２図（ｄ））。化学研摩時の研だ材としては０
．０２μｍ径の石英粒と有機アンモニアを用いた。これ
により、Ｓｉ結晶の方が絶縁層９よりも約１０倍研磨ス
ピードが速くなり、絶縁Ｎ９の厚さで自動的に研摩が終
了する。さらに、スパッタ法を用いて第２の絶縁保護層
１２としてＳｉｎｇを１５００人形成し、コンタクトホ
ールを開ける（第２図（ｅ））。Thereafter, the Si substrate 14 is removed and thinned using chemical polishing (FIG. 2(d)). 0 as an abrasive material during chemical polishing
．． Quartz grains with a diameter of 0.02 μm and organic ammonia were used. As a result, the polishing speed of the Si crystal becomes about 10 times faster than that of the insulating layer 9, and the polishing automatically ends when the thickness of the insulating layer N9 is reached. Furthermore, 1,500 layers of Sing are formed as the second insulating protective layer 12 using a sputtering method, and contact holes are opened (FIG. 2(e)).
その後、ドレイン、ソース電極１０．１１としてＡｌを
０．３ μｍ形成し、ドレイン、ソース領域７゜８と電
気的に接続されるようにパターニング形成する。更に、
液晶ディスプレイ用薄膜トランジスタアレイを形成する
場合には、ソース電極１１と接続されるように透明電極
として酸化インジウム銭（ＩＴＯ）をスパッタ法で１０
００人形成し、パターニングして絵素電極１３を形成し
、ディスプレイ用薄膜トランジスタが完成される（第２
図（ｆ））。第１図は、以上のようにして製造された薄
膜トランジスタを示している６
なお、本実施例においてはＡＮゲー）ｐＭＯ３ＦＥＴが
形成されているが、多結晶Ｓｉゲートを用いたＦＥＴや
ｎＭＯ３ＦＥＴでも本発明は有効である。また、本実施
例においては第１．第２の絶縁保護層５，１２は信頼性
向上のため形成しであるが、必ずしも必要なものではな
い。Thereafter, Al is formed to a thickness of 0.3 .mu.m as drain and source electrodes 10.11, and patterned to be electrically connected to the drain and source regions 7.8. Furthermore,
When forming a thin film transistor array for a liquid crystal display, 100% of indium oxide (ITO) is sputtered as a transparent electrode so as to be connected to the source electrode 11.
The thin film transistor for display is completed by patterning and forming the pixel electrode 13.
Figure (f)). FIG. 1 shows a thin film transistor manufactured as described above6. Note that in this example, a pMO3FET (AN gate) is formed, but an FET using a polycrystalline Si gate or an nMO3FET can also be used according to the present invention. is valid. Moreover, in this embodiment, the first. The second insulating protective layers 5 and 12 are formed to improve reliability, but are not necessarily required.
本発明による薄膜トランジスタの特性を調べた結果、９
ＭＯ３薄膜トランジスタで、移動度〜２００ｃＩａ／ｖ
−５ｅｃ 、 ＯＦ Ｆ電流０．８〜４ Ｘｌ０−
１２Ａ、ｎＭＯ３薄膜トランジスタで、移動度〜６００
ｃｄ／ｖ・ｓｅｃ、ＯＦＦ電流２〜５ Ｘｌ０−”
Ａというように、液晶ディスプレイ用の薄膜トランジス
タとして十分な性能を有するばかりか、周辺駆動回路と
しても十分な性能を有する薄膜トランジスタが得られた
。また、光透過率も８０％以上の透明性を有する高性能
薄膜トランジスタが得られた。As a result of investigating the characteristics of the thin film transistor according to the present invention, 9
Mobility ~200 cIa/v with MO3 thin film transistor
-5ec, OF current 0.8~4Xl0-
12A, nMO3 thin film transistor, mobility ~600
cd/v・sec, OFF current 2 to 5 Xl0-”
As shown in A, a thin film transistor was obtained that not only had sufficient performance as a thin film transistor for a liquid crystal display, but also had sufficient performance as a peripheral drive circuit. Furthermore, a high-performance thin film transistor having transparency with a light transmittance of 80% or more was obtained.
第１図は第１の発明の実施例を示す図であり、（ａｌは
断面図、（ｂｌは平面図、
第２図は第２の発明の薄膜トランジスタの製造方法の一
実施例を示す図であり、（ａ）〜（ｆ）は各製造工程で
の断面図、
第３図は従来の単結晶Ｓｉを用いた液晶ディスプレイ用
トランジスタの構造を示す図である。
１・・・絶縁性基板
２・・・透明接着材
３・・・ゲート絶縁膜
４・・・ゲート電極
５・・・第１の絶縁保護層
６・・・単結晶Ｓｉ層
７・・・ドレイン領域
８・・・ソース領域
９・・・素子分離用絶縁層
１０・・・ドレイン電極
１１・・・ソース電極
１２・・・第２の絶縁保護層
１３・・・絵素電極
１４・・・Ｓｉ基板
１５・・・素子分離用Ｓｉ層
代理人弁理士 岩 佐 義 幸第１図
第 ２図 （その１）
第 ２図 （その２）
第３図FIG. 1 is a diagram showing an embodiment of the first invention, (al is a cross-sectional view, (bl is a plan view, and FIG. 2 is a diagram showing an embodiment of the method for manufacturing a thin film transistor of the second invention. 1. Insulating substrate 2 ...Transparent adhesive material 3...Gate insulating film 4...Gate electrode 5...First insulating protective layer 6...Single crystal Si layer 7...Drain region 8...Source region 9 ...Insulating layer for element isolation 10...Drain electrode 11...Source electrode 12...Second insulating protective layer 13...Picture element electrode 14...Si substrate 15...For element isolation Si layer representative patent attorney Yoshiyuki Iwasa Figure 1 Figure 2 (Part 1) Figure 2 (Part 2) Figure 3
Claims (2)
いて、素子分離用絶縁層と、ソース、ドレイン領域を有
し前記素子分離用絶縁層と同一面内に設けられた島状の
単結晶Ｓｉ部と、前記絶縁性基板と前記単結晶Ｓｉ部と
の間に設けられたゲート絶縁膜、ゲート電極、接着絶縁
層と、前記島状の単結晶Ｓｉ部に対して前記ゲート電極
と反対側にソース、ドレイン領域と電気的に接触せしめ
るように設けられたソース、ドレイン電極とを有するこ
とを特徴とする薄膜トランジスタ。(1) In a thin film transistor provided on an insulating substrate, an insulating layer for element isolation, an island-shaped single crystal Si portion having source and drain regions and provided in the same plane as the insulating layer for element isolation; , a gate insulating film, a gate electrode, an adhesive insulating layer provided between the insulating substrate and the single-crystal Si portion, and a source on the side opposite to the gate electrode with respect to the island-shaped single-crystal Si portion; A thin film transistor characterized by having a source electrode and a drain electrode provided in electrical contact with a drain region.
、前記素子分離用絶縁層を部分的に除去して絶縁層の窓
を形成する工程と、形成された窓部分に島状の単結晶Ｓ
ｉ層を選択的に形成する工程と、前記島状の単結晶Ｓｉ
層にこの層の厚さ以上の厚さを持つソース、ドレイン領
域を有するトランジスタを形成する工程と、形成された
トランジスタ側に絶縁性基板を接着する工程と、前記絶
縁性基板の反対側から前記Ｓｉ基板を研磨加工して前記
素子分離用絶縁層と前記トランジスタを残して薄膜化す
る工程と、前記ソース、ドレイン領域と電気的接触せし
めるようにソース、ドレイン電極を形成する工程とを含
むことを特徴とする薄膜トランジスタの製造方法。(2) A step of forming an insulating layer for element isolation on the Si substrate, a step of partially removing the insulating layer for element isolation to form a window in the insulating layer, and a step of forming an island-like insulating layer in the formed window portion. Single crystal S
A step of selectively forming an i-layer, and a step of forming the island-shaped single crystal Si.
A step of forming a transistor having a source and drain region having a thickness equal to or greater than the thickness of this layer in a layer, a step of bonding an insulating substrate to the side of the formed transistor, and a step of bonding the insulating substrate from the opposite side of the insulating substrate. The method includes the steps of: polishing the Si substrate to make it a thin film leaving the element isolation insulating layer and the transistor; and forming source and drain electrodes so as to make electrical contact with the source and drain regions. Characteristic method for manufacturing thin film transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61236217A JPS6390859A (en) | 1986-10-06 | 1986-10-06 | Thin film transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61236217A JPS6390859A (en) | 1986-10-06 | 1986-10-06 | Thin film transistor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6390859A true JPS6390859A (en) | 1988-04-21 |
Family
ID=16997515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61236217A Pending JPS6390859A (en) | 1986-10-06 | 1986-10-06 | Thin film transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6390859A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05152332A (en) * | 1991-11-07 | 1993-06-18 | Fujitsu Ltd | Mos transistor and manufacturing method thereof |
| US5347154A (en) * | 1990-11-15 | 1994-09-13 | Seiko Instruments Inc. | Light valve device using semiconductive composite substrate |
| US5455182A (en) * | 1990-11-02 | 1995-10-03 | Sharp Kabushiki Kaisha | Semiconductor process for forming channel layer with passivated covering |
| US5496764A (en) * | 1994-07-05 | 1996-03-05 | Motorola, Inc. | Process for forming a semiconductor region adjacent to an insulating layer |
| US5574292A (en) * | 1992-05-13 | 1996-11-12 | Seiko Instruments Inc. | Semiconductor device with monosilicon layer |
| US5618739A (en) * | 1990-11-15 | 1997-04-08 | Seiko Instruments Inc. | Method of making light valve device using semiconductive composite substrate |
| US5633176A (en) * | 1992-08-19 | 1997-05-27 | Seiko Instruments Inc. | Method of producing a semiconductor device for a light valve |
| US5674758A (en) * | 1995-06-06 | 1997-10-07 | Regents Of The University Of California | Silicon on insulator achieved using electrochemical etching |
| US5811322A (en) * | 1996-07-15 | 1998-09-22 | W. L. Gore & Associates, Inc. | Method of making a broadband backside illuminated MESFET with collecting microlens |
| US6187605B1 (en) * | 1992-08-19 | 2001-02-13 | Seiko Instruments Inc. | Method of forming a semiconductor device for a light valve |
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| JPS5252582A (en) * | 1975-10-25 | 1977-04-27 | Toshiba Corp | Device and production for semiconductor |
| JPS5678168A (en) * | 1980-10-08 | 1981-06-26 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS5691276A (en) * | 1979-12-25 | 1981-07-24 | Citizen Watch Co Ltd | Display panel |
| JPS5692573A (en) * | 1979-12-26 | 1981-07-27 | Citizen Watch Co Ltd | Display panel |
| JPS5928330A (en) * | 1982-08-10 | 1984-02-15 | Nec Corp | Vapor growth method of semiconductor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5252582A (en) * | 1975-10-25 | 1977-04-27 | Toshiba Corp | Device and production for semiconductor |
| JPS5691276A (en) * | 1979-12-25 | 1981-07-24 | Citizen Watch Co Ltd | Display panel |
| JPS5692573A (en) * | 1979-12-26 | 1981-07-27 | Citizen Watch Co Ltd | Display panel |
| JPS5678168A (en) * | 1980-10-08 | 1981-06-26 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS5928330A (en) * | 1982-08-10 | 1984-02-15 | Nec Corp | Vapor growth method of semiconductor |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5455182A (en) * | 1990-11-02 | 1995-10-03 | Sharp Kabushiki Kaisha | Semiconductor process for forming channel layer with passivated covering |
| US5618739A (en) * | 1990-11-15 | 1997-04-08 | Seiko Instruments Inc. | Method of making light valve device using semiconductive composite substrate |
| US5347154A (en) * | 1990-11-15 | 1994-09-13 | Seiko Instruments Inc. | Light valve device using semiconductive composite substrate |
| US5486708A (en) * | 1990-11-15 | 1996-01-23 | Seiko Instruments Inc. | Light valve device using semiconductive composite substrate |
| US5728591A (en) * | 1990-11-15 | 1998-03-17 | Seiko Instruments Inc. | Process for manufacturing light valve device using semiconductive composite substrate |
| US5572045A (en) * | 1990-11-15 | 1996-11-05 | Seiko Instruments Inc. | Light valve device using semiconductive composite substrate |
| JPH05152332A (en) * | 1991-11-07 | 1993-06-18 | Fujitsu Ltd | Mos transistor and manufacturing method thereof |
| US5574292A (en) * | 1992-05-13 | 1996-11-12 | Seiko Instruments Inc. | Semiconductor device with monosilicon layer |
| US5633176A (en) * | 1992-08-19 | 1997-05-27 | Seiko Instruments Inc. | Method of producing a semiconductor device for a light valve |
| US6187605B1 (en) * | 1992-08-19 | 2001-02-13 | Seiko Instruments Inc. | Method of forming a semiconductor device for a light valve |
| US5496764A (en) * | 1994-07-05 | 1996-03-05 | Motorola, Inc. | Process for forming a semiconductor region adjacent to an insulating layer |
| US5674758A (en) * | 1995-06-06 | 1997-10-07 | Regents Of The University Of California | Silicon on insulator achieved using electrochemical etching |
| US5811322A (en) * | 1996-07-15 | 1998-09-22 | W. L. Gore & Associates, Inc. | Method of making a broadband backside illuminated MESFET with collecting microlens |
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