WO1995018463A1 - Single crystal silicon on quartz - Google Patents

Single crystal silicon on quartz Download PDF

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Publication number
WO1995018463A1
WO1995018463A1 PCT/US1994/014517 US9414517W WO9518463A1 WO 1995018463 A1 WO1995018463 A1 WO 1995018463A1 US 9414517 W US9414517 W US 9414517W WO 9518463 A1 WO9518463 A1 WO 9518463A1
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Prior art keywords
single crystal
layer
crystal silicon
silicon
display
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PCT/US1994/014517
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French (fr)
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Kalluri R. Sarma
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Honeywell Inc.
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Publication of WO1995018463A1 publication Critical patent/WO1995018463A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

Single crystal silicon bonded on a high temperature quartz substrate, thereby resulting in, for example, high mobility thin film transistor integrated drivers in active matrix displays for high resolution and fast response.

Description


  
 



   SINGLE CRYSTAL SILICON ON QUARTZ
 BACKGROUND OF THE INVENTION
 The present invention is relevant to high resolution active matrix display technology. Particularly, the invention pertains to single crystal silicon thin film transistors having high mobility, on a high temperature transparent substrate.



   High resolution active matrix displays are desired for various applications including computers, entertainment, electronics and avionics. In the related art, the high resolution active matrix displays are manufactured using amorphous silicon (a-Si) active matrix thin film transistors (TFTs), having external row and column drivers connected to the display glass with a flex cable or other connecting mechanism. The external row and column drivers are fabricated using conventional single crystal silicon wafers, which is an approach that is satisfactory for only low resolution displays. The reason is that because, as the display resolution increases, the number of interconnections increases and the interconnect pitch decreases. Such increase of interconnection density results in an extremely difficult, impractical or impossible, interconnection of the external drivers to the display.

   For instance, when the interconnect pitch, which is the distance between the centers of the interconnects, becomes smaller than 0.006 inches (150 microns), then the feasibility of the implementation of external drivers diminishes.



  Light valve displays require higher resolutions such as one thousand lines per inch (lpi) or greater, with a 0.001 inch (25 micron) or smaller pitch, resulting in an almost impossible task to utilize interconnections to external drivers. The solution to this very small pitch interconnection problem, is fabrication of row and column drivers on the display glass itself, i. e., integrated drivers, together with the active matrix array.



  Integrated drivers allow high display resolution, reduce external connections from several thousand to less than several dozen, improve display system reliability and reduce costs. However, because of the low mobility (e. g., one centimeter squared per volt-second) of a-Si TFTs in the present displays, fabrication of integrated drivers on high resolution displays is not practical since the needed performance would not be present. In response to this situation, polysilicon (p-Si) TFTs are being developed in the related art for displays having integrated drivers. The mobility of p-Si TFTs is approximately 50 centimeters squared per volt-second. Even though p-Si TFTs have significantly better mobility than a-Si TFTs, they still require a complex series-parallel  architecture for the driver design.

   The"off'current in polysilicon TFTs is high; thus, two TFTs are connected in series to reduce the"off'current.



   Much more superior integrated drivers can be fabricated using single crystal silicon TFTs having a typical mobility of 600 centimeters squared per voltsecond. If one is able to fabricate single crystal silicon TFTs on glass, having a performance comparable to bulk silicon devices, one can fabricate high resolution displays having integrated drivers without performance degrading tradeoffs.



   In the related art, two approaches are being pursued to fabricate single crystal silicon TFTs on a transparent substrate. One approach involves fabricating the
TFT drivers in a silicon-on-insulator (SOI) substrate, attaching the driver side of the
SOI substrate to a transparent display substrate having an adhesive, and etching away a silicon wafer leaving behind the TFTs in the driver layer. Major problems with this approach are the poor reliability of the low temperature adhesive bonding and the degrading effect of the presence of this adhesive layer on the performance of high current drivers.



   A second approach involves electrostatically bonding a silicon wafer having an etch-stop layer to an expansion-matched glass substrate, etching away the silicon wafer and the etch stop layer thereby leaving behind a thin single crystal silicon device layer, and fabricating TFTs on this device layer using lower processing temperatures (e. g., 600 degrees Centigrade) which are dictated by the strain point of glass. This approach requires further development in the use of low temperature device processes.



   SUMMARY OF THE INVENTION
 The features of the invention are high mobility single crystal silicon TFTs on transparent display substrates, and the improvement of the resolution and reliability of active matrix displays. The advantages of using fused quartz as a substrate in the invention is that the quartz is readily available in needed sizes and required surface quality, and quartz has high chemical purity, high temperature tolerance and compatibility with conventional silicon integrated circuit processing techniques.



   BRIEF DESCRIPTION OF THE DRAWINGS
 Figure 1 shows a layout of the related art drivers and active matrix display.  



   Figure 2 shows the layout of a single crystal active matrix display and single crystal silicon integrated drivers on the same substrate.



   Figure 3 is a graph revealing the thermal expansion coefficients of silicon, quartz and other kinds of glass.



   Figure 4a-4g show a series of steps for fabricating single crystal silicon thin film transistors on a quartz substrate.



   Figure 5 is a cross-section view of a CMOS device fabricated with a silicon on quartz substrate.



   Figures 6a and 6b reveal performance characteristics of single crystal silicon N-channel thin film transistors on quartz
 Figures 7a and 7b reveal performance characteristics of single crystal silicon P-channel thin film transistors on quartz.



   Figure 8 is a cross section diagram of a single crystal silicon on quartz active matrix liquid crystal display.



   DESCRIPTION OF THE PREFERRED EMBODIMENTS
 The related art active matrix display array 11 in figure 1, has drivers 13 on printed circuit board 23 that are situated apart from array 11 and connected with flex connectors 17 to array 11. Several drawbacks of this configuration are limited display resolution and reliability. Figure 2 illustrates display 10 of the present invention which is an active matrix array 11 having integrated row drivers 19, and column drivers 20, on the same display substrate. Few external interconnects 21 provide for driver connections.



   While it may be apparent to use a high temperature transparent substrate such as quartz for conventional high temperature device processing, it has not been possible to bond a silicon wafer to a quartz (SiO2) substrate because of the big difference between the expansion coefficients 12 and 14 of quartz and silicon, respectively, as shown in Figure 3. Expansion coefficient 15 of CORNING 7059 glass appears very different than the other materials, especially at around 600 degrees
Centigrade. Coefficient of expansion 16 of CORNING 1733 glass substrate is very close to coefficient 14 of silicon. Thus, a silicon wafer can be bonded to CORNING
 1733 and processed, at low temperatures (e. g., 600 degrees Centigrade), without  breakage.

   However, if silicon is bonded to quartz at a high temperature by diffusion or an anodical process, the resulting quartz-silicon composite would eventually crack or shatter and disintegrate into many pieces while cooling down to room temperature due to the thermal stresses exceeding the fracture strengths of quartz and silicon.



   If a single crystal silicon substrate surface is prepared to be hydrophilic, it will bond to a quartz substrate, even at room temperature. However, the strength of this kind of bond is not sufficient to keep the silicon-quartz composite in one unit while performing grinding and lapping operations to remove a major portion of the silicon substrate before selective etching is done to remove the remaining final part of the silicon wafer and the etch-stop layer. The present invention prevents the destructive aspect of the latter operations.



   Figures 4a-g illustrate the various steps involving fabrication of single crystal TFTs on a quartz substrate 20. To begin, one epitaxially deposits a 2 micron thick heavily boron (p++) doped silicon layer 30, in figure 4a, as an etch stop layer on an approximately 22 mil lightly boron (p-) doped single crystal silicon substrate 18 at about 900 degrees Centigrade. Next, an approximately 0.6 micron thick lightly boron (p-) doped single crystal silicon device layer 32 is epitaxially deposited on silicon etch stop layer 30 at about 900 degrees Centigrade. Single crystal silicon device layer 32 has a surface with no more than a 0.3 micron variation in surface relative to a true plane at the surface. The surface of single crystal device layer 32 is cleaned in a solution containing H202.

   Then, one bonds a surface of an amorphous quartz substrate 20, the surface of quartz substrate 20 having no more than a 0.3 micron variation in surface relative to a true plane at the surface, to the cleaned surface of single crystal silicon device layer 32, wherein the surfaces of quartz substrate 20 and silicon device layer 32 naturally bond through hydrogen-oxygen (H-O) bonding at room temperature. Figure 4b shows the securing and sealing the bond of single crystal silicon device layer 32 and quartz layer 20 with an adhesive 22 EPO-TEK 301 applied to edge of silicon substrate 18, etch stop layer 30, single crystal silicon device layer 32 and quartz layer 20. Figure 4c illustrates an alternative configuration having layers 18,30 and 32 different in size relative to layer 20 or cut down in size, and then adhesive 22 being applied to the layers for sealing and securing.

   Figure 4d illustrates grinding away a portion of silicon substrate 18 and a portion of adhesive 22. The remaining portion of silicon substrate 18  is etched away with ethylenediamine pyrocatechol. The remaining portion of adhesive 22 is physically removed from the edges of layers 20,30 and 32. Etch stop layer is etched away. Islands 34 are defined with a photoresist mask applied to single crystal silicon device layer 32. Then dry etching of single crystal silicon islands is performed with reactive ion etching of portions of single crystal device layer 32, according to a pattern of the photoresist mask.

   Single crystal silicon islands 34 are diffusion bonded to quartz substrate 20 at about 1000 degrees Centigrade ; and, at the same time, single crystal silicon islands 34 may be thermally oxidized in ambient oxygen at about 1000 degrees Centigrade, to form a 500 angstrom layer 36 of silicon dioxide on silicon islands 34. After these processes, related art processing methods can be resorted to in order to complete the making of high mobility thin film transistors for integrated drivers.



   As noted above, after conditioning the silicon layer 32 surface to be hydrophilic, the layer 32 surface is bonded to a quartz substrate 20 at room temperature.



  Cleaning silicon layer 32 in an RCA solution (RCA 1-1 NH3: 5 H20: 1 H202, or RCA 2-1 HC1: 6 H20: 1 H202) or solutions containing H2SO4 and H202 may be used to make the silicon surface hydrophilic. The bonding surfaces of silicon layer 32 and quartz 20 have a planar surface that does not exceed 0.3 micron in variation in planarity.



  After the silicon layer 32 and quartz wafer 20 surfaces are cleaned in a clean room to produce particle-free surfaces, a very uniform bonding can occur with no voids. After the bonding, this composite layer 24 is edge sealed with a suitable adhesive material 22 as shown in Figure 4b. Figure 4b illustrates the situation when both silicon and quartz substrates 18 and 20 are of the same size and edge ground. Figure 4c illustrates the situation when substrates 18 and 20 are not of the same size and not edge ground.



  Configuration of Figure 4b or the configuration of Figure 4c may be used. Edgeseal/adhesive 22 serves two purposes. First, in addition to the bonding, edge seal/adhesive 22 keeps silicon-quartz substrate composite 24 intact during the subsequent silicon grinding and lapping operations, including grinding away some adhesive 22, which result in composite 24 in Figure 4d. Second, seal 22 presents water and other chemical etching solutions during lapping and thinning operations, from seeping into the bond interface through any improperly bonded regions at the very edge of substrates 18 and 20. Figure 4c illustrates a crevice 26 at the very edge of the  interface due to improper bonding. If water or etching solutions get to the interface, delamination of composite layer 24 could result. An effective adhesive 22 used for edge-sealing is EPO-TEK 301 (Epoxy Technology Inc.).

   A thin bead of this epoxy may be applied at the edge of substrate composite 24 with a syringe. Other material such as a photo resist or other adhesive materials may also be used for edge-sealing.



   Figure 4e shows composite 28 after edge-sealing removal, and silicon grinding and lapping operations. Remaining unground silicon substrate 18 is selectively etched away with the application of ethylenediamine pyrocatechol (EDP) selective etch.



  Then the epoxy edge seal is easily removed from quartz substrate 20 by a mechanical means. This removal is followed by removal of etch-stop layer 30 (having a typical thickness of two microns) by selective etching with 1 HF: 3 HNO3: 8 HAc etchant, thereby leaving a thin (typically 0.6 micron thick) single crystal silicon device layer 32 as shown in Figure 4e. Figure 4f shows a result when the silicon device layer 32 is photolithographically patterned and dry etched (with reactive ion etching-RIE) to define silicon islands (mesas) 34 for the fabrication of integrated TFT active matrix display and row and column drive circuitry. All the steps of processing up through
Figure 4f are conducted at room temperature.



   Figure 4g reveals the result of the next process step which is the high temperature annealing/diffusion bonding of silicon islands 34 in ambient oxygen.



  Quartz wafer 20 having silicon islands 34 is placed in an annealing/oxidation furnace wherein the temperature is slowly ramped from room temperature to approximately 1,000 degrees Centigrade at a ramp rate of about 20 degrees Centigrade per minute.



  When the furnace has reached about 500 degrees Centigrade, dry oxygen is circulated into the furnace to grow about a 500 angstrom thickness of thermal silicon dioxide 36 on islands 34. This process occurs for about a total of sixty minutes, twenty-five minutes of it while the furnace temperature is being ramped from 500 to a 1,000 degrees and then the remaining thirty-five minutes is at about 1,000 degrees Centigrade. After that period of time, the substrate 20 is removed from the furnace. Even though the silicon on quartz structure 28 of Figure 4g, is heated to be annealed at 1,000 degrees
Centigrade, structure 20 does not have any thermal stress problems because the thermal stresses in silicon film islands 34 increase as a square of their size, i. e., diameter or width.

   Islands 34 having a size as large as 250 by 250 microns may be made without  the destructive effect of stresses at very high temperatures such as 1000 degrees
Centigrade. Thus, the etching of single crystal silicon device film 32 into islands 34 having a typical size on the order of 10 by 10 microns, results in very small thermal stresses in silicon film islands 34 at high temperatures.



   The high temperature annealing process results in diffusion bonding with a substantial increase in bond strength between silicon islands 34 and quartz substrate 20.



  The process also results in a growing of a 500 angstrom thick thermal oxide 36 which is used as an implant screen oxide for subsequent CMOS device processing. Diffusionbonded structure 28 may be processed using conventional, high-temperature silicon
CMOS device processes. The conventional high temperature silicon CMOS processes may be used to fabricate either N or P channel single crystal silicon field effect TFTs 54 or 66, respectively, as shown in Figure 5, for an active matrix display with integrated drivers.



   P type single crystal silicon 43 of N-channel field effect transistor (FET) 54 in figure 5, is situated under polysilicon gate electrode 58. Single crystal silicon 46 under source contact 48 and single crystal silicon 50 under drain contact 52, along with single crystal silicon 43, are single crystal island 34 formed on quartz substrate 20.



  Single crystal silicon portion 46 is initially boron doped p type silicon which is subsequently implanted with phosphorous (P31) ions to result in n+ type silicon. The implantation conditions for the n+ silicon are an energy of about 80 keV and a dose of about 5 X 1015/cm2 of P31. Single crystal silicon portion 50 is also implanted with phosphorous (P31) atoms to result in the n+ doped silicon. The boron concentration of the channel region 43 is adjusted to about 7 X 1015 atoms/cm3 by B implantation, to adjust the threshold voltage of N-channel FET 54. Formed on portions 46 and 50 are ohmic contacts 48 and 52, respectively. The thickness of portions 43,46 and 50 is about 5000 angstroms. The composition of ohmic contacts 48 and 52 is about one percent silicon, four percent copper and the rest is aluminum.

   Formed on portion 43 and parts of portions 46 and 50 is about 500 angstroms of thermal silicon dioxide 56 and 57.



  Silicon dioxide, 56 and 57, is grown at about 1000 degrees C. Grown on silicon dioxide 56 is a phosphorous doped polysilicon gate electrode 58 which approximately covers the area of portion 43 of the single crystal silicon layer. The gate 58 layer is about 4000 angstroms thick. Formed on polysilicon gate electrode 58 is about 7500 angstroms of  passivation silicon dioxide 60. Other areas of FET 54 are also covered by about 7500 angstroms of passivation silicon dioxide 64.



   The structure of P-channel FET 66 is similar to that of FET 54. Portions 68,70 and 72 are single crystal silicon island 34 of figure 4g. The reason for the different portions is that each has a doping difference that separates the adjacent portions from each other. Single crystal portions 68,70 and 72 are approximately about 5000 angstroms thick. Portion 70 of the single crystal silicon layer is actually n doped for purposes of adjusting the P-channel FET 66 threshold voltage. Such doping to get the n doped portion 70 is done with phosphorous implantation to achieve a doping concentration of about 1 X 1016 atoms/cm3. Portions 68 and 72 for the source and drain, respectively, are p+ doped material which is implanted with boron (B 11) ions with an energy of 70 keV and a dose of about 5 X 1015/cm2.

   Situated on portions 68 and 70, respectively, are source contact 74 and drain contact 76. Of course, one must note that portions 68,70 and 72 of single crystal island 34 is bonded to quartz 20.



  Contacts 74 and 76 have the same composition as contacts 48 and 52 of FET 54.



  Contacts 44,48,74 and 76 have a thickness of about 10,000 angstroms. Formed on portion 70 and overlapping partially onto portions 68 and 72, is a layer of thermal silicon dioxide, 78 and 79, grown at 1000 degrees C. and having a thickness of 500 angstroms. Formed on layer 78 is layer 80 of a phosphorous doped polysilicon gate electrode having a thickness of 4000 angstroms. Layer 82, which is formed on layer 80, is about 7500 angstroms of passivation silicon dioxide similar to that of layer 60 of FET 54. Passivation silicon dioxide is also formed about the FETs as layer 64.



   Figures 6a, 6b, 7a and 7b show the performance characteristics of the single crystal silicon thin film transistors (TFTs) fabricated on the quartz substrate using conventional high temperature CMOS integrated circuit processing. The TFTs, tested for results shown in figures 6a, 6b, 7a and 7b, were fabricated using 500 angstrom thick thermal Si02 dielectric grown at 1000 degrees C, and a polysilicon gate electrode.



   Figure 6a shows the source-drain current, Ids, and transconductance, Gm, as a function of the gate voltage Vg, for a drain voltage, Vd, of five volts, for an Nchannel (NMOS) silicon on quartz (SOQ) TFT with a channel width to length ratio,
W/L of 10pm/10pm. Figure 6b shows a plot of the square root of Ids versus Vg, for the  
TFT of figure 6a under a saturation condition. Figure 6b shows that this TFT has a threshold voltage of 0.55 V, and an electron mobility of over 700 cm2/Volt * Sec.



   Similarly figures 7a and 7b show the performance of a typical P-channel (PMOS) SOQ TFT. Figure 7a shows the Ids, and Gm as function of Vg for a Vd of minus five volts for TFT with a W/L ratio of 10pLm/10, um. Figure 7b shows the threshold voltage and the hole mobility of this PMOS TFT to be-1.63 V, and over 200 cm2/Volt * Sec., respectively. The superior performance of these TFTs, as indicated by the high saturation currents, low leakage currents, and high electron and hole mobility, is due to the single crystal silicon on quartz substrate structures. These TFT device performance characteristics permit the fabrication of high resolution active matrix displays having integrated drivers.



   Figure 8 shows a schematic cross-section of an active matrix liquid crystal display using silicon on quartz active matrix array with integrated drivers. The liquid crystal material 93 is sandwiched between the single crystal silicon on quartz (SOQ) active matrix substrate 84 and the common electrode/color filter substrate 92, and sealed at the periphery using a conventional display sealing material 85. The peripheral seal 85 may be placed on top of the integrated drivers 86 to minimize the inactive display area. In the display area, the SOQ TFTs 87 are connected to pixel electrodes 88.



  Common electrode substrate 92 may be made of the conventional display glass material such as CORNING 7059. Color filter 90 and black matrix 91 elements are fabricated on common electrode substrate 92 using standard procedures. Then the indium tin oxide (ITO) common electrode 89 is deposited on the color filter/black matrix array using standard conditions and procedures. For a compact packaging, external connections 94 to the display are made on just one side of substrate 84, as shown in figures 8 and 2.



   In addition to using the additive color technique and apparatus as shown in figure 8, full color also can be achieved in an SOQ active matrix liquid crystal display either by using subtractive color technique and apparatus, or field sequential color technique and apparatus.

Claims

CLAIMS 1. A high mobility transistor comprising: a quartz substrate; and single crystal silicon formed on said quartz substrate.
2. The transistor of claim 1 further comprising: a first electrode contact formed on a first portion of said single crystal silicon; a second electrode contact formed on a second portion of said single crystal silicon; silicon dioxide formed on a third portion of said single crystal silicon; and a polysilicon electrode formed on said silicon dioxide.
3. The transistor of claim 2 further comprising silicon dioxide formed on said polysilicon electrode.
4. A high mobility transistor comprising: a quartz substrate; and a single crystal silicon layer formed on said quartz substrate, wherein: a first portion of said single crystal silicon layer is doped and is a source electrode; a second portion of said single crystal silicon is doped and is a drain electrode; a third portion of said single crystal silicon is situated between first and second portions of said single crystal silicon layer; a first contact formed on the first portion of said single crystal silicon layer; a second contact formed on the second portion of said single crystal silicon layer; a silicon dioxide layer formed on at least the third portion of said single crystal silicon layer; and a polysilicon gate electrode layer formed on said thermal silicon dioxide layer.
5. The transistor of claim 4 wherein: said first and second portions are n+ doped; and the third portion is p doped material.
6. The transistor of claim 5 wherein: said single crystal silicon layer is about 5000 angstroms thick; said silicon dioxide layer is a thermal silicon dioxide having a thickness of about 500 angstroms; and said polysilicon gate electrode layer has a thickness of about 4000 angstroms.
7. The transistor of claim 6 further comprising a passivation silicon dioxide layer formed on said polysilicon gate electrode layer, wherein said silicon dioxide layer has a thickness of about 7500 angstroms.
8. The transistor of claim 4, wherein: said first and second portions of said single crystal silicon layer are p+ doped; and said third portion of said single crystal silicon layer is n doped.
9. The transistor of claim 8 wherein: said single crystal silicon layer is about 5000 angstroms thick; said silicon dioxide layer is a thermal silicon dioxide having a thickness of about 500 angstroms; and said polysilicon gate electrode layer has a thickness of about 4000 angstroms.
10. The transistor of claim 9 further comprising a passivation silicon dioxide layer formed on said polysilicon gate electrode layer, wherein said silicon dioxide layer has a thickness of about 7500 angstroms.
11. An active matrix liquid crystal display comprising: a quartz substrate; and a plurality of single crystal silicon thin film transistors formed on said quartz substrate.
12. The display of claim 11, wherein said plurality of single crystal silicon thin film transistors are pixel switches and display pixel drivers integrated on said display.
13. The display of claim 12, wherein said display comprises additive color apparatus.
14. The display of claim 12, wherein said display comprises subtractive color apparatus.
15. The display of claim 12, wherein said display comprises frame sequential color apparatus.
PCT/US1994/014517 1993-12-30 1994-12-15 Single crystal silicon on quartz WO1995018463A1 (en)

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US08/176,583 1993-12-30

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EP0504714A2 (en) * 1991-03-15 1992-09-23 Shin-Etsu Handotai Company Limited Semiconductor substrate having a SOI structure and method of producing the same
EP0510368A1 (en) * 1991-03-28 1992-10-28 Honeywell Inc. Method for fabricating thin film transistors and thin film transistor produced by said method
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EP0497592A2 (en) * 1991-01-30 1992-08-05 TDK Corporation Non single crystal semiconductor device and manufacturing method
EP0504714A2 (en) * 1991-03-15 1992-09-23 Shin-Etsu Handotai Company Limited Semiconductor substrate having a SOI structure and method of producing the same
EP0510368A1 (en) * 1991-03-28 1992-10-28 Honeywell Inc. Method for fabricating thin film transistors and thin film transistor produced by said method
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002058153A2 (en) * 2001-01-02 2002-07-25 Honeywell International Inc. Back illuminated imager with enhanced uv to near ir sensitivity
WO2002058153A3 (en) * 2001-01-02 2003-05-01 Honeywell Int Inc Back illuminated imager with enhanced uv to near ir sensitivity

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