JP3531415B2 - SOI substrate, method of manufacturing the same, semiconductor device and liquid crystal panel using the same - Google Patents

SOI substrate, method of manufacturing the same, semiconductor device and liquid crystal panel using the same

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Publication number
JP3531415B2
JP3531415B2 JP10451897A JP10451897A JP3531415B2 JP 3531415 B2 JP3531415 B2 JP 3531415B2 JP 10451897 A JP10451897 A JP 10451897A JP 10451897 A JP10451897 A JP 10451897A JP 3531415 B2 JP3531415 B2 JP 3531415B2
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Prior art keywords
substrate
layer
light
crystal silicon
single crystal
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JPH10293320A (en
Inventor
幸哉 平林
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セイコーエプソン株式会社
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Description

DETAILED DESCRIPTION OF THE INVENTION [0001] The present invention relates to SOI (Silic).
on on Insulator substrate, especially transparent support
SOI substrate using a metal plate, its manufacturing method, and its SO
The present invention relates to a liquid crystal panel and an electronic device using an I substrate. [0002] 2. Description of the Related Art A silicon thin film is formed on an insulating substrate and
Technology for forming semiconductor devices on silicon thin film
Has the advantages of higher speed, lower power consumption, higher integration, etc.
It is widely studied because it has. As one of the SOI technologies, a single crystal silicon
Technology for manufacturing SOI substrates by bonding
You. This method, commonly called laminating, uses a single crystal
Bonding silicon substrate and support substrate using hydrogen bonding force
After that, the bonding strength is not enhanced by heat treatment.
And then grinding or polishing the single crystal silicon substrate, or
The thin single crystal silicon layer on the supporting substrate by etching
It is formed. In this method, a single crystal
To reduce the thickness of the silicon substrate, the crystallinity of the silicon thin film
Excellent and high performance devices can be created. [0004] Further, there is a case where this bonding method is applied.
And implant hydrogen ions into the single crystal silicon substrate.
After bonding it to the supporting substrate, heat treatment
Separate the silicon layer from the hydrogen implanted region of the single crystal silicon substrate
(US Patent 5374564)
A single-crystal silicon layer on a porous silicon substrate
It was grown epitaxially and bonded to a supporting substrate.
Later, the silicon substrate is removed and the porous silicon layer is etched.
Single crystal on supporting substrate
A method of forming a silicon thin film (JP-A-4-34641)
8) are known. According to such a bonding method
SOI substrates are similar to ordinary bulk semiconductor substrates.
Used in the manufacture of various devices,
As a different feature from the support substrate, various materials are used for the support substrate.
Points that can be used. Ie
As well as a normal silicon substrate as a support substrate,
Transparent quartz or glass substrates can be used.
Wear. Forming a single-crystal silicon thin film on a transparent substrate
Devices that require light transmission, such as transmission
Single crystal with excellent crystallinity even for oversized liquid crystal display devices
Forming high-performance transistor elements using silicon
It becomes possible. [0005] SUMMARY OF THE INVENTION A transparent support group
Board and SOI substrate with single crystal silicon thin film bonded together
In other words, the single crystal silicon layer is a MOSFET (Metal
  Oxide Semiconductor Field
d Effect Transistor)
As channel, source, and drain regions of transistor elements
Used. At this time, if the substrate is transparent,
When the light is irradiated, the channel area of this MOSFET
Leakage current due to light irradiation in the region, device characteristics
Deteriorates. (Note that here the single crystal silicon layer is formed
The opposite side is the front side of the substrate, and the opposite side is the rear side. )
This point will be specifically described with reference to the drawings. FIG.
Is a bonded SO using a conventionally manufactured transparent substrate.
It is sectional drawing of an I board. In this SOI substrate, a single crystal silicon
The recon layer 2 is bonded to the support substrate 1 via the oxide film layer 3.
The structure has been. The oxide film layer 3 described here is one layer.
Generally, it has the property of transmitting light, so quartz or gas
In a conventional SOI substrate using a transparent material such as glass,
Any layer having a light shielding property is provided under the crystalline silicon layer 2.
It has not been queried. FIG. 3 shows the conventional SOI substrate shown in FIG.
It is sectional drawing of the MOSFET manufactured using it. Support substrate
On top of this is an oxide film layer 3 and a single crystal silicon layer
Source region of MOSFET formed by patterning
2b, a channel region 2a, and a drain region 2c.
This single crystal silicon region is formed by oxidizing the surface
2d. Gate insulating film 2
On top of the gate electrode 6 is a single-crystal MOSFET MOSFET.
The recon region and the gate electrode 6 are covered with a first interlayer film 7.
Has been done. Further, the source line 9 and the drain line 8
The source region 2 b and the source region 2 b are respectively formed through the openings of the interlayer film 7.
It is connected to the rain area 2c. On top of this, a second layer
An interlayer film 10 is formed, and the upper light shielding layer 11 is
0. Upper light-shielding layer 11 is black polyimide
Opaque insulating material such as metal resin or aluminum
And the like. From the substrate surface side
When the light 12a is directly incident, it is provided on the substrate.
The channel region 2a of the MOSFET is formed by the upper light-shielding layer 11.
Thus, light leakage due to the light 12a can be suppressed.
However, in the MOSFET channel region 2a,
In the case where the light indicated by 12c directly enters,
Cannot be prevented. Also, the light is reflected at the backside interface 1a of the substrate.
When there is light like 12b, it is from the substrate surface
Even if it is incident, part of it is the MOSFET chip.
Light reaches the channel region 2a and causes light leakage.
You. That is, the SOI group having the conventional structure shown in FIG.
In the plate, light is shielded between the support substrate 1 and the single-crystal silicon layer 2.
Since no layer is provided, using this SOI substrate
Field of MOSFET formed from single crystal silicon thin film
In this case, the MOSFET channel region 2a is
Whether direct incident light 12c or reflected light 12b on the back of the substrate
Could not be blocked. For this reason, the conventional structure
Light leakage occurs in MOSFET fabricated on SOI substrate
However, there is a fundamental problem that the characteristics of the element are deteriorated.
Was. It is also transparent to light-based devices
It is difficult to use a simple SOI substrate and its versatility is low.
There was a problem. An object of the present invention is to use a transparent support substrate.
Semiconductor devices without light leakage problems.
And a method of manufacturing the same.
Another object of the present invention is to reduce light leakage using a transparent substrate.
High-performance semiconductor devices using SOI substrates
Is to do. [0009] The SOI substrate of the present invention comprises:
To achieve the above objectives, a transparent support substrate and
Prevents light leakage between the single crystal silicon layer
In this case, a buried type light shielding layer is provided. this
The light shielding layer is formed on one surface of the support substrate,
The single-crystal silicon layer is the insulator layer deposited on this light-shielding layer.
Formed on top. The light-shielding layer is the device to be manufactured
To cover the channel region of the MOSFET
Turned, the channel area of the above MOSFET
No light-shielding layer exists in portions other than the region. For this reason, for example,
It is necessary for substrates such as large-sized liquid crystal display devices to transmit light.
It can be used for various applications. Also, this light shielding layer
Refractory metals or their silicon compounds (silicon)
Re-side) to the single crystal silicon layer
Thermal processes such as impurity diffusion
Of SOI substrate with characteristics that are sufficiently stable against heat
be able to.Also, a method for manufacturing an SOI substrate of the present invention
The step of patterning a light-shielding layer on a supporting substrate;
Forming an insulator layer on the support substrate and the light-shielding layer;
Forming an oxide layer on one side of the single crystal silicon substrate.
And forming the single crystal silicon on the insulator layer of the support substrate.
Bonding the oxide layer of the control board by heat treatment;
The single crystal silicon substrate is thinned by etching.
Forming a single-crystal silicon layer by etching,
After the step of performing a heat treatment higher than the heat treatment,
It is characterized by that. Also, the production of the SOI substrate of the present invention
The method may be such that the thickness of the insulator layer is smaller than the thickness of the light shielding layer.
Thicker from 500nm to 1000nm
To be. [0010] BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a preferred embodiment of the present invention.
Explanation will be made based on the plane. (Embodiment 1) FIG. 1 shows an SO to which the present invention is applied.
It is sectional drawing which shows the 1st Example of I board | substrate. In addition, FIG.
FIG. 5 is a view showing the fabrication of an SOI substrate in the first embodiment of the present invention
It is a figure showing a method. As shown in FIG.
The OI substrate has a transistor element on a transparent support substrate 1.
A light-shielding layer 4 is provided, and an insulating layer 5
The single crystal silicon layer 2 is formed via the oxide film layer 3
It is. The manufacturing process of this SOI substrate will be described with reference to FIG.
Will be explained. First, as shown in FIG.
Next, the light shielding layer 4 is formed over the entire surface. In this embodiment
In this case, quartz having a thickness of 1.1 mm was used as a supporting substrate. Interception
The optical layer 4 is formed by sputtering molybdenum by 100 to 10
It is obtained by depositing to a thickness of about 00 nm. This implementation
In the example, molybdenum was deposited to a thickness of 400 nm.
Was. The material of the light-shielding layer 4 is limited to this embodiment.
Not the maximum temperature of the thermal process of the device to be manufactured
Any material that is stable against
No problem. For example, tungsten, tantalum, etc.
Refractory metals, polycrystalline silicon, and even tungsten
Preferred are silicides such as silicide and molybdenum silicide.
It is used as a good material, and its forming method is not only sputtering but also
CVD method, electron beam heating evaporation method, etc. can be used.
Wear. Next, the light shielding layer 4 formed as shown in FIG.
To cover the channel region of MOSFET formed on
To remove the photoresist pattern 13
To form Next, the photoresist formed as shown in FIG.
Etching of the light shielding layer 4 using the distaste pattern 13 as a mask
And dry the light-shielding layer outside the transistor formation area.
Remove by etching. Photoresist after etching
The pattern 13 is peeled off. Next, as shown in FIG.
Between the optical layer 4 and the monocrystalline silicon layer formed thereon;
To ensure insulation, an insulating layer 5 is deposited. This insulation
The layer used was a silicon oxide film. This silicon oxide film
For example, sputtering method or TEOS (tetraethyl oxide)
(Rusosilicate) by plasma CVD method
it can. The insulating layer 5 is formed by polishing the step of covering the light shielding layer 4 by polishing.
Even if the single crystal silicon layer 2 is
The film thickness is set so that sufficient insulating properties can be secured. Specifically, an insulating layer
5 is about 500 to 1000 nm with respect to the thickness of the light shielding layer 4
It is good to deposit many times. In this embodiment, the light shielding layer 4
Silicon oxide film of TEOS
1000 nm was deposited by plasma CVD. Like this
The support substrate with a light-shielding layer obtained by
Because it is uneven depending on the presence or absence of 4
When bonded to a polycrystalline silicon substrate,
Voids (voids) are formed and bond strength when bonded
Is generated. For this reason, as shown in FIG.
The surface of the support substrate on which the optical layer 4 is formed is polished globally.
And flatten. As a method of flattening by polishing, CM
The P (chemical mechanical polishing) method was used. In CMP,
The polishing amount of the insulating layer 5 on the light shielding layer 4 is determined by the thickness of the light shielding layer 4.
Should also be set to be slightly larger by about 200 to 700 nm. This
By performing the CMP process under the conditions of
Part can be reduced to 3 nm or less.
Therefore, even when bonding a single crystal silicon substrate,
Uniform bonding strength is obtained. Next, as shown in FIG.
Support substrate with a light-shielding layer and a single-crystal silicon substrate
The plate 20 is bonded. Single crystal used for bonding
The silicon substrate 20 has a thickness of 300 μm and has a surface
Is oxidized by about 0.05 to 0.8 μm in advance
Layer 3 is formed in advance. This is formed after lamination
Forming interface between single crystal silicon layer 2 and oxide film layer 3 by thermal oxidation
In order to secure an interface having good electric characteristics. Bonding
The heating step is performed by, for example, heat treatment at 300 ° C. for 2 hours.
A method of directly bonding two substrates can be adopted. Paste
To further increase the bonding strength, further heat treatment temperature
It is necessary to raise the temperature to about 450 ° C.
Single crystal silicon substrate has significant difference in thermal expansion coefficient
Therefore, if heated as it is, cracks in the single crystal silicon layer
Defects such as these occur, and the quality of the substrate deteriorates. this
In order to suppress the occurrence of defects such as cracks,
Once heat-treated for bonding at 300 ° C
For wet etching or CMP of crystalline silicon substrate
Therefore, after thinning to about 100 to 150 μm,
It is desirable to carry out a high-temperature heat treatment. In this embodiment
Using a KOH aqueous solution at 80 ° C.
Was etched so as to have a thickness of 150 μm. This
After that, the bonded substrates are again heat-treated at 450 ° C.
The bonding strength is increased. Further shown in FIG.
This bonded substrate is polished to a single crystal silicon
The thickness of the layer 2 was 3 to 5 μm. The bonded substrate thinned as described above
Finally, PACE (Plasma Assisted)
Chemical Etching)
Etching to a thickness of about 0.05-0.8 μm
And finish it. By this PACE process, single crystal silicon
The uniformity of the cone layer 2 is, for example, 100 nm in thickness.
Those within 10% were obtained. Through the above steps, the light shielding layer
Was obtained. Embodiment 2 FIGS. 6 and 7 show a second embodiment of the present invention.
It is a figure showing an example. 4 and 5 have the same reference numerals.
Are the layers or parts formed in the same process.
Shows the material. In this embodiment, the pattern shown in FIG.
Flatten the support substrate surface with the turned light shielding layer
The steps up to this step are exactly the same as those in the first embodiment.
FIG. 6A shows a single crystal silicon substrate used for bonding.
It is. This single crystal silicon substrate 20 has a thickness of 600 μm.
m, the surface of which is previously 0.05 to 0.8 μm
The oxide film layer 3 is formed after being oxidized to a certain degree. Next figure
As shown in FIG. 6 (b), hydrogen is applied to the single crystal silicon substrate 20.
Ions 14 are implanted. For example, in this embodiment, water
Elementary ion (H+) At an acceleration voltage of 100 keV and a dose of 1
0E16cm-2Was injected. By this process
High-concentration layer 15 of hydrogen ions is formed in polycrystalline silicon substrate 20
Is done. Next, ion implantation was performed as shown in FIG.
A light-shielding layer 4 and an insulating layer 5 are formed on a single-crystal silicon substrate 20.
And bonded to the support substrate 1. For example, the bonding process
For example, two substrates are directly heated by heat treatment at 300 ° C for 2 hours.
A bonding method can be adopted. Further, FIG.
And bonding of the bonded single crystal silicon substrate 20
Oxide film 3 on the surface side (this is embedded when the SOI substrate is completed)
A single-crystal silicon layer 2 on a supporting substrate.
The single crystal silicon substrate 20 is peeled from the supporting substrate
Heat treatment for separation is performed. This phenomenon of substrate separation is simply
By hydrogen ions introduced into the crystalline silicon substrate,
Silicon bonding in a layer near the surface of the single crystal silicon substrate
This occurs because the join is divided. In this embodiment,
In addition, the two substrates bonded together were heated at a rate of 20 ° C./min.
Heated to 600 ° C in degrees Celsius. By this heat treatment,
The bonded single crystal silicon substrate 20 is separated from the supporting substrate
And a silicon oxide film 3 of about 400 nm
And a single-crystal silicon layer 2 of about 200 nm is formed thereon.
Was. FIG. 7E is a cross-sectional view showing the SOI substrate after separation.
is there. The surface of this SOI substrate is the surface of the single crystal silicon layer.
Since several nanometers of irregularities remain in the
Need to be Therefore, in this embodiment, the CMP method
Polishing the substrate surface to a very small amount (polishing amount less than 10 nm)
Touch polish was used. This flattening method
Hydrogen annealing for heat treatment in a hydrogen atmosphere
Method can also be used. SOI fabricated as above
The substrate has good uniformity of single crystal silicon film thickness, and
Light shielding that suppresses light leakage for devices to be manufactured
It has a structure having layers. (Embodiment 3) FIGS. 8 and 9 show the present invention.
It is a figure showing a 3rd example. The same reference numerals as in FIGS.
The attached area is a layer formed in the same process, or
Indicates a member. In this embodiment, as shown in FIG.
Flatten the support substrate surface with a patterned light-shielding layer
The steps up to the step of converting are completely the same as in the first embodiment.
You. FIG. 8A shows a single crystal silicon layer for bonding.
This is a silicon substrate to be formed. Silicon substrate 16
Has a thickness of 600 μm and is exposed in HF / ethanol solution.
The surface is turned into a porous layer 17 by extreme oxidation.
Can be. This process makes the surface porous
Oxidized single crystal silicon substrate 16 in a hydrogen atmosphere
By performing a heat treatment at 50 ° C., the surface of the porous layer 17 is
Is smoothed. This is then formed on the silicon substrate 16
Reduce the defect density of the single crystal silicon layer
Is to improve. Next, as shown in FIG.
In addition, silicon in which the surface of the porous silicon layer 17 is smoothed
A single crystal silicon layer is epitaxially grown on the substrate 16.
Form 2 Single crystal silicon by epitaxial growth
The thickness of the deposited layer 2 is 500 nm in this embodiment.
However, this does not limit the scope of the present invention.
No. The thickness of the single crystal silicon layer is
Can be arbitrarily selected according to the service. Further FIG.
As shown in (c), the surface of the single crystal silicon layer 2 is
Oxidize about 0 nm to form oxide film layer 3 and stick it
The buried oxide film of the SOI substrate after the alignment is used. Next figure
As shown in FIG. 9D, the single crystal silicon layer 2 and the oxidized
The substrate on which the film layer 3 is formed is provided with the light-shielding layer 4 and the insulating layer 5 formed thereon.
To the support substrate 1 thus obtained. The bonding process is an example
For example, two substrates are directly heated by heat treatment at 300 ° C. for 2 hours.
Adhesive bonding method can be adopted. Next, as shown in FIG.
As shown in FIG.
Leaving the con layer 2 and the porous silicon layer 17
Grind the silicon substrate. Next, as shown in FIG.
Next, the porous silicon layer 17 is removed by etching.
A single-crystal silicon layer 2 is obtained on the supporting substrate. This porous silicon
The etching of the con layer 17 is performed using HF / H2O2Composition
The use of the etching solution of
The porous silicon layer 17 shows high etching selectivity
To maintain very good uniformity of single crystal silicon film thickness
While only porous silicon can be completely removed
You. SOI from which the porous silicon layer 17 has been removed as described above.
The substrate has irregularities of about several nm on the surface of the single crystal silicon layer 2.
Needs to be flattened. this
In this embodiment, the heat treatment is performed in a hydrogen atmosphere.
A hydrogen annealing method was used. Also, this flattening method
The single crystal silicon layer 2 of the SOI substrate by using the CMP method.
To polish a very small amount of surface (polishing amount less than 10 nm)
Polishing can also be used. Produced by the above
SOI substrate has good single-crystal silicon film thickness uniformity.
Light leakage to the device to be manufactured.
The structure had a light shielding layer. (Embodiment 4) FIG.
As a preferred example of a device using a fabricated SOI substrate,
FIG. 3 is a diagram showing a planar layout of a large-sized liquid crystal panel. What
Please note that this drawing may not be
Places are omitted and are drawn as models. [0016] As shown in FIG.
There is a pixel area 27, and the pixel electrodes 19 are arranged in a matrix.
Are located. A display signal is provided around the display pixel area 27.
A driving circuit for processing the signal is formed. Gate line drive
The circuit 21 sequentially scans the gate signal lines and drives the data lines.
The path 22 supplies an image signal corresponding to the image data to the source signal line.
Supply. Also, an externally input signal is input through the pad area 26.
Input circuit 23 for capturing image data to be
A circuit such as a timing control circuit 24 for controlling the path is provided.
These circuits are all pixel electrode switching
Formed in the same process as the MOSFET for
MOSFET or active element or switching element
And load elements such as resistors and capacitors.
It is composed of FIG. 11 is a cross-sectional view of the liquid crystal panel shown in FIG.
It is sectional drawing in the A 'line. LCD panel as shown in FIG.
Represents a substrate 31 on which display pixels and a driving circuit are formed, and an LC core.
Pair consisting of a transparent conductive film (ITO) to which a mon potential is applied
A transparent substrate 32 having a counter electrode 33 is arranged at regular intervals.
In the gap sealed by the sealing material 35
TN (Twisted Nematic) liquid crystal 34
Or the liquid crystal molecules are aligned almost vertically without applying voltage.
SH (Super Homeotropic) liquid crystal
And the like to form a liquid crystal panel 30.
You. Note that the pad area must be
The area 26 is located outside the sealing material 35 so that the sealing material is
Is set. FIG. 12 shows an SOI group prepared according to the present invention.
In an enlarged plan view of the pixel part of a transmissive liquid crystal panel using a plate
is there. Each pixel has a trap that controls the charge writing to the pixel.
A MOSFET is formed as a transistor element. each
Each pixel has a single channel, source and drain region.
A crystalline silicon layer 2 is provided to form a MOSFET,
One terminal is connected to the gate line 6 and the other terminal is connected to the source line 9.
And the other terminal is connected to the pixel electrode 19 of the display pixel.
It is connected to the rain electrode 8. MOSFET chip
To prevent light blocking in the channel area and light leakage between display pixels.
For this purpose, an upper light shielding layer 11 is formed. This LCD panel
The biggest feature is that the control MOSFET for each display pixel and
Display signal processing, input circuit, and timing control circuit
Under the region for forming the MOSFET to be constituted, all SO
Structure in which the light shielding layer 4 formed at the time of manufacturing the I substrate is arranged
It is a point that has become. This will be described in detail with reference to FIG.
You. FIG. 13 is provided in the display pixel area shown in FIG.
FIG. 3 is a diagram showing a cross-sectional structure taken along line B-B ′ of the MOSFET.
You. MOSFET channel region 2a and transparent support substrate
1 and a light shielding layer 4 so as to cover the channel region 2a.
Is provided, and any incident light from the back side of the substrate is
It has a structure that can be blocked. For example, conventional SO
Direct entry from the back side of the substrate, which could not be
For the emitted light 12c and the reflected light 12b on the back surface of the substrate
The light-shielding layer 4 of the present invention exhibits an effective light-shielding property. here
The MOSFET structure of the display pixel part is shown as an example of the light shielding layer.
However, this structure is based on the drive formed around the display pixel area.
The same applies to MOSFETs that make up circuits.
You. Support substrate provided with light-shielding layer 4 and insulating layer 5
On top of this is an oxide film layer 3 and a single crystal silicon layer
Source region of MOSFET formed by patterning
2b, a channel region 2a, and a drain region 2c.
This single crystal silicon region is formed by oxidizing the surface
2d. Gate insulating film 5
Above the gate electrode 6 is a single crystal silicon MOSFET.
The capacitor region and the gate electrode 6 are covered with the first interlayer film 7
Have been. Further, the source line 9 and the drain line 8 are formed in the first layer.
The source region 2 b and the drain are respectively formed through the openings of the interlayer film 7.
In region 2c. On top of this, a second interlayer
The film 10 is formed, and the upper light-shielding layer 11 and the pixel electrode 19 are
It is formed on the two interlayer films 10. The pixel electrode 1
Reference numeral 9 denotes a drain electrode 8 through an opening of the second interlayer film 10.
The upper light-shielding layer 11 is made of black polyimide resin.
It is made of an opaque insulating material such as
The structure prevents light leakage. In the above embodiment, a transmissive liquid crystal panel is taken as an example.
However, this does not limit the use of the present invention.
Other display devices that use a transparent display mode.
Image input device that reads devices and optical information
It is clear that it can be applied to various semiconductor devices such as
It is. At that time, the drive for driving the semiconductor device is also performed.
The transistor element and the like are mounted on the SOI substrate as in the above embodiment.
What is necessary is just to form on the shading light-shielding layer. The pattern of the light-shielding layer is formed thereon.
Is determined by the arrangement of transistors
The process of laminating the boards is the production of the target semiconductor device
Desirably included as part of the process. This
Connect the board manufacturing process and device manufacturing process
High-performance base that meets the needs of the device.
It is possible to build a total process using plates
To achieve higher device performance and lower process costs.
Can be achieved. [0023] As described above, the SOI substrate according to the present invention is:
Transparent support substrate and semiconductor thin film layer formed on it
A light-shielding layer is provided between the
And light reflected on the back surface of the substrate
To prevent light leakage. others
If the SOI substrate of the present invention is used,
Thus, a device can be manufactured.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of an SOI substrate according to a first embodiment of the present invention. FIG. 2 shows an SO using a conventionally manufactured bonding method.
Sectional drawing of an I board. FIG. 3 is a cross-sectional structural view showing a light shielding means of a MOSFET manufactured using an SOI substrate by a conventional bonding method. FIG. 4 is a diagram showing a manufacturing process of the SOI substrate in the first embodiment of the present invention. FIG. 5 is a diagram showing a manufacturing process of the SOI substrate in the first embodiment of the present invention. FIG. 6 is a view showing a manufacturing process of an SOI substrate according to a second embodiment of the present invention. FIG. 7 is a diagram showing a manufacturing process of an SOI substrate according to a second embodiment of the present invention. FIG. 8 is a diagram showing a manufacturing process of an SOI substrate according to a third embodiment of the present invention. FIG. 9 is a view showing a manufacturing process of an SOI substrate according to a third embodiment of the present invention. FIG. 10 is a plan view of a liquid crystal panel according to a fourth embodiment of the present invention. FIG. 11 is a sectional view of a liquid crystal panel according to a fourth embodiment of the present invention. FIG. 12 is a plan layout view of a display pixel portion formed on a substrate of a liquid crystal panel according to a fourth embodiment of the present invention. FIG. 13 is a sectional structural view of a MOSFET manufactured on a liquid crystal panel substrate in a fourth embodiment of the present invention. DESCRIPTION OF THE REFERENCE NUMERALS 1 Transparent support substrate 2 Single crystal silicon thin film 2a MOSFET channel region 2b MOSFET source region 2c MOSFET drain region 2d MOSFET gate oxide film 3 Buried oxide film by surface oxidation 4 Light shielding layer 5 Insulating layer 6 Gate electrode 7 First Interlayer film 8 Drain electrode 9 Source electrode and signal line 10 Second interlayer film 11 Upper light shielding layer 12a Incident light 12b from the substrate surface side Light 12c incident from the substrate surface and reflected by the support substrate 12c Incident light from the substrate back surface 13 Photoresist mask 14 Hydrogen ion beam 15 Hydrogen ion layer 16 implanted in silicon substrate 16 Silicon substrate 17 Porous silicon layer 19 Pixel electrode 20 Single crystal silicon substrate 21 Data line drive circuit 22 Gate line drive circuit 23 Input circuit 24 Timing Control circuit 26 Pad area 2 7 display pixel area 30 liquid crystal panel 31 liquid crystal panel element substrate 32 transparent substrate 33 counter electrode 34 liquid crystal layer 35 sealing material

Claims (1)

  1. (57) a step All Claims to 1. A light-shielding layer on a supporting substrate is patterned, forming an insulator layer on the supporting substrate and the light-shielding layer, a single crystal silicon substrate Forming an oxide layer on one surface of the support substrate, bonding the oxide layer of the single crystal silicon substrate on the insulator layer of the support substrate by heat treatment, and etching the single crystal silicon substrate.
    Forming a single-crystal silicon layer by thinning;
    A step of performing a heat treatment at a higher temperature than the heat treatment after the etching
    And a method for manufacturing an SOI substrate. 2. The thickness of the insulator layer is equal to the thickness of the light shielding layer.
    Compared to 500nm to 1000nm thicker
    The method for manufacturing an SOI substrate according to claim 1, wherein: 3. The step of patterning the light-shielding layer comprises:
    Transistor element formed by the single crystal silicon layer
    Characterized by being patterned to cover the child area
    A method for manufacturing an SOI substrate according to claim 1. 4. The product according to claim 1, wherein
    SOI substrate manufactured by the fabrication method. 5. A production method according to claim 1 or 3.
    Semiconductor device using a fabricated SOI substrate. 6. A production method according to claim 1 or 3.
    Liquid crystal panel using a finished SOI substrate.
JP10451897A 1997-04-22 1997-04-22 SOI substrate, method of manufacturing the same, semiconductor device and liquid crystal panel using the same Expired - Fee Related JP3531415B2 (en)

Priority Applications (1)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10451897A JP3531415B2 (en) 1997-04-22 1997-04-22 SOI substrate, method of manufacturing the same, semiconductor device and liquid crystal panel using the same

Publications (2)

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US6358759B1 (en) * 1999-07-16 2002-03-19 Seiko Epson Corporation Method for manufacturing electro-optical device, electro-optical device, and electronic equipment
JP3889533B2 (en) 1999-09-22 2007-03-07 シャープ株式会社 Liquid crystal display device and manufacturing method thereof
US6661025B2 (en) 2000-09-22 2003-12-09 Seiko Epson Corporation Method of manufacturing electro-optical apparatus substrate, electro-optical apparatus substrate, electro-optical apparatus and electronic apparatus
JP4843840B2 (en) * 2000-09-25 2011-12-21 セイコーエプソン株式会社 Electro-optical device substrate manufacturing method, electro-optical device substrate, electro-optical device, and electronic apparatus
JP3909583B2 (en) 2001-08-27 2007-04-25 セイコーエプソン株式会社 Manufacturing method of electro-optical device
US7119365B2 (en) 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
JP4772258B2 (en) * 2002-08-23 2011-09-14 シャープ株式会社 Manufacturing method of SOI substrate
US7192812B2 (en) 2002-12-20 2007-03-20 Seiko Epson Corporation Method for manufacturing electro-optical substrate
US8130335B2 (en) 2007-02-13 2012-03-06 Seiko Epson Corporation Electro-optic substrate, electro-optic device, method of designing the electro-optic substrate, and electronic device
US8110832B2 (en) 2007-02-22 2012-02-07 Seiko Epson Corporation Electro-optical substrate, method for designing the same, electro-optical device, and electronic apparatus
JP5396772B2 (en) * 2008-08-11 2014-01-22 セイコーエプソン株式会社 Electro-optical device design method
US8481375B2 (en) 2009-02-05 2013-07-09 Sharp Kabushiki Kaisha Semiconductor device and method for producing the same
WO2011039907A1 (en) 2009-10-02 2011-04-07 シャープ株式会社 Semiconductor device and manufacturing method therefor
JP2016053722A (en) * 2015-10-20 2016-04-14 株式会社半導体エネルギー研究所 Semiconductor device
JP2017004013A (en) * 2016-09-13 2017-01-05 株式会社半導体エネルギー研究所 Semiconductor device
JP6466614B2 (en) * 2018-06-04 2019-02-06 株式会社半導体エネルギー研究所 Liquid crystal display

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