JPH0587975B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor element provided on a dielectric layer.

Conventional techniques for forming semiconductor elements on dielectric materials include sapphire (A ₂ O ₃ ) and spinel (MgA ₂ O ₃ ).
It has been developed using single-crystal silicon thin films grown on single-crystal dielectric substrates such as so-called SOS substrates. Recently, SOI (Silicon on Insulator), which uses laser annealing technology to form a single crystal silicon film on an amorphous insulating film as an alternative to an SOS substrate, has also been attracting attention. When these SOS or SOI structures are used, the junction can be formed on the dielectric by making the single crystal film as deep as the source/drain junction of a MOS device, thereby reducing junction capacitance and realizing high-speed devices. . Furthermore, when a complementary MOS (CMOS) device is formed, the
There was no need to consider the latch-up phenomenon caused by pnpn thyristors, and the device design had the advantage of being capacitive.

However, on the other hand, epitaxial films formed by heterojunctions have large crystal defect densities due to slight mismatches in lattice constants and differences in thermal expansion coefficients with the substrates, and leakage current of devices formed thereon. There were also drawbacks that degraded characteristics and high speed. Furthermore, since conventional SOS and SOI structures are completely dielectrically isolated, it is usually difficult to form wiring on the substrate itself from the surface. This causes the substrate to be electrically floating, causing hysteresis in current-voltage characteristics and kink phenomenon. This is thought to cause major problems in high-speed operation, stability, and reliability when element dimensions become finer and power supply voltage decreases.

An object of the present invention is to provide a method for manufacturing a semiconductor device having a new SOI structure that maintains the advantages of conventional SOS and SOI and solves their problems.

In order to achieve the above object, the present invention includes a step of forming an amorphous insulating film on a semiconductor substrate, opening a window in a semiconductor element region, and forming a selective epitaxial layer only on the exposed semiconductor substrate. forming a semiconductor element on the selective epitaxial layer, bonding the surface on which the semiconductor element is to be formed to a holding substrate with an adhesive (A), and pressing the semiconductor substrate until the amorphous insulating film is exposed; After removing the adhesive while polishing it from the back side, and then depositing an insulating film on the removed surface at a temperature lower than the melting point of the adhesive (A),
A process of opening a window in the area where the wiring is to be made, a process of forming the wiring, and applying an adhesive (B) to the surface where the wiring is to be formed.
A step of fixing it to a support substrate via a step is provided.

The difference between the conventional structure and the structure formed by the present invention will be described in more detail using figures. Figure 1 is a cross-sectional view schematically showing an example of a conventional SOI structure.
2 is a substrate, 2 is an amorphous insulating film such as SiO ₂ film, 3 is a single crystal silicon film, 4 is a gate oxide film, 5 is
A frequently used structure is polycrystalline silicon for a gate electrode, 6 and 7 a drain and source region, respectively, and 8 an interlayer insulating film. Here, the bottoms of the drain and source regions are separated by an insulating film 2, which contributes to reducing parasitic capacitance, but the potential of the substrate 3 of the transistor is in a floating state. FIG. 2 is a cross-sectional view schematically showing the structure of the present invention. 11 is a substrate, 12 is an element isolation region, 13 is a silicon single crystal, 14 is a gate oxide film, 15 is polycrystalline silicon for gate electrode, 16 and 17 are drain and source regions, respectively, 18 is an interlayer insulating film, and 19 is a conductive film. and 20 indicate the adhesive material. Source/drain regions 16 and 1
7 is not separated by an insulating film, but is characterized in that a wiring 19 is in ohmic contact with the silicon single crystal 13, and by applying a voltage from this wiring, the potential of the substrate 13 of the element is It is fixed at a certain applied voltage or ground voltage, and stable characteristics can be obtained like elements formed on ordinary semiconductor substrates. Isolating the source/drain regions with an insulator can be easily achieved by making the thickness of the insulating film 12 in the field region approximately the same as the depth of the source/drain diffusion.

By using the present invention, substrate wiring can be performed without damaging the complete dielectric isolation structure that is a feature of SOS and SOI, and the semiconductor layer can be formed using an epitaxial layer using a bulk semiconductor substrate as a seed crystal. Therefore, the essential crystal defect density is comparable to that of the bulk. Furthermore, since the selective epitaxial film is formed so as to be flat with the surface of the field insulating film, there are few steps, the shape of the surface wiring is extremely good, and the yield is high. By applying the present invention to the manufacture of CMOS devices, it has various advantages such as high carrier mobility and low leakage characteristics that can be obtained in bulk, and the possibility of wiring on a substrate, and also provides a latch that can only be realized with SOI. Because it has the feature of being startup-free, it is possible to obtain a CMOS device with superior high speed and low power consumption.

Next, an example will be described using figures. Figure 3a,
b, c, d, and e are schematic cross-sectional views of the manufacturing process using a CMOS inverter as an example.

P-type silicon substrate 31 with (100) plane orientation
A thermal oxide film 32 having a thickness of approximately 2 μm is formed on the substrate, and the thermal oxide film 32 in the element region is etched away by photolithography and dry etching. Thereafter, hydrogen chloride gas (HC) is added to an atmosphere containing dichlorosilane (SiH ₂ C ₂ ) as a source gas and hydrogen as a carrier gas at 950° C., and is selectively heated so as not to deposit on the amorphous insulating film 32. Then, a p-type epitaxial film 33 is grown only in the element region. Next, using the resist as a mask, phosphorus ions are implanted only into the p-channel device region, and by indentation at 1100°C for 20 hours, an n-type region (n-well) with a depth of approximately 3 μm is formed.
34 is formed, and FIG. 3a is obtained.

Next, a gate oxide film 35 is formed, and an impurity layer 36 is controlled and introduced by ion implantation so that a predetermined threshold voltage value is obtained. Conductive polycrystalline silicon is deposited by CVD, and gate electrode 37 is formed by photolithography. followed by n
An n-type impurity such as arsenic is implanted into the channel region, and a p-type impurity such as boron is implanted into the p-channel region at a high concentration by ion implantation to form source/drain regions 38 and 39, respectively.

Next, an interlayer insulating film 40 is deposited by CVD, contact holes are formed, and then aluminum is deposited by vacuum evaporation. A metal wiring 41 is formed using photolithography, and an interlayer insulating film 42 is deposited again to obtain the structure shown in FIG. 3B.

An adhesive 43 such as an epoxy resin is applied on the interlayer insulating film 42, and a holding substrate 4 such as a glass plate is attached.
4. Glue and fix. Subsequently, the silicon substrate 31 is etched and mechanochemically polished.
When removed flatly from the back surface using the field insulating film 32 as a stopper, the image shown in FIG. 3c is obtained.

Next, an interlayer insulating film 42 is further deposited at a low temperature, contact holes are formed, and then a second aluminum layer is deposited to form wiring electrodes 45 by photolithography. After protecting the surface with an interlayer insulating film 42, the structure shown in FIG. 3D is obtained by adhesively fixing it to another holding substrate 47 via, for example, a low melting point glass 46.

After removing the holding substrate 44 by etching or polishing and then removing the adhesive 43 using a suitable organic solvent, FIG. 3e is obtained. Thereafter, an appropriate heat treatment is performed to alloy the aluminum and remove the protective film in the bonding area, thereby completing the process.

Furthermore, although aluminum wiring is used in the embodiment, the effectiveness of the present invention remains unchanged even if polycrystalline silicon, metal silicide, or other metals are used as conductors. Furthermore, in addition to silicon, semiconductor substrates of compounds such as gallium arsenide and indium phosphide can also be used as semiconductors.

[Brief explanation of the drawing]

1 is a schematic cross-sectional view of a semiconductor device having a conventional SOI structure, and FIG. 2 is a schematic cross-sectional view of a structure according to the present invention shown in contrast to FIG. 1. Third
Figures a, b, c, d, e show embodiments of the present invention.
FIG. 3 is a schematic cross-sectional view of a semiconductor device manufacturing process showing a CMOS inverter in the order of steps. Numbers in the diagram are 1, 31...silicon substrate, 2
...Amorphous insulating film, 12,32...Field oxide film, 3...Single crystal silicon, 13,33...Selected epitaxial layer, 34...N well, 4,1
4, 35... Gate oxide film, 36... Ion implantation layer for threshold voltage adjustment, 5, 15, 37... Polycrystalline silicon gate wiring, 6, 16, 7, 17...
...source or drain region, 38...source/drain region of n-channel element, 39...source/drain region of p-channel element, 8, 18, 4
0,42...Interlayer insulating film, 41...Metal wiring, 1
9,45... Wiring according to the present invention, 20,46...
Adhesive layer such as low melting point glass, 11, 44, 47...
Holding plate, 43...adhesive, respectively.

Claims (1)

[Claims] 1. A step of forming an amorphous insulating film on a semiconductor substrate and opening a window in a semiconductor element region, a step of forming a selective epitaxial layer only on the exposed semiconductor substrate, and a step of forming a semiconductor layer on the selective epitaxial layer. a step of forming an element, a step of adhering the formation surface of the semiconductor element to a holding substrate with an adhesive (A), and removing the semiconductor substrate while polishing it from the back side until the amorphous insulating film is exposed; Next, after depositing an insulating film on the removed surface at a temperature lower than the melting point of the adhesive (A), a step of opening a window in the area where wiring is to be made, a step of forming wiring, and a step of depositing the wiring forming surface with adhesive. A method for manufacturing a semiconductor device, comprising the step of fixing it to a support substrate via (B).