JPH0621205A - Dielectric isolation substrate and semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To solve the problem of the bonding defect of a semiconductor single- crystal wafer as a support body in conventional cases regarding the manufacturing method of a semiconductor integrated circuit device (power IC) having a dielectric isolation substrate and of a dielectric isolation substrate used to manufacture it. CONSTITUTION:A semiconductor integrated circuit device is formed of a dielectric isolation substrate having a structure composed of the following: a polycrystalline semiconductor layer 601 which buries a groove used to isolate a single-crystal island 3 forming an element; an SiO2 layer 7 which corrects and flattens uneven parts on the face of the polycrystalline layer and whose thickness is 20 to 2000nm; and a semiconductor single-crystal support body 5. Thereby, a perfect single-crystal wafer support body can be bonded firmly by the SiO2 layer having a definite thickness range, and the production yield of the semiconductor integrated circuit device is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric isolation substrate, and more particularly to a dielectric isolation substrate having a support made of single crystal silicon, a method of manufacturing the same, and a semiconductor integrated circuit device using the dielectric isolation substrate. It is about.

[0002]

2. Description of the Related Art Withstand voltage between elements is several tens of volts to several hundreds.
V and a large high voltage integrated circuit device (power IC),
Each element to be integrated is connected to a dielectric film (eg, SiO ₂
A method of completely separating with an insulating film such as a film) is used, and a dielectric isolation substrate manufactured by processing a normal semiconductor single crystal wafer is used for its production.

FIG. 2 is an explanatory view (cross-sectional view and perspective view) of a manufacturing process of a dielectric isolation substrate and a power IC. At the beginning,
The main surface of a single crystal silicon wafer 301 (for example, a diameter of 5 inches and a thickness of 600 μm) is oxidized and the entire surface thereof is SiO ₂
After forming the film 15 and patterning it by a photolithographic method, the SiO ₂ film 15 at a predetermined position is opened by a method such as etching. Next, the remaining SiO ₂
Using the film 15 as a mask, the separation groove 6 having a depth of about 60 μm is formed by anisotropic etching using, for example, a mixed solution of potassium hydroxide and isopropyl alcohol (FIG. 7A). The SiO ₂ film 15 used as the mask is removed, the main surface of the wafer 301 is oxidized again, and an insulating SiO ₂ film 2 having a thickness of about 1.2 μm is formed on the entire surface (FIG. 2B). A polycrystalline silicon layer 602 is formed on the surface thereof by a high temperature vapor phase growth method (CVD: formation temperature of about 1200 ° C., formation rate of about 5 μm / min) to fill the separation groove 6, and the same thickness as the wafer (about 600 μm). It is deposited ((c) in the same figure). Asperities on the surface of the deposited polycrystalline silicon layer 602 (formed because the separation groove 6 is deep) are formed on the single crystal wafer 30.
The lower surface of No. 1 is used as a reference for smoothing ((d) of the same figure). Next, on the contrary, the unnecessary portion of the single crystal wafer 301 is removed by a method of grinding or polishing with reference to the surface side of the polycrystalline silicon layer 602 having no unevenness, and the single crystal islands each separated by the SiO ₂ film 2 are removed. 3 is formed to complete the dielectric isolation substrate 101 ((e) in the figure).

Dielectric isolation substrate 1 produced in this way
01 is treated in the same manner as a silicon single crystal wafer used for manufacturing an ordinary LSI, a desired semiconductor element is formed on the single crystal isolation island 3 by the semiconductor element manufacturing process, and wiring between elements is performed by a metal thin film (see FIG. (Not shown), a large number (several hundreds) of pellets (for example, several tens to several 1) in the substrate
00 mm ² ) is created ((f) in the same figure). In this case, in recent years, as the integration of devices in power ICs has increased (several hundreds), the processing size has been miniaturized, and the smaller the initial curvature of the dielectric isolation substrate and the change in curvature during the process, the smaller the photolithography process. The alignment accuracy in the case of patterning can be improved and the manufacturing yield of the device can be increased. After cutting the wafer after element formation into pellets one by one,
The semiconductor integrated circuit device (power IC) is completed by welding to a metal base (lead frame), wiring to the connection pins, and protecting the whole with resin (FIG. 9 (g)).

As is well known, the conventional dielectric isolation substrate is the polycrystalline silicon layer 60 shown in FIG. 2 (e).
Many of them have a composite structure in which a plurality of single crystal silicon islands 3 for forming a semiconductor element are formed on the surface of a support made of 2 via a dielectric film 2. In such a dielectric isolation substrate having a composite structure, the substrate may be warped (curved) or distorted due to the difference in thermal expansion coefficient between the single crystal silicon in the isolation island 3 portion and the polycrystalline silicon 602 layer in the support portion. However, there was a problem that the grain size of the polycrystal was changed by the heat treatment for forming the element and the curvature was greatly changed. Therefore, as a dielectric isolation substrate for solving these problems, for example, Japanese Patent Laid-Open No. 53-3359.
No. 0, JP-A-63-62252, and JP-A-3.
No. 265153, etc., and the basic structure of the cross section is shown in FIG. 3, the support is made of single crystal silicon, and the single crystal silicon wafer to be the support and the single crystal island is provided with a SiO ₂ film interposed therebetween. A structure in which they are joined together (hereinafter referred to as a joining structure) has been used.

In FIG. 3, a semiconductor element 4 is formed in an island-shaped single crystal silicon region 3, and the single crystal island 3 is insulated from each other by a dielectric film 2 on a surface of a support 5 made of single crystal silicon. It is formed in the formed state. Polycrystalline silicon 601 is formed in the isolation trench 6 adjacent to each single crystal silicon island region 3 insulated by the dielectric film 2, and the single crystal islands 3 are connected to each other. The thickness of polycrystalline silicon 601 may be set to the minimum thickness at which isolation trench 6 is filled. The single crystal island 3 connected by the polycrystalline silicon 601 in the separation groove 6 is the SiO ₂ film 7.
It is bonded to the single crystal silicon support 5 through.

Hereinafter, a method of manufacturing a dielectric separated substrate having such a junction structure will be described with reference to the sectional view shown in FIG. First, about 60 μm on the main surface of the single crystal silicon wafer 301.
After forming the isolation trench 6 of 1., an insulating SiO ₂ film 2 having a thickness of about 1.2 μm is formed on the entire surface, and a polycrystalline silicon layer 601 is deposited to a thickness of about 100 μm until the isolation trench 6 is completely filled. (a)). The steps up to this point are the same as the steps shown in FIG. 2 except that the amount of polycrystalline silicon deposited is smaller than in the conventional method. Then, a large recess of the deposited polycrystalline silicon layer 601 formed immediately above the separation groove 6 is removed by mechanical cutting (grinding) or the like, and further, by a mechanochemical polishing method having both physical polishing and chemical etching. The fine irregularities are removed to form a smooth surface (FIG. 2 (b)). S on the surface
A single crystal silicon wafer serving as the support 5 on which the iO ₂ film 7 is formed is prepared, and its surface and the polycrystalline silicon layer 601 are prepared.
The polished surfaces of 1 are bonded together by an appropriate method, and a high temperature heat treatment is applied to bond the two wafers (FIG. 7C). As a method for joining the above-mentioned two semiconductor wafers, for example, there is a method described in JP-A-62-27040. Finally, as in the case of FIG. 2, the unnecessary portion of the single crystal silicon wafer 301 is removed by polishing to form the single crystal isolation island 3 to complete the dielectric isolation substrate 1 (FIG. 2D). The subsequent power IC manufacturing process is the same as the process shown in FIG.

[0008]

In the above-mentioned conventional example, since the thickness of the SiO ₂ film 7 formed at the bonding interface is insufficiently considered, the bonding of the support wafer 5 is likely to be incomplete. There was a problem. If perfect wafer bonding is not achieved, the bonding force will be weak. In a power IC manufactured by forming an element on such a semiconductor single crystal isolation island, the isolation island is supported by a thermal cycle generated by the operation or non-operation of the element. It may be moved or peeled off, and a defect such as a disconnection trouble of a wiring connecting elements may occur.

Further, the conventional dielectric isolation substrate is liable to be bent (several hundred μm), and is subjected to microfabrication (processing dimension is about 3 μm or less), which is required by the photolithography process of the number 1
Another problem is that it is difficult to obtain a substrate with a low curvature of about 0 μm or less.

According to experiments, the present inventors found that the support wafer 5
The main cause of the bonding failure is the minute unevenness on the polished surface of the polycrystalline layer caused by the effect of the deep separation groove, and the difference in thermal expansion coefficient between the SiO ₂ film at the bonding interface and the polycrystalline silicon filling the separation groove. Is estimated to be due to residual stress that occurs during
It was also found that the reason why it is difficult to reduce the substrate curvature to several tens of μm or less is that a warp occurs due to the difference in the coefficient of thermal expansion between the dielectric film formed at the bonding interface and the support.

An object of the present invention is to solve the above-mentioned problems and to complete a wafer bonding and to provide a small curvature in a dielectric isolation substrate, a manufacturing method thereof, and a disconnection using the dielectric isolation substrate. Power I with no trouble and high reliability
To provide C.

[0012]

SUMMARY OF THE INVENTION In order to solve the above problems and realize perfect wafer bonding, the present invention provides a semiconductor single crystal support and a main surface of the semiconductor single crystal support. Buffer layer, a polycrystalline silicon layer adjacent to the buffer layer, and a plurality of semiconductor single crystal components formed on the surface of the polycrystalline silicon layer and insulated from each other by the dielectric film. A dielectric isolation substrate comprising: a remote island, wherein the buffer layer is a silicon oxide film (SiO ₂ ) layer having a thickness of approximately 20 to 2000 nm.

The present invention also provides a step of forming a dielectric film on one main surface of a semiconductor single crystal wafer having a separation groove on one main surface, and at least until the separation groove is filled.
Forming a polycrystalline silicon layer on the dielectric film;
A step of substantially smoothing the polycrystalline silicon layer, and a step of smoothing the polycrystalline silicon layer with a semiconductor single crystal support having a buffer layer formed of a silicon oxide film (SiO ₂ ) layer having a thickness of approximately 20 to 2000 nm. A dielectric isolation substrate having a step of bonding to a surface and a step of polishing the other main surface of the semiconductor single crystal wafer into semiconductor single crystal islands separated into a plurality of semiconductor single crystal wafers by the dielectric film. Is a manufacturing method. Here, the buffer layer made of a silicon oxide film (SiO ₂ ) layer is preferably formed by oxidizing the semiconductor single crystal support.

Further, according to the present invention, a step of forming a dielectric film on one main surface of a semiconductor single crystal wafer having a separation groove on one main surface, and at least until the separation groove is filled,
Forming a polycrystalline silicon layer on the dielectric film;
A step of substantially smoothing the polycrystalline silicon layer, and a step of forming a silicon oxide film (Si) on the substantially smooth surface of the polycrystalline silicon layer.
A step of forming a buffer layer composed of an O ₂ ) layer and polishing the surface to make the surface smooth in a range of about 20 to 2000 nm; and bonding the semiconductor single crystal support to the smoothed buffer layer surface. And a step of polishing the other main surface of the semiconductor single crystal wafer to form the semiconductor single crystal wafer into semiconductor single crystal islands separated into a plurality of semiconductor single crystal wafers by the dielectric film. Is. Here, the buffer layer formed of a silicon oxide film (SiO ₂ ) layer is preferably formed by oxidizing the polycrystalline silicon layer.

Further, the present invention comprises a metal base, a pellet provided on the base, wiring for connecting the element formed on the pellet and the connection pin, and a resin for protecting each member. A semiconductor integrated circuit device, wherein the pellets are formed of the dielectric component substrate.

[0016]

According to the above-mentioned structure, minute irregularities on the bonding surface, which are substantially smoothed by filling the separation groove with the polycrystalline semiconductor layer and polishing,
Fluidization of a sufficient amount of the SiO ₂ film during the high temperature heat treatment provides a smooth surface so that a strong bond can be obtained. In addition, since bonding can be achieved with a minimum amount of the SiO ₂ film, there is substantially no bending or distortion. No support bonding is possible.

Further, since the joint strength is sufficiently large when the complete support can be joined, a power IC using this junction-type dielectric isolation substrate has a wiring disconnection due to a thermal cycle caused by the operation or non-operation of the element. Problems such as troubles will disappear.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to the sectional view shown in FIG. In this case, silicon (Si) was used as the semiconductor material. First, diameter 5 inches, thickness 6
A silicon single crystal wafer 301 of 00 μm is prepared.
Using this SiO ₂ film (see FIG. 2 (a)) formed by oxidizing this wafer as a mask, anisotropic etching is performed using, for example, a mixed solution of potassium hydroxide and isopropyl alcohol, and the separation groove 6 of about 60 μm is dug. , A region 3 which becomes a single crystal island is formed. After removing the remaining SiO ₂ film, it is oxidized again to form an insulating SiO ₂ film 2 of about 1.2 μm.
Then, a polycrystalline silicon layer 601 is formed by CVD to a thickness of about 100 μm until the isolation trench 6 is filled (FIG. 8A). After that, the polycrystalline silicon 601 layer is mechanically cut to eliminate large depressions due to the separation grooves 6, and is further flattened by the mechanochemical polishing method to eliminate fine irregularities (FIG. 2B). A single crystal silicon wafer having a SiO ₂ film 7 in the range of about 20 nm to 2000 nm as a support 5 is prepared, and the surface and the polished surface of the polycrystalline silicon layer 601 are bonded together by an appropriate method. A high temperature heat treatment is applied to bond the two wafers (FIG. 7C).

FIG. 5 is a result of examining the relationship between the in-wafer area ratio of the unbonded portion (void) generated in the bonded wafer by the above-mentioned high temperature heat treatment and the film thickness of the SiO ₂ film 7 formed on the support. is there. In order to eliminate the generation of voids, it is necessary to form the SiO ₂ film 7 having a thickness of at least 20 nm on the support 5. It is estimated that this is due to the following reasons.

The surface on which the support wafer 5 is bonded is separated by the separation groove 6.
Polycrystalline silicon 601 is deposited until it is completely filled up. First, a large recess formed by the influence of the separation groove 6 is made flat by a mechanical cutting method (grinding), and then the minute unevenness remaining on this surface is physically removed. The surface is smoothed with higher precision by the mechanochemical polishing method that has both high polishing and chemical etching effects (see FIG. 4). However, FIG.
As shown in (a), the interface 16 where the crystal grains collide exists in the separation groove 6 region, and the crystal plane orientations of the planes orthogonal to the crystal growth direction tend to be the same (orientation). Since the surface orientation is different at the bottom of the single crystal island 3 and the like, the chemical etching rate in the region of the separation groove 6 is higher than that of other portions, and as a result, the separation groove 6 is formed on the bonding surface.
Irregularities are formed in the region that is about 20 nm lower than the bottom of the island (FIG. 6B).

The results shown in FIG. 5 indicate that in order to completely bond the support wafer 5 to the surface having irregularities of about 20 nm, an amount of SiO ₂ layer 7 which flows by high temperature heat treatment and fills at least the irregularities remaining on the bonding surface. It indicates that it is necessary.

On the other hand, increasing the thickness of the SiO ₂ layer 7 more than necessary is limited in the following points.

The dielectric isolation substrate is made of SiO for insulating and isolating the single crystal islands 3 as shown in the sectional view of FIG. 2 (e).
_{Since the two} layers 2 are formed only in the vicinity of the surface by several μm, the support wafer 5 (single crystal silicon) having a larger expansion coefficient than that of SiO ₂ contracts and bends in a direction in which the surface side of the substrate is convex. Further, in the process of forming the element, a relatively thick SiO ₂ layer is formed on the single crystal island 3 for patterning the element.
It is formed on the surface and is further curved by the SiO ₂ layer in a direction in which the surface side is convex. Si formed on the support 5
The O ₂ layer 7 is also near the surface at the substrate cross-section position, and acts to increase the curvature of the substrate in the same direction. If the curvature of the substrate caused by such a cause is large, it hinders the photolithographic processing of fine elements.

FIG. 7 shows the junction interface S of the junction type dielectric isolation substrate.
The relationship between the iO ₂ layer thickness and the defect rate in the photolithography process was experimentally investigated. In order to obtain a high product yield, the thickness of the bonding interface SiO ₂ layer should be approximately 2000 nm.
It has been found that it is necessary to reduce the curvature of the substrate as follows.

When the thickness of the SiO ₂ layer 7 is increased, another problem occurs. The line (20) in FIG. 8 is -70.
The relationship between the defect (wiring disconnection) rate in the heat cycle test of ° C / + 150 ° C and the bonding interface SiO ₂ layer 7 is shown. If the thickness of SiO ₂ becomes thicker than necessary, the defect rate increases. This is because although a large strain remains in the polycrystal layer 601 sandwiched from the isolation island bottom side and the joint interface side by SiO ₂ whose expansion coefficient is smaller than that of metallic Si by one digit or more, the joint interface SiO ₂ layer 7 It is considered that when the thickness is thick, the residual stress becomes larger and the joint surface is broken by the thermal shock of the heat cycle test. The line (30) in FIG. 8 indicates the characteristic defect rate of the element and the bonding interface SiO in the high temperature reliability test.
It is the result of examining the relationship with the _second layer 7. In this case as well, the thicker the bonding interface SiO ₂ layer 7 is, the more defective the characteristics are. This is because the heat generated during the operation of the element is radiated through the metal base shown in FIG. 2 (g), but since the thermal conductivity of SiO ₂ is smaller than that of Si, the thickness of the SiO ₂ layer below the element is small. It is presumed that the larger the ratio, the smaller the heat dissipation rate, and the lower the device characteristics. From the above experiment, in order to obtain the power IC with a high yield, as shown by the line (40) in FIG. 8 synthesized by the lines (20) and (30), the bonding interface Si
It is understood that the thickness of the O ₂ layer 7 needs to be about 2000 nm or less.

[0026] In case of bonding a support wafer directly through the SiO ₂ film, the following points as reasons optimization other required thickness range of the SiO ₂ film. As a method of removing the recess of the polycrystalline silicon 601 by a method such as cutting and flattening it by polishing, and then joining it to the support 5 through the SiO ₂ film 7, there is a method between the polycrystalline silicon 601 and the support 5. There is a method of applying a voltage for bonding (anodic bonding method). In this case, if the thickness of the SiO ₂ film 7 is thin, a short circuit will occur between the polycrystalline silicon and the support. On the other hand, if it is thick, the resistance of the SiO ₂ film increases and the voltage required at the bonding interface cannot be applied. As a result of the experiment, it was found that the strongest bonding was achieved when the thickness of the SiO ₂ film 7 was in the range of 20 nm to 2000 nm.

Finally, the unnecessary portion of the single crystal silicon 301 of the wafer to which the single crystal silicon wafer to be the support 5 is bonded is removed by polishing to form the single crystal separation island 3 as shown in FIG. 1 (d). The dielectric isolation substrate 1 is completed. After that, desired elements are formed on the isolation island 3 by a normal semiconductor manufacturing process, and then wiring is performed between the respective elements to form the wiring shown in FIG.
The pellet shown in is completed.

Next, another embodiment of the present invention will be described with reference to FIG. A single crystal wafer is prepared, a separation groove 6 is dug in this, an insulating SiO ₂ film 2 is formed on this surface, the groove 6 is filled with polycrystalline silicon 601, and is flattened by polishing (see FIG. )). The steps up to this point are the same as those in the embodiment shown in FIG. Next, a SiO ₂ layer 7 is formed on this surface by an oxidation treatment performed in a high temperature (about 700 ° C. or higher) steam atmosphere or a vapor phase chemical reaction (CVD) method (FIG. 2B). In this case, the SiO ₂ layer 7 is formed to have a thickness equal to or larger than the unevenness of the bonding surface of about 20 nm caused by the difference in the polishing rate of the mechanochemical polishing between the isolation groove 6 region and the island bottom. For the same reason as in the above-mentioned embodiment, the upper limit of the thickness of the SiO ₂ layer 7 is selected within the range of 2000 nm or less.

Thereafter, the irregularities remaining on the surface of the formed SiO ₂ layer 7 are subjected to mechanochemical polishing to smooth the joint surface. Since the SiO ₂ layer 7 is a homogeneous amorphous material having no grain boundaries, a smooth surface capable of achieving perfect bonding can be easily obtained.
Then, a single crystal wafer to be the support 5 is bonded to this surface (FIG. 7C). In this case, the surface of the support 5 is Si
0 ₂ layers even without because one bonding surface is smooth,
A perfect support bond can easily be achieved. In addition, it is natural that perfect bonding can be achieved even by using a support wafer having a SiO ₂ layer. In this case the upper limit of the thickness of the Si0 ₂ layer regulates Si0 ₂ layer thickness of the support wafer so that the range of 2000 nm. After that, polishing is performed for separating the single crystal islands 3 to complete the dielectric isolation substrate 1 in the same manner as in the above-described embodiment (FIG. 3D).

In this embodiment, the case has been described as an example where a semiconductor single crystal wafer having a small curvature is used as the support. Even when a member such as a semiconductor single crystal wafer, quartz, or silicon carbide that causes less contamination in the semiconductor process and has a countermeasure against the occurrence of bending is used, the same effect as that of the present embodiment can be obtained.

According to the embodiment described above, the optimum amount of S
The i0 ₂ layer eliminates the irregularities on the polished surface of the polycrystalline layer, and the residual stress at the bonding interface is substantially small, so that the support can be easily bonded to obtain a dielectric isolation substrate.

[0032]

As described above, according to the present invention, the bonding of the support wafer in the dielectric isolation substrate having the bonding structure is completely achieved, so that it is possible to provide a highly reliable dielectric isolation substrate. Further, by using the dielectric isolation substrate having such a structure, the power I having high integration and high reliability can be obtained.
C can be provided.

[Brief description of drawings]

1A to 1D are cross-sectional views for explaining a method of manufacturing a dielectric isolation substrate according to an embodiment of the present invention in the order of steps.

2A to 2G are cross-sectional views and perspective views for explaining a conventional method for manufacturing a dielectric isolation substrate and an integrated circuit device in the order of steps.

FIG. 3 is a cross-sectional view illustrating a conventional dielectric isolation substrate having a junction structure.

4A to 4D are cross-sectional views for explaining a conventional method for manufacturing a dielectric isolation substrate in the order of steps.

FIG. 5 is a diagram for explaining the relationship between the unbonded area in the wafer and the thickness of the SiO ₂ layer.

6 (a) and 6 (b) are cross-sectional views for explaining a crystal structure of a polycrystalline layer in a separation groove of a dielectric separation substrate.

FIG. 7 is a diagram for explaining the relationship between the defect rate and the SiO ₂ layer thickness in the photolithography process.

FIG. 8 is a diagram for explaining a relationship between a defective rate and a SiO ₂ layer thickness in a heat cycle test and a high temperature reliability test.

FIG. 9 is a cross-sectional view for explaining a method of manufacturing a dielectric isolation substrate according to another embodiment of the present invention in the order of steps.

[Explanation of symbols]

1 Dielectric Separation Substrate 2 Dielectric Film 3 Semiconductor Single Crystal Separation Island 301 Single Crystal Silicon Wafer 4 Semiconductor Element 5 Semiconductor Single Crystal Support 6 Separation Groove 601 Polycrystalline Semiconductor Layer 602 Polycrystalline Silicon Layer 603 Second Polycrystalline Silicon Layer 7 Si0 ₂ layer (buffer layer)

Claims (6)

[Claims] 1. A support, a buffer layer formed on a main surface of the support, a polycrystalline silicon layer adjacent to the buffer layer, a plurality of polycrystalline silicon layers, and a dielectric film. And a semiconductor single crystal isolation island insulated from the polycrystalline silicon, and the buffer layer is a silicon oxide film (SiO ₂ ) layer having a thickness of about 20 to 2000 nm. Dielectric isolation substrate. 2. A step of forming a dielectric film on one main surface of a semiconductor single crystal wafer having a separation groove on one main surface, and a polycrystalline film on the dielectric film at least until the separation groove is filled. A step of forming a silicon layer, a step of substantially smoothing the polycrystalline silicon layer, and a silicon oxide film (SiO 2) having a thickness of about 20 to 2000 nm.
₂ ) bonding a support having a buffer layer consisting of a layer to the smooth surface of the polycrystalline silicon layer; polishing the other main surface of the semiconductor single crystal wafer to form the semiconductor single crystal wafer with the dielectric layer. And a step of forming a semiconductor single crystal island separated into a plurality of pieces by a body film. 3. The dielectric isolation substrate manufacturing method according to claim 2, wherein the buffer layer made of a silicon oxide film (SiO ₂ ) layer is formed by oxidizing the support. Method for manufacturing separation substrate. 4. A step of forming a dielectric film on one main surface of a semiconductor single crystal wafer having a separation groove on one main surface, and a polycrystalline film on the dielectric film at least until the separation groove is filled. A step of forming a silicon layer, a step of substantially smoothing the polycrystalline silicon layer, and a step of forming a buffer layer composed of a silicon oxide film (SiO ₂ ) layer on a substantially smooth surface of the polycrystalline silicon layer, and then the surface thereof To smooth the surface in a thickness range of about 20 to 2000 nm, to bond the support to the smoothed buffer layer surface, and to polish the other main surface of the semiconductor single crystal wafer by polishing. And a step of forming a semiconductor single crystal wafer into semiconductor single crystal islands separated by the dielectric film into a plurality of semiconductor single crystal islands. 5. The method for manufacturing a dielectric isolation substrate according to claim 4, wherein the buffer layer made of a silicon oxide film (SiO ₂ ) layer is formed by oxidizing the polycrystalline silicon layer. Manufacturing method of dielectric isolation substrate. 6. A semiconductor integrated circuit comprising a metal base, a pellet provided on the base, a wiring for electrically connecting an element formed on the pellet and a connection pin, and a package for protecting each member. A semiconductor integrated circuit device, wherein the pellet is formed of the dielectric component substrate according to claim 1.