JP2678218B2 - Bonded substrate and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor-bonded substrate for a silicon-based or compound-based individual semiconductor device, an integrated circuit device or the like and a method for manufacturing the same, and particularly to a high breakdown voltage or large current integrated circuit device. A dielectric isolation substrate,
SOI (Silicon On Ins) used for electrical noise countermeasures
and a method for manufacturing the same.

[0002]

2. Description of the Related Art A method for directly adhering a supporting substrate and an element forming substrate to integrate them is disclosed in JP-A-48-715.
No. 80 publication is mentioned. Further, as a method relating to the case where an element forming substrate is attached to a supporting substrate and then the element forming substrate is ground and polished to a desired thickness, there is disclosed in Japanese Patent Laid-Open No.
202024 publication is mentioned.

[0003]

Among the above-mentioned conventional techniques, in the technique disclosed in Japanese Unexamined Patent Publication (Kokai) No. 48-71580, a supporting substrate and an element forming substrate in a region of about 1 to 10 mm around the substrate are formed. The adhesive force is smaller than that in the vicinity of the center, and there is a problem in that after the element forming substrates are bonded, or when the substrate is ground or polished to a desired thickness, it is peeled off at a portion having a small adhesive force. This is a general chamfering work to finish the taper-like polishing on the end face part as a measure to prevent chipping and cracking of the end face of the silicon substrate when manufacturing the silicon substrate, and a mirror finishing work on the surface. In the chamfered area on the outer periphery of the surface and in the area beyond the chamfered area, smooth unevenness and inclination of about several tens of liters are generated. Therefore, when the substrates are directly bonded to each other, a gap formed by the chamfering and a minute gap on the inner diameter side are formed on the side wall of the base body. As a result, it is considered that a portion having a small adhesive force is generated. The portion having a small adhesive force is empirically within a range of about 5 mm. Therefore, as shown in FIG. 13, after the element forming substrate 11 is attached to the supporting substrate 21, or after the substrate is ground and polished to a desired thickness, the corner portion (range of about 10 mm) around the substrate is fixed at a constant angle. The taper part 71 is formed by polishing with 10
About mm was cut and removed. Therefore, the acquisition rate of semiconductor devices in the same substrate is significantly reduced.

On the other hand, according to the technique disclosed in Japanese Unexamined Patent Publication No. 2-202024, as shown in FIG. 14, after a gap 72 is provided around the element forming substrate 12 and the substrates are bonded together, an organic substance-based or SOG 32 is provided in the gap. Is embedded, and this embedded material appears on the ground or polished surface, or the appearance thereof ensures a predetermined thickness. According to this method, the element forming substrate side, that is, the periphery of the substrate which is thinned by grinding and polishing, becomes the region in which the element cannot be formed due to the existence of the gap 72 and the filling material 32. The acquisition rate will decrease. Further, as described above, the adhesive produced by this method is an organic material or SOG.
It is obvious that the adhesive force is smaller than the adhesive force in the vicinity of the center of the substrate, and it is locally peeled off at the time of grinding and polishing as in the known example. In addition, since a high-temperature heat treatment process is performed when forming a semiconductor device, the base material formed by this method is always used after the grinding and polishing.
Is required. Further embedding material 32
If there is a gap in the removed part, a notch will occur at the end of the gap during cleaning or handling, which is a pre-process of high-temperature heat treatment, or when setting on a quartz jig for heat treatment. This causes a reduction in the yield of semiconductor devices due to scattering.

An object of the present invention is to provide a bonded substrate and a method for manufacturing the bonded substrate which are less likely to cause a reduction in the acquisition rate of semiconductor devices and a reduction in the yield of semiconductor devices in the same substrate.

[0006]

In order to achieve the above object, the present invention fills a gap formed in a peripheral edge portion of a bonding surface between substrates in which the peripheral edge portion of the substrate is formed thinner than other portions with an inorganic adhesive material. It is a bonded substrate.

Further, according to the present invention, a first semiconductor substrate having a chamfered peripheral edge, a second substrate bonded to a chamfered side surface of the first semiconductor substrate, and the first semiconductor substrate are provided. A bonded base body, comprising: an inorganic adhesive material filled in a gap formed by the chamfering on a peripheral edge of a surface to be bonded to a second substrate. Here, the first semiconductor substrate is preferably a substrate made of a silicon material. Also,
The second substrate is silicon (Si) based material, carbon (C)
A material selected from a group of materials, an aluminum (Al) group material, a glass group material, and an oxide or a nitride of each of the above materials is preferable. Further, the inorganic adhesive material is preferably a material selected from the group consisting of silicon oxide, silicon nitride, polycrystalline silicon, inorganic silanol-based material, phosphorous glass, boron glass, and lead glass.

According to the present invention, a first semiconductor substrate having a chamfered peripheral edge, a second substrate bonded to a chamfered side surface of the first semiconductor substrate, and a peripheral edge of the second substrate. A bonded base comprising a groove formed in the region and on the surface side in contact with the first semiconductor substrate, and an inorganic adhesive material filled in the groove. Here, the depth of the groove is preferably 5 μm or less.

Further, according to the present invention, a first semiconductor substrate having a chamfered peripheral edge, a second substrate bonded to a chamfered side surface of the first semiconductor substrate, and the first semiconductor substrate are provided. Bonding the peripheral edge portion and the other portion of the joint surface with the second substrate,
A bonded base body, which comprises an adhesive material having fluidity due to thermal energy. Here, the adhesive material is preferably a material selected from the group consisting of inorganic silanol-based materials, phosphorous glass, boron glass and lead glass.

Further, according to the present invention, a step of forming an insulating film on the surface of the first semiconductor substrate having a chamfered peripheral edge, and a step of superposing a second substrate made of an electrically conductive material on the first semiconductor substrate. And a step of filling a gap formed on the side walls of the peripheral edges of both substrates with each other, and a subsequent heat treatment step.

Further, according to the present invention, a step of superposing a first semiconductor substrate having a chamfered peripheral edge and a second substrate made of an electric conductor material, and a filling material in a gap formed on the peripheral side walls of the superposed substrates. And a subsequent heat treatment step.

According to the present invention, the step of removing the chamfered portion of the first semiconductor substrate whose peripheral edge is chamfered to planarize
And a step of adhering a second substrate to the planarized first semiconductor substrate, which is a method for manufacturing a bonded base. Here, the method of removing the chamfered portion is preferably a mechanical flattening method using a polishing material or the like. Further, the method of removing the chamfered portion is preferably a method of flattening by etching with an ionized gas or the like.

The present invention also electrically insulates a supporting silicon substrate, a device forming silicon substrate bonded to the supporting silicon substrate, and an adjacent semiconductor single crystal island formed on the device forming silicon substrate. Separating SiO ₂
In a semiconductor device including a film and an element provided on each semiconductor single crystal island, the bonding structure between the supporting silicon substrate and the element forming silicon substrate is the structure of any one of the above bonded substrates. It is a semiconductor device characterized by the above.

[0014]

Since the element forming substrate side remains in its original shape, that is, single crystal silicon, even if it is embedded with an inorganic adhesive material, there is no reduction in the acquisition rate of semiconductor devices in the same substrate. Further, since the inorganic adhesive material is of the same type as that of the material forming the substrate, no bending or peeling due to the difference in thermal expansion coefficient occurs. Furthermore, since the inorganic adhesive material is of the same type as that of the material constituting the substrate, the adhesive strength is large and the possibility of peeling is small.

[0015]

【Example】

Embodiment 1 FIG. 1 shows an embodiment of the present invention. Si for dielectric isolation on the bottom
Element-forming silicon substrate 1 having a predetermined thickness and having an O ₂ film 3
Is directly bonded to the supporting silicon substrate 2, and a gap 7 is formed around it. The gap 7 is filled with the adhesive material embedding layer 4 made of polycrystalline silicon, and by this emphasis, the substrate 1 and the substrate 2 are firmly bonded from the vicinity of the center to the outer periphery. On the element forming silicon substrate 1, a SiO ₂ film 5 for separating single crystal islands for electrically insulating and separating the adjacent semiconductor single crystal islands 6 is formed. Further, in each semiconductor single crystal island 6, in addition to a diode, a thyristor, etc. formed by a combination of pn junctions, an active element made of a MOS or the like is singly or integrated. The semiconductor device substrate 10 configured as described above is divided into individual semiconductor devices by a dicing device or the like after all active element formation and wiring steps between elements are completed.

Among the divided semiconductor devices, the semiconductor device located around the semiconductor device substrate 10 is located between the dielectric isolation SiO ₂ film 3 and the supporting substrate 2 as shown in FIG. Although the adhesive embedding layer 4 exists, since the adhesive is made of polycrystalline silicon as described above, the adhesive force between the silicon of the supporting substrate 2 and the SiO ₂ film 3 for dielectric isolation is It becomes extremely large and never peels off.

As described above, according to this embodiment, the base 1
Since each semiconductor device 81 located around 0 can be used as a product in the same manner as each semiconductor device located in the center of the substrate, it is referred to (Japanese Patent Laid-Open No. 48-39090 and Japanese Patent Laid-Open No. 2690/1990).
There is little risk of becoming an element unformable region as disclosed in Japanese Patent Laid-Open No. 202024).

FIG. 3 shows a manufacturing method for obtaining the structure of FIG. The same reference numerals as those in FIG. 1 indicate the same parts. First, FIG.
As shown in (a), a SiO ₂ film 3 for dielectric isolation is formed on a single crystal silicon substrate 1 on which a semiconductor device will be formed in the future. Next, as shown in FIG. 3B, the single crystal silicon substrate 1 having the SiO ₂ film 3 formed thereon and the support substrate 2 are directly bonded to each other and subjected to a predetermined heat treatment. Next, as shown in FIG. 3C, the polycrystalline silicon 4 is grown by the thermal CVD (Chemical Vapor Deposition) method to fill the gap 7.
Next, as shown in FIG. 3D, after removing the unnecessary portion of the polycrystalline silicon film, the element forming silicon substrate 1 side is ground,
Polish to a specified thickness. Thereafter, as shown in FIG. 1, a semiconductor device substrate 10 having a plurality of silicon single crystal islands 6 surrounded by a dielectric isolation film 5 is obtained by forming an isolation groove and an SiO ₂ film by etching.

In the above description, the method of forming polycrystalline silicon has been described by the thermal CVD method, but other methods such as plasma CVD may be used as long as the technology can sufficiently fill the gap 7.

Embodiment 2 FIG. 4 shows another embodiment. The same reference numerals as those in FIG. 1 indicate the same parts. The difference between this embodiment and the embodiment of FIG. 1 is that a groove 73 intentionally larger than the chamfered region is provided on the support substrate 2 side. When the gap 7 formed by chamfering by the thermal CVD method of the above-described embodiment is filled with polycrystalline silicon, the groove 73 is too high in the growth rate of polycrystalline silicon to generate voids inside the gap 7 or the gap 7. When embedding 7 with a thermal silicon oxide film or a thermal silicon nitride film, the purpose is to prevent stress from being generated in the single crystal silicon inside the gap 7 due to the growth rate of the thermal silicon oxide film or the thermal silicon nitride film being too high. I am trying. Therefore, the groove 73 of the present embodiment
As described above, it is necessary to have a shape that matches the growth rate of the material to be embedded, and the depth d of the groove is empirically about 5 μm or less in order to be embedded by reduced pressure CVD up to about 5 mm from the edge of the substrate. preferable.

Embodiment 3 FIG. 5 shows another embodiment. The same reference numerals as those in FIG. 1 indicate the same parts. The difference between this embodiment and the embodiment of FIG. 1 is the position of the SiO ₂ film 3 for dielectric isolation. In the case of FIG. 1, the dielectric isolation SiO ₂ film 3 is formed on the element forming substrate 1 side, whereas in the present embodiment, the dielectric isolation S 2 is formed on the supporting substrate 2 side.
An iO ₂ film 3 was formed and then bonded to the element forming substrate 1 and then filled with polycrystalline silicon 4. According to this method, among the semiconductor devices divided after the completion of all the active element formation and the wiring process between elements, the semiconductor device group 81 located around the semiconductor device substrate 10 is polycrystalline on the bottom surface of the element formation substrate. Silicon 4 will be present.

Embodiment 4 FIG. 6 shows another embodiment. The same reference numerals as those in FIG. 4 indicate the same parts. The difference between this embodiment and the embodiment of FIG. 4 is the shape of the groove 73. In the case of FIG. 4, the shape of the groove is a taper shape, whereas in the present embodiment, the shape of the groove formed on the supporting substrate 2 side is a substantially right angle step shape. After that, it was attached to the element forming substrate 1 and then filled with polycrystalline silicon 4.

Embodiment 5 FIG. 7 shows another embodiment. The same reference numerals as those in FIG. 4 indicate the same parts. The difference between this embodiment and the embodiment of FIG. 4 is also the shape of the groove 73, and like the case of FIG. 6, the shape of the groove is a substantially right angle step. 6 is different from FIG. 6 in that a groove is formed on the supporting substrate 2 side, a dielectric isolation SiO ₂ film 3 is formed, and then the device forming substrate 1 is bonded and then filled with polycrystalline silicon 4. did.

Although the shape of the groove in the above embodiment is a taper shape or a step shape of a substantially right angle, the same purpose can be achieved without being limited to these shapes even if it is a reverse taper shape. . In the above description, an example of filling the groove or the gap with polycrystalline silicon as a filling material has been described.
The same effect was achieved by a SiO ₂ film or a SiN film formed by an LD (High Temperature Low Pressure Deposition) method. Similar effects can be achieved by using a solvent containing a silanol group, but in this case, it is necessary to remove the solvent by appropriate heat treatment and solidify it by firing. In the above description, the invention of a measure against the small adhesive force in the peripheral region of the base due to the gap due to chamfering that occurs when the second substrate is directly bonded to the first substrate has been described. A method of bonding by another method will be described.

Embodiment 6 FIG. 8 illustrates an example in which there is no chamfered portion on the peripheral edge of the second substrate 2 on the side where it is bonded to the first substrate 1, and the entire surface of the substrate is flattened. The surface of the silicon substrate 1 that has been normally chamfered to be bonded to the second substrate 2 in the future is removed by grinding or polishing to the position indicated by the line AA in the figure, that is, the position where the chamfered portion disappears. Flattening and then directly bonding to the second substrate.

The flattening method is not limited to grinding and polishing,
For example, as shown in FIG. 9, the surface to be flattened is flattened with a photoresist, an organic resin such as polyimide, or an inorganic material 9 composed of a silanol group, and then the ordinary L
Ion etching may be performed from the direction indicated by the arrow by the etch back method used in the SI manufacturing process. However, in the case of this method, it is necessary to select, as the etch-back condition, a condition in which the etching rate of the material coated on the substrate surface and the etching rate of the substrate are as close as possible. Further, as means for ion etching, there are ion milling, sputter etching and the like.

Here, the peripheral region of the second substrate 2 may be chamfered in some cases. In this case as well, as in the case of the above-mentioned flattening, it is removed by grinding or polishing, or by an etch-back method. After the flattening, it may be directly attached to the flattened first substrate.

Embodiment 7 FIG. 10 shows a bonded base in which a chamfered first substrate 1 and a second substrate 2 are indirectly bonded together by a high temperature heating adhesive material 91 having fluidity. . In this case, after the adhesive material 91 is formed on the first substrate 1 or the second substrate 2, it is heated at a high temperature while applying a uniform predetermined pressure between the two substrates, so that the adhesive material in the vicinity of the center between the two substrates is formed. Since they are washed away, they will be embedded in the gaps formed by chamfering the peripheral area of the substrate. Therefore, the thickness of the adhesive material 91 formed on the first substrate 1 or the second substrate 2 is determined by the depth of the gap formed by the chamfering.

For example, the diameter is 125 mm and the chamfering depth is 100.
If the chamfering width is 100 μm and the chamfering width is 100 μm, the volume of the gap formed by chamfering is about 20 × 10 ⁸ μm ³ . on the other hand,
According to the flow of the adhesive material formed on the substrate, the
The thickness of the adhesive material that can completely fill the gap of 0 × 10 ⁸ μm ³ is about 0.02 μm at the maximum in a substrate having a diameter of 125 mm. Therefore, the thickness of the adhesive material formed on the first substrate 1 or the second substrate 2 is
(0.02 μm + adhesive layer). However, since a known heat treatment or photolithography process is performed to form a semiconductor element after forming a desired bonded substrate, the adhesive materials described so far are materials that can withstand a temperature of about 1000 ° C. Needless to say, it must be a material that can withstand the organic solvent used in the photolithography process. On the other hand, although the substrate 1 and the substrate 2 have been described as being limited to silicon, the same effect can be achieved with materials such as general glass, sapphire, diamond, and alumina, without being limited to silicon.

Embodiment 8 FIG. 11 shows a semiconductor integrated circuit device manufactured by using the substrate 10 formed by the above method. 1 denote the same members. This apparatus uses the above-mentioned SiO for dielectric isolation in a direction perpendicular to the surface of the substrate 10 by a known photolithography process and a dry etching process from the surface of the substrate 10.
₂ After forming a trench-shaped groove to a depth reaching the film 3, the groove is filled with the SiO ₂ film 5 for separating single crystal islands,
After the surface is flattened, a thyristor element, a transistor element, and a thyristor element are formed in each single crystal island by a photolithography step, a dry etching step, an ion implantation step, a heat treatment step, etc.
A resistance element, a diode element, and a capacitance element are formed, and then the respective elements are connected by an AI wiring (not shown) to form a plurality of integrated circuit devices in the substrate 10 and individual semiconductor integrated circuit device chips are diced. made.

Embodiment 9 FIG. 12 shows an individual semiconductor device 100 made by using the substrate 10 formed by the above method. The same reference numerals as those in FIG. 1 indicate the same parts. The difference from the embodiment of FIG.
The point is to make one semiconductor device using the entire surface of. This individual semiconductor device 100 is, for example, several thousand volts and several hundreds.
It is a class A high-power semiconductor device.

[0032]

According to the present invention, approximately 94 semiconductor devices of 10 mm × 10 mm can be obtained from the semiconductor device substrate 10 having a diameter of 5 inches. This acquisition number is 2 compared to the conventional acquisition number.
The improvement was 5%, and in the end, a large effect was achieved in reducing the manufacturing cost of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a part of a semiconductor device group located in the peripheral portion of the base body of FIG.

3 (a) to 3 (d) are cross-sectional views showing a manufacturing process for embodying the present invention.

FIG. 4 is a sectional view showing another embodiment of the present invention.

FIG. 5 is a sectional view showing another embodiment of the present invention.

FIG. 6 is a sectional view showing another embodiment of the present invention.

FIG. 7 is a sectional view showing another embodiment of the present invention.

FIG. 8 is a sectional view showing another embodiment of the present invention.

FIG. 9 is a sectional view showing another embodiment of the present invention.

FIG. 10 is a sectional view showing another embodiment of the present invention.

FIG. 11 is a sectional view showing another embodiment of the present invention.

FIG. 12 is a sectional view showing another embodiment of the present invention.

FIG. 13 is a schematic cross-sectional view for explaining a conventional technique.

FIG. 14 is a schematic sectional view for explaining a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon substrate for element formation 2 Silicon substrate for support 3 SiO ₂ film for dielectric isolation 4 Adhesive embedding layer 5 SiO ₂ film for isolation between single crystal islands 6 Semiconductor single crystal island 7 Gap created by chamfering 8 Semiconductor located in peripheral area Device group 10 Semiconductor substrate 11, 12 Element forming substrate 21, 22 Supporting silicon substrate 31 Dielectric isolation SiO ₂ film 32 Embedding material 51 Single crystal island isolation SiO ₂ film 61 Semiconductor single crystal island 71 Corner around the substrate Of the taper 72 by the polishing of 72 Gap 73 Groove 81 An example of a semiconductor device located in the peripheral portion 91 Adhesive material having fluidity at high temperature

Claims (15)

(57) [Claims] 1. A bonded base body in which an inorganic adhesive material is filled in a gap formed in a peripheral portion of a bonding surface between substrates in which the peripheral portion of the substrate is formed thinner than other portions. 2. A first semiconductor substrate having a chamfered peripheral edge, a second substrate bonded to the chamfered side surface of the first semiconductor substrate, the first semiconductor substrate and the second semiconductor substrate. A bonded base body, comprising: an inorganic adhesive material, which is filled in a gap formed by the chamfer on a peripheral surface of a bonding surface with a substrate. 3. The bonded base according to claim 2, wherein the first semiconductor substrate is a substrate made of a silicon material. 4. The silicon substrate according to claim 2, wherein the second substrate is a silicon (Si) -based material, a carbon (C) -based material, an aluminum (Al) -based material, a glass-based material, and an oxide or a nitride of each of the materials. A bonded base material that is a material selected from among materials. 5. The group of inorganic adhesive materials according to claim 1 or 2, wherein silicon oxide, silicon nitride, polycrystalline silicon, inorganic silanol-based material, phosphorus-based glass, boron-based glass, lead-based glass. A bonded substrate which is a material selected from 6. A first semiconductor substrate having a chamfered peripheral edge, a second substrate bonded to the chamfered surface of the first semiconductor substrate, and a peripheral region of the second substrate, A bonded base comprising a groove formed on the surface side in contact with the first semiconductor substrate and an inorganic adhesive material filled in the groove. 7. The bonded base body according to claim 6, wherein the depth of the groove is 5 μm or less. 8. A first semiconductor substrate having a chamfered peripheral edge, a second substrate bonded to the chamfered side surface of the first semiconductor substrate, the first semiconductor substrate and the second semiconductor substrate. A bonded base body, comprising: an adhesive material having fluidity by heat energy, which adheres a peripheral edge portion and another portion of a bonding surface to a substrate. 9. The bonded substrate according to claim 8, wherein the adhesive material is a material selected from the group consisting of an inorganic silanol group-based material, a phosphorous glass, a boron glass and a lead glass. 10. A step of forming an insulating film on a surface of a first semiconductor substrate having a chamfered peripheral edge, a step of overlaying a second substrate made of an electrically conductive material on the first semiconductor substrate, and an overlaying step. A method of manufacturing a bonded base body, which includes a step of filling a filling material in a gap formed on the peripheral side walls of both substrates and a subsequent heat treatment step. 11. A step of superimposing a first semiconductor substrate having a chamfered peripheral edge and a second substrate made of an electrically conductive material, and filling a gap formed in peripheral side walls of the superposed substrates with a filler material. A method for manufacturing a bonded substrate, which comprises a step and a subsequent heat treatment step. 12. A step of removing a chamfered portion of a first semiconductor substrate having a chamfered peripheral edge to planarize it, and a step of adhering a second substrate to the planarized first semiconductor substrate. A method for manufacturing a bonded substrate body including the same. 13. The method for manufacturing a bonded base according to claim 12, wherein the chamfered portion is removed by a mechanical flattening method using a polishing material or the like. 14. The method for manufacturing a bonded substrate according to claim 12, wherein the method of removing the chamfered portion is a method of flattening by etching with ionized gas or the like. 15. A separation for electrically insulating and separating a supporting silicon substrate, an element forming silicon substrate bonded to the supporting silicon substrate, and an adjacent semiconductor single crystal island formed on the element forming silicon substrate. In a semiconductor device comprising an SiO ₂ film for use in a semiconductor and an element provided on each semiconductor single crystal island, the bonding structure between the supporting silicon substrate and the element forming silicon substrate is defined in any one of claims 1 to 9. A semiconductor device having the structure of the bonded base as described above.