JPS6074640A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the restraint of crystal defects generating in a semiconductor substrate without so much increase in the length of a bird's beak by a method wherein an inserted oxide film and an Si nitride film are put to nearly equal film thicknesses. CONSTITUTION:After an N<+> type buried region 2 is formed in the surface of the P type Si substrate 1, and N-epitaxial layer 3 is grown over the entire surface of the substrate. Then, a P<+> type high concentration isolation region 10 is formed. Next, the inserted oxide film 11 is formed by thermal oxidation of the surface of the layer 3, and thereafter the Si nitride film 12 is deposited over the entire surface. Both are formed with equal film thicknesses, where the ratio of these thicknesses is set at 0.8-1.2. After patterning to a laminated film, selective anisotropic etcing with an alkaline solution is performed only by a required thickness. A field oxide film 7 is formed by selective oxidation of the layer 3. A thermal oxide film 13 is formed, and a P<-> type inner base region 4 is formed by ion implantation and heat annealing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an improvement in a selective oxidation method used for element isolation.

[Technical background of the invention and its problems] In the production of semiconductor devices such as ICs and LSIs, element isolation methods for electrically isolating individual elements play an important role.
A selective oxidation method has conventionally been widely used as this element isolation method.

In this type of selective oxidation, for example, a thin SiO2 film (hereinafter referred to as an intercalated oxide film) is grown on the surface of a silicon substrate, and then a CVD method (chemical vapor deposition method) is applied on top of it. After depositing a silicon nitride film, the laminated film is patterned by selective etching to serve as an oxidation-resistant mask during selective oxidation. As a result of selective oxidation using the silicon nitride film pattern as an oxidation-resistant mask, a field 5fCh for element isolation is formed in the region where the mask does not exist.
At the same time, the field oxide film is formed partially penetrating under the mask of the silicon nitride film.

This intruding portion is called a bird's beak, and since its length or width reaches approximately 1 μm, it is a major obstacle in achieving fine patterning with a high degree of integration.

For this reason, various studies have been conducted on methods to shorten the length of the bird's beak, and the data of Taniguchi et al. shown in Figures 1 and 2 (Half-One Spatula Study Group; 5SD77-23)
As is clear from the above, it is known that if the thickness of the field 5102 film is kept constant, the bird's beak length can be shortened by thickening the silicon nitride film as a mask or by thinning the inserted oxide film.

However, it has been found that although the bird's beak length becomes shorter when the silicon nitride film is made thicker and when the inserted oxide film is made thinner, crystal defects such as dislocations occur in the silicon substrate, which impairs device characteristics. It has become clear that various problems such as deterioration occur.

[Object of the Invention] The present invention has been made in view of the above circumstances, and when manufacturing a semiconductor device using an element isolation method by selective oxidation,
To provide a method that can significantly suppress crystal defects occurring in a semiconductor substrate without significantly increasing the length of a bird's beak, and further to provide a method for manufacturing high-performance bipolar transistors at a high yield by applying this method. It is something.

[Summary of the invention]

That is, the present invention covers a predetermined region on the surface of a semiconductor layer with a laminated film pattern of an oxide film and a silicon nitride film, and further uses the laminated film pattern as a mask to remove the semiconductor layer by a predetermined depth. A semiconductor in which a field oxide film is formed by selectively oxidizing the semiconductor layer using a silicon nitride film as an oxidation-resistant mask, and an element such as a transistor is formed in a predetermined region of the semiconductor layer surrounded by the field oxide film. In the method for manufacturing the device, the ratio of the thickness of the silicon nitride film to the thickness of the oxide film is set to 0.
8 to 1.2.

The inventors etched the field part of the semiconductor layer and selectively oxidized it to isolate the elements (bipolar I
As a result of intensive research into the occurrence of bird's beaks and crystal defects during selective oxidation in the manufacture of semiconductor devices having a bar 5-1'N structure (usually referred to as an isoplanar structure), = In order to shorten the u-ri, the thickness ratio of the silicon nitride film to the inserted oxide film is set to 2 or more, usually about 3. However, this film thickness ratio is set to 0.8 to 1.2, and We have discovered the remarkable fact that the occurrence of crystal defects can be significantly suppressed by making the oxide film and the silicon nitride film approximately equal in thickness, and based on this we have arrived at the present invention.

(Embodiments of the Invention) Hereinafter, embodiments in which the present invention is applied to manufacturing a bipolar semiconductor device will be described.

Before describing a specific example of a manufacturing method, first, the bipolar type semiconductor device shown in FIGS. 3 to 6, which is to be manufactured, will be described.

Figure 3 (A> shows one large emitter area (400X
500 μm), and FIG. 3(B) is a plan view of a particle-type bipolar transistor having
- It is a sectional view along the B line. In these figures, 1 is a p-type silicon substrate, 2 is an n-type buried region, 3 is an n-type epitaxial silicon layer (collector region), 4 is a p-type base region, 6-rod and 5 are pF-type pads. Contact areas 1 to 6 are n+ type plate transmitter areas. In this case, the field oxide film is formed outside the base region 4, away from it (
Hereinafter, the transistors shown in FIGS. 3A and 3B will be referred to as a normal large emitter structure.)

Figure 4 (A>) shows a transistor array in which the n-type emitter region 6 in the large emitter structure of Figures 3 (A) and (B) is divided into 104 emitter regions 6- (4 x 5 μm openings). It is a plan view, and FIG. 4 (B) is a plan view of the same figure (A
> is a sectional view taken along line BB. Also in this case,
The field oxide film is formed apart from the base region (hereinafter, this will be referred to as a normal transistor array structure).

FIG. 5(A) shows the fourth
5A is a pattern plan view showing a transistor array having an emitter region of the same size as FIG. 5B, and FIG. Diagram A
(C) is a cross-sectional view taken along the line CC in (A) of the same figure.

In these figures, 7 is a field oxide film, 8 is a 5i02 film formed on the surface of the element region, and 9 is an emitter electrode formed of an arsenic-doped polycrystalline silicon layer (in Fig. 5 (A), the diagonal lines indicate ).

In this case, the emitter region 6' is formed by doping arsenic from the emitter electrode 9. Of course, the emitter regions 6.about.6' in the conventional large emitter structure and the conventional transistor array structure are also formed from arsenic-doped polycrystalline silicon. As shown in the figure, in this isoplanar structure, the base region 4 is formed in a so-called walled base structure in contact with the field oxide film 7, but the emitter region 6- is formed with the SiO2 film 8.
is formed apart from the field oxide film 7 by using it as a diffusion mask (hereinafter, this will be referred to as the first isoplanar array structure).

FIG. 6(A) is also a pattern plan view of a transistor array formed with an isoplanar structure, and FIG. 6(B) is a sectional view taken along line BB in FIG. ) is a sectional view taken along line CC in FIG. In this case as well, the emitter region 6- is doped with arsenic using an emitter electrode 9 made of an arsenic-doped polycrystalline silicon layer as a diffusion source. However, as shown in the figure, not only the base region 4 but also the emitter region 6' has a so-called walled emitter structure in which it is in contact with the field oxide film 7 (hereinafter referred to as "walled emitter").
This is called the second isoplanar array structure).

Next, referring to FIGS. 7(A) to (E), the above-mentioned FIGS.
The present invention applied to manufacturing the bipolar semiconductor device shown in FIG. 6 will be described in detail.

Example 1 (First Isoplanar Array Structure, Second Isoplanar Array Structure) (I) First, as in the case of a normal bipolar IC, sb or Selectively dope As to achieve a surface concentration of 10 to 10 atOI
After forming the n-type buried region 2 of Il/2m3, the substrate 1
For example, a resistivity of 1 to 2 Ω・cm and a thickness of 2 to 3
．． Grow an n-type shrimp layer 3 of about 5 μm. Next, n-type impurities such as boron are added to the surface of the epitaxial layer 3 at 1100°C.
By selectively diffusing at a high temperature of ~1200 DEG C., a p4 type high concentration isolation region 1o reaching the p type substrate 1 necessary for electrical isolation of the element is formed (as shown in FIG. 7(A)).

(U) Next, the surface of the epitaxial layer 3 is thermally oxidized to form an insertion oxide film 11 with a thickness of 1000±100 mm, and then silicon nitride 1112 with a thickness of 1000±100 mm is deposited on the entire surface using the CVD method. (Therefore, the insertion oxide film 11
The silicon nitride film 12 and the silicon nitride film 12 are formed with equal film thickness, and the film thickness ratio between the two is approximately 1).

Subsequently, a pattern plan view of the laminated film of the inserted oxide film 11 and the silicon nitride film 12 is made to form a laminated film pattern that covers the intended element area, and then a predetermined thickness is applied to the silicon substrate 1 using the laminated film pattern as a mask. Selective anisotropic etching is performed using an alkaline solution (as shown in FIG. 7(B)).

Note that the etching depth at this time should be changed depending on the thickness of the evitable layer 3 and the thickness of the field oxide film to be formed in the next step, but is usually 0.3 to 0. Etching is performed to a thickness of about 8 μm, and the bottom end of the field oxide film is n-type buried 'aN 2 (7) Height 11
It is formed so as to be in contact with the evaporative part (eg, Eva 5 x 1017 atoms/cm3).

(I[l) Next, using the silicon nitride film 12 as an oxidation-resistant mask, the epitaxial layer 3 is selectively oxidized in a thermal oxidation furnace at 1000° C. to form a field oxide film 7 with a thickness of 1.0 μm or less. . Subsequently, after removing the silicon nitride film 12 and the inserted oxide film 11 by etching, a new thermal oxide film 13 with a thickness of about 500 layers is formed on the surface of the element region.

Next, by boron ion implantation (internal base implantation) and thermal annealing, the p
- Form the internal base region 4 of the mold (as shown in FIG. 7(C)).

(IV) Next, an emitter diffusion window is opened in the thermal oxidation 1 (113), and the first isoplanar array structure shown in FIGS. In the second isoplanar array structure shown in (C), the method of opening the emitter diffusion window is slightly different.

That is, in the first isoplanar array structure, FIG.
In the second isoplanar array structure, as shown in FIG. 6(C), the field oxide film 7 is formed apart from the field oxide film 7, as shown in FIG. do. The difference between the first isoplanar array structure and the second isoplanar array structure is that the emitter diffusion window opening method is different.
The manufacturing method for all isoplanar array structures is the same.

After forming the emitter diffusion window as described above, a polycrystalline silicon layer with a thickness of 2,500 layers is deposited on the entire surface by CVD, and the polycrystalline silicon layer is ion-implanted and thermally annealed to approximately 3×11020 atoms/layer. Dope with arsenic at a concentration of cm3. Subsequently, the arsenic-doped polycrystalline silicon layer is patterned to form an emitter electrode I19, and then a thermal oxide film 14 is grown on the surface of the emitter electrode 9. Next, emitter electrode 9 and field oxide film 7
The p-type external base region (
A base contact region) 5 is formed by self-line (as shown in FIG. 7(D)).

(V) Next, arsenic is thermally diffused using the emitter electrode 9 as a diffusion source to form an n+ type emitter region 6- in the internal base region 4. Then, for example, silicon nitride M15
After depositing the metal wiring layer 1 on the entire surface, the metal wiring layer 1 is formed by forming contact holes, depositing metal wiring material, and patterning.
6 (as shown in FIG. 7(E)).

In this way, a bipolar semiconductor device having the first isoplanar structure or the second isoplanar structure is completed.

Embodiment 2 (Normal large emitter structure, normal transistor array structure) In this case, when forming the internal base m14, as shown in FIG.
The internal base region 4 is formed at a distance from the field oxide film 7 by a normal mask alignment method, rather than by the self-alignment method for the field oxide III 7 as described in section C).

Other than that, the method shown in FIG. 3(A) was substantially the same as in Example 1.
(B) Normal large emitter structure, Fig. 4 (A) (B)
) is obtained.

Comparative Example The thickness of the inserted oxide film 11 described in connection with FIG. 7(B) was set to 300±60, and everything else was carried out in the same manner as in Examples 1 and 2. Therefore, the silicon nitride film 12
The film thickness is 1000±100, and the film thickness ratio of the silicon nitride film 12 to the inserted oxide film 11 is 3 in this case, which is within the conventional range. In this way, by the conventional selective oxidation method, the normal large emitter structure and the normal transistor array structure shown in FIGS. 3 to 6, respectively, are formed.
Four types of bipolar semiconductor devices having first and second isoplanar structures were obtained.

The following tests were conducted on the four types of bipolar semiconductor devices (example amounts) obtained in Example 1 and Example 2 above, and the four types of bipolar semiconductor devices obtained in the comparative examples (comparative example amounts). I did this.

Test Example 1 First, the leakage (abbreviated as EC leak) between the emitter and the collector was electrically measured for each of the four comparative example amounts and the four example amounts, and V was determined from the results. E=0.3
I in case of V. . The non-defective rate was evaluated by considering those with ≦1 μA as non-defective products. FIG. 8(A) shows the evaluation results for the comparative example amount, and FIG. 8(B) shows the evaluation result for the example amount. These evaluation results are based on the case of the normal large emitter structure shown in FIG. 3, and are normalized with this case as 1. Furthermore, when standardizing, consideration is given to the fact that since the large emitter structure and the transistor array have different device sizes, the yield rate may differ depending on workability factors.

To explain the results in Fig. 8, first, as is clear from the results in Fig. 8 (A), in the comparative example quantities, the yield rate of the isoplanar structure shown in Figs. 5 and 6 is lower than that in Figs. 3 and 6. It can be seen that the non-defective product rate is significantly lower than that of the structure shown in Figure 4, and the failure rate due to EC leakage is extremely high. This is because crystal defects such as dislocations generated in the epitaxial layer 3 due to selective oxidation are localized near the field oxide film 7. This situation can be seen in the SEM photograph (scanning electron micrograph) of the surface of the comparative example product shown in Figure 6 manufactured by the conventional selective oxidation method.
This is clearly shown in FIG. In the same SEM photograph, the ridged part that appears to run horizontally is the field oxide film 7, and the concave-looking part between the oxide films 7 and 7 is the emitter region 6', and the convex-looking part is the emitter region 6'. In the base contact region 5 and the emitter region, what looks like scratches indicated by arrows is a crystal defect. As described above, since crystal defects due to selective oxidation occur near the field oxide film 7, the internal base region 4 is formed in contact with the field oxide film 7 in FIGS. 5(A) to 6(C) and FIG. A)～(
It is known that the isoplanar array structure of C) is seriously affected by crystal defects and therefore has a high failure rate due to EC leakage.

In particular, in the structure shown in FIG. 6 (second isoplanar array structure) having a walled emitter structure in which the emitter region 6- is also formed in contact with the field oxide film 7, emitter impurities undergo abnormal diffusion through the crystal defects. As a result of the so-called emitter pipe phenomenon in which the emitter region is formed by penetrating the base region, the number of defects due to EC leakage becomes extremely large, and the yield rate is extremely low at 40% or less.

On the other hand, in the example quantities produced by the method of the present invention, as is clear from the results in FIG. 8(B),
In any of the structures shown in the figure, the yield rate is high, and the occurrence of defects due to EC leakage is greatly suppressed. This indicates that generation of crystal defects due to selective oxidation was prevented. In particular, the structure shown in Figure 5 (first isoplanar structure)
Since the structure shown in FIG. 6 (second isoplanar structure) has a higher yield rate than the structure shown in FIG. 6, it can be seen that abnormal diffusion of the emitter at the end of the field oxide film is completely prevented.

17- On the other hand, when the bird's beak length of the field oxide film 7 was measured for both the example amount and the comparative example amount, it was 1.28 μm for the example amount and 1°10 μm for the comparative example amount.

Therefore, in the example, the increase in the bird's beak length due to the thinning of the inserted oxide film 11 could be suppressed to 16%.

Test Example 2 The thickness of the field oxide film 7 formed in the step shown in FIG. 7(C) and the arsenic concentration in the polycrystalline silicon layer 14 used as an emitter diffusion source in the step shown in FIG. 7(D) were determined. By carrying out Example 1 with changes, FIGS.
Obtaining the second isoplanar array structure shown in (C),
The same test as in Test Example 1 above was conducted on the obtained Example amount.

Figure 10 (A) shows the arsenic concentration of the polycrystalline silicon layer at 5X.
1020 atoms/cttt 3, and the results of manufacturing yield determined by EC leakage are shown for examples obtained by varying the film thickness of the field oxide film 7. In addition, regarding the practical control obtained by setting the film thickness of the field oxide film 18- (-7) to 1 μm and changing the arsenic concentration of the polycrystalline silicon layer in FIG. It shows the yield results.

As shown in the results in FIGS. 10(A) and 10(B), when the field oxide film thickness becomes 1.0 μm or more in the case of an arsenic concentration of 5×1020/cur3, an extreme decrease in yield is observed. When the selective oxide film thickness is i, 0 μm and the arsenic concentration exceeds 3.0×10 20 /Cm 3 , the yield decreases sharply. In this way, although the effects of the above embodiments depend on the field oxide film thickness and the arsenic concentration of the emitter diffusion source, the excellent effects described above can be obtained by appropriately setting these parameters. be.

The above-mentioned example shows that by applying the present invention to bipolar ICs, it is possible to significantly prevent a decrease in manufacturing yield due to EC leakage, but as already mentioned, this effect is not achieved during selective oxidation. This is because crystal defects in the semiconductor layer that occur can be significantly suppressed. Therefore, the present invention is applicable not only to bipolar semiconductor devices but also to the manufacture of all semiconductor devices using selective oxidation, such as MO8 type ICs.

〔Effect of the invention〕

As described in detail above, according to the present invention, when manufacturing semiconductor devices using an element isolation method using selective oxidation, crystal defects occurring in semiconductor substrates can be significantly reduced without significantly increasing the length of the bird's mouth. It is possible to provide a method that can suppress the amount of damage caused by the oxidation process, and furthermore, by applying this method, it is possible to produce high-performance bipolar transistors at a high yield, and other remarkable effects can be obtained.

[Brief explanation of the drawing]

FIGS. 1 and 2 show that the bird's beak length of the selective oxide film is l! of the insertion oxide film and the silicon nitride film. Diagrams showing known data that it depends on thickness, Figures 3(A)(B) to 6
Figures (A), (B), and (C) are diagrams showing a bipolar semiconductor device to be manufactured in an embodiment of the present invention, and Figure 7 (A
)～(E) is 'fangs? FIG. 8 is a sectional view sequentially showing the manufacturing process of an embodiment in which 1 light is applied to the manufacturing of the bipolar semiconductor devices shown in FIGS. 5(A) to (C) and FIGS. 6(A) to (C) (A) and (B) are diagrams showing the effects of an example in which the present invention is applied to the manufacture of a bipolar semiconductor device, and FIG. 9 is a surface of a bipolar semiconductor device obtained in a comparative example using a conventional manufacturing method. Scanning electron micrograph, Figure 10 (
A) and (B) show the effects of applying the present invention to the manufacture of bipolar semiconductor devices, including the selective oxide film thickness and the impurity I! of the emitter diffusion source. It is a diagram showing that it depends on the melon. 1...p-type silicon substrate, 2...type-resistant buried region, 3
... n-type epitaxial layer (collector region), 4...
・p- type internal base region, 5... p+ pear-shaped outer base region (base contact region 1), 6.6-... n1 type emitter region, 7... field oxide film (selective oxidation film), 8... SiO2 film, 9... Emitter electrode (polycrystalline silicon layer), 11... Insert oxide film, 12... Silicon nitride film, 13.14... Thermal oxide film, 15 ...
Passivation curtain, 16...metal wiring layer. 21- Fig. 1: Thickness of arch-shaped lunar capsule: 10P 0 1 (X7 200 300 X 7 200 300) death. Ward Figure 6 C S! 3N+15i0z= 1

Claims (1)

[Claims] <1) A predetermined region of the surface of the semiconductor layer is covered with a laminated film pattern of an oxide film and a silicon nitride film, and the semiconductor layer is further etched away to a predetermined depth using the laminated film pattern as a mask. After that, a field oxide film is formed by selectively oxidizing the semiconductor layer using the silicon nitride film as an oxidation-resistant mask, and an element such as a transistor is formed in a predetermined region of the semiconductor layer surrounded by the field oxide film. A method for manufacturing a semiconductor device, characterized in that a ratio of the thickness of the silicon nitride film to the thickness of the oxide film is 0.8 to 1.2. (2) A silicon layer with a plane orientation of (100) is used as the semiconductor layer, and the silicon layer is selectively anisotropically etched in the depth direction using the laminated film pattern as a mask. A method for manufacturing a semiconductor device according to claim 1. (3) The etching depth of the semiconductor layer is set to 0.3 to 0.0°.
A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that the thickness is 7 μm. (4) A particulate bipolar transistor is formed in a predetermined region of the semiconductor layer surrounded by the field oxide film, and at that time, a polycrystalline silicon layer containing arsenic is used as a diffusion source in the emitter region of the bipolar transistor. Claims 1, 2, or 3 are characterized in that the polycrystalline silicon layer is formed by thermal diffusion of arsenic, and the arsenic concentration in the polycrystalline silicon layer is 5 x 10" atoms/cm3 or less. A method of manufacturing the semiconductor device described above.