JPH10303210A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an active base area having a flat surface even when the surface is etched by forming an insulation film at such a temperature that the amorphous state of an amorphous silicon film can be maintained. SOLUTION: After a semiconductor layer surrounded by a LOCOS oxide film 57 is exposed, an a-Si (amorphous silicon) film 67 is formed on the entire surface of a circuit board, and an insulating film 68 is formed at such a low temperature that the a-Si film 67 is not crystallized into poly-Si. Therefore, even when the semiconductor layer is exposed by etching, there are no irregularities formed and an active base area 74 having a uniform diffusion depth can be formed, because the etching rate of the a-Si film 67 is the same throughout the film 67.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor integrated circuit for realizing a surface of an active base region having no irregularities by etching a silicon film serving as a diffusion source of a predetermined external base region in a shape having no irregularities.

[0002]

2. Description of the Related Art As a method for obtaining an extremely fine base-emitter junction, for example, the methods described in Japanese Patent Application Laid-Open No. 7-235547 and Japanese Patent No. 2576373 are known. This is a BIP type transistor having a high speed enough to be used in a supercomputer.

As will be described later, since the base region of this transistor employs a polysilicon film, there is a problem that the surface of the active base region is particularly uneven, which affects the characteristics. 22 to 26 show the latter publication, and will be described below with reference to this figure.

As shown in FIG. 22, a P-type semiconductor substrate 1 is provided.
Is provided with an N-type epitaxial layer 2 and an N + -type buried layer 3 is provided therebetween. Also on both ends,
An insulating separation layer 4 is provided. This insulating separation layer 4
As in the present application, a trench, a LOCOS, or a PN isolation may be formed under the LOCOS.

Further, a P + type polysilicon film 5 is formed on the entire surface.
And a silicon oxide film 6 are formed. (Refer to FIG. 22 above.) Subsequently, as shown in FIG. 23, there is a step of patterning the polysilicon film 5 and the silicon oxide film 6 by dry etching. The patterned polysilicon film serves as a diffusion source for the external base region 7 and also serves as an extraction electrode 8 for the external base region 7. Also, this patterning
The intended active base region 9 is exposed. (Refer to FIG. 23 above.) Further, in the step of applying heat from now on, the impurities of the extraction electrode 8 are diffused to generate the external base region 7. The active base region 9 is formed through the opening 11 exposing the active base region 9, and the silicon oxide film 10 is formed as shown in FIG.
Is formed on the entire surface and etched back to form the spacers 12 as shown in FIG.

Finally, an extraction electrode 14 of an emitter region serving as a diffusion source and an electrode is formed through an opening 13 formed by the spacer 12, thereby forming an emitter region. A fine high-frequency transistor can be manufactured by the above manufacturing method.

[0007]

However, FIG.
23, since the polysilicon film 5 is employed, there is a problem that the surface of the planned active base region becomes uneven as shown in FIG. The insulating film 6 is a CVD oxide film, and the lower film 5 is a polysilicon film. Polysilicon is a collection of grains and a grain boundary, and the grain boundary has a higher etching rate. Therefore, when dry etching is performed, grains remain on the surface of the active base region, and the active base region corresponding to the grain boundary is etched, so that the exposed silicon substrate surface becomes uneven.

Since this region finally becomes a contact portion of the emitter electrode 14, there is a problem of increasing the contact resistance. Moreover, the unevenness of the surface of the semiconductor layer exposes various crystal faces. For example, the surface is [1,0,
[0] plane, but the [1,1,1] plane appears on the uneven surface.
In this [1,1,1] plane, the diffusion speed is high, so that the shape of the active base region becomes uneven, which has a problem that the transistor characteristics are affected.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and comprises forming an amorphous silicon film on a semiconductor layer into which impurities of a predetermined external base region are introduced, and further forming the amorphous silicon film. The problem is solved by forming the second insulating film at a temperature at which the film can maintain an amorphous state.

First, amorphous silicon (hereinafter a-Si)
Has no grain or grain boundary, so that even without etching, a surface without unevenness can be realized. However, when high-temperature heat is applied to the amorphous silicon layer,
Since it is converted to a polysilicon film, it is preferable that a-Si remains as much as possible until the planned active base region in FIG. 11 is exposed. Therefore, the deposition temperature of the second insulating film formed on a-Si is preferably a low temperature capable of maintaining the a-Si state as much as possible.

Second, an amorphous silicon film in which impurities of a predetermined external base region are introduced is formed on the semiconductor layer, and a second insulating film is formed at a temperature at which the amorphous silicon film can maintain an amorphous state. The problem can be solved by removing the second insulating film and the amorphous silicon film so that the active base region is exposed, and forming an emitter electrode via a spacer provided on a side wall of the extraction electrode of the external base region. Things.

Until the active base region is exposed, a-
Since the substrate is maintained in the Si state, the portion of the active base region becomes flat. Therefore, even if the emitter electrode is formed, the contact resistance is reduced. Third, the problem is solved by forming the second insulating film with a silicon oxide film formed by a CVD method, and fourth, by forming the second insulating film with a silicon oxide film formed by plasma CVD. Is the solution.

For example, when a silicon oxide film is formed by CVD, it is divided into normal pressure CVD and low pressure CVD by pressure.
Depending on the type of excitation, it is divided into high-temperature CVD, low-temperature CVD, plasma CVD, and optical CVD. Especially plasma CVD
Can be formed at a temperature of about 400 degrees or less, and the optical CVD can be formed at a temperature of about 300 degrees or less. In low-pressure low-temperature CVD, a film can be formed at about 380 ° C. using silane alone. Therefore, a-Si under the silicon oxide film can maintain an amorphous state.

A fifth problem is solved by maintaining the amorphous silicon film at least until the formation of the extraction electrode in the emitter region. Spacer is poly S
If i, the surface becomes uneven, but if it can be maintained with a-Si, the surface can be made smooth.
Therefore, whether the emitter region is formed by ion implantation or the extraction electrode of the emitter region is formed as a diffusion source,
The emitter diffusion region has a gentle shape on both the bottom surface and the outer periphery, so that variations in the diffusion region can be suppressed.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.
This will be described with reference to FIGS. First, an N-type semiconductor layer 51 serving as a collector is formed on a P-type semiconductor substrate 50 by an epitaxial growth method. The semiconductor layer 51
An N + type buried layer 52 is formed on the entire surface between the semiconductor substrate 50 and the semiconductor substrate 50. Further, the collector contact region 53 of the transistor is formed by diffusion or ion implantation.

On the surface of the semiconductor layer 51, a thermal oxide film 54 of about 500.degree. And a silicon nitride film 55 as an oxidation resistant film of about 1000.degree. Are formed by CVD to cover the collector contact region 53 and a predetermined base region. The silicon nitride film 55 is etched via the resist 56 thus formed. (Refer to FIG. 1 above.) Subsequently, after the resist 56 is removed, the film thickness of 500
A LOCOS oxide film 57 of about 0 ° is formed,
The oxidation resistant film 55 and the thermal oxide film 54 surrounded by the oxide film 57 are removed. (Refer to FIG. 2 above.) Subsequently, the entire surface is oxidized to form a thermal oxide film 58 of about 400 ° on the exposed semiconductor layer 51, and then a further 1000 °.
A silicon nitride film 59 having a thickness of about 3,000 and a non-doped silicon glass film 60 having a thickness of about 3000 are formed by CVD, and a resist 62 is applied so that a portion corresponding to a predetermined trench 61 is exposed. Then, using the resist 62 as a mask, the surface of the semiconductor layer 51 is etched. (End of Figure 3
Subsequently, the resist 62 is removed, and the silicon glass film 60 is removed.
, The trench 61 is dug down halfway through the semiconductor substrate 50. (See FIG. 4 above.) Subsequently, a thermal oxide film 62 of about 1000 ° is formed on the surface in the trench by steam oxidation of about 1000 °. (See FIG. 5 above.) Subsequently, the silicon glass film 60 is removed with hydrofluoric acid. At this time, the thermal oxide film 62 inside the trench is also removed,
A thermal oxide film of about 3000 ° is formed by thermal oxidation again. (Refer to FIG. 6 above.) Subsequently, a trench film 64 is formed on the entire surface to fill the trench 61. Here, the trench film 64 is polysilicon or a-Si. (See FIG. 7 above.) Subsequently, the trench film 64 is etched back. The trench film 64 on the surface of the silicon nitride film 59 is completely removed and slightly over-etched to cover the trench 61 with a cap. (See FIG. 8 above.) Subsequently, steam oxidation of about 1000 degrees is performed to oxidize the trench film and form a cap 65 made of a silicon oxide film. Since the cap 65 is convex upward, the cap 65 is slightly etched using the silicon nitride film 59 as a mask, and then the silicon nitride film 59 is removed with hot phosphoric acid. At this time, since the thermal oxide film 58 is also removed together, the thermal oxide film 66 is again
Å Generate about. (Refer to FIG. 9 above.) Subsequently, in order to expose the collector contact region 53 surrounded by the LOCOS oxide film 57 and a predetermined base region, the thermal oxide film 66 on the semiconductor layer is removed, and a
-Si67 is formed with a thickness of about 2000 DEG by CVD, and BF2 is ion-implanted over the entire surface. Here, a
An impurity may be added to the Si-forming gas (a gas composed of H2 and silicon, for example, silane), or the impurity may be deposited. Further, here, in order to use the a-Si as a diffusion source and to utilize the a-Si as an extraction electrode, it is preferable to perform ion implantation that can accurately control resistance value control and concentration control of an external base.

Next, a feature of the present invention is that an insulating film 68 is formed on the entire surface. The insulating film 68 is a plasma TEOS film having a thickness of about 2000 ° here. Where plasma TE
The OS film is a film in which an organic material (Si (OC2H5) 4) of tetraethoxysilane (TEOS) is formed by plasma CVD. The point here is that an insulating film is formed at a low temperature so that the a-Si film 67 is not converted into polysilicon.
Is maintained in the state of a-Si until the etching is completed. The detailed reason is that, as described later, once converted into polysilicon, the semiconductor layer becomes uneven as shown in FIG. 23 due to the difference in the etching speed of the grains and the grain boundary. In other words, the point is to keep the extraction electrode from being converted into polysilicon until the pattern etching of the extraction electrode in the external base region is completed. Here, aside from polysilicon, a-Si and single-crystal Si are considered. As described later, even if a-Si is maintained, it is converted into a single-crystal Si film by heat treatment, and the etching shown in FIG. If performed, the surface of the semiconductor layer does not form unevenness by etching.

When a-Si is heat-treated at about 580 ° C. or more, it is converted to poly-Si.
It should be deposited at as low a temperature as possible. Further, it is necessary to use a-Si as an extraction electrode of the planned external base region and to insulate the periphery as shown in FIG.
8 is preferably a silicon oxide film.

Here, if the oxide film is used by CVD, (forming method) reaction system deposition temperature normal pressure low-temperature oxidation (SiH4-O2) 400 degrees reduced pressure low-temperature oxidation (SiH4-O2) 400 degrees thermal decomposition (Si Various methods such as (OC2H5) 4) 750 degrees plasma (SiH4-N2O) 250 degrees plasma (Si (OC2H5) 4) 400 degrees light (SiH4-N2O) 200 degrees are conceivable. In other words, pyrolysis is
The temperature is too high, but otherwise it is suitable because it is relatively low. As will be described later, after once attaching a-Si,
It may be converted to a single crystal by heat treatment. This is because neither a-Si nor single-crystal Si has a structure in which grains and grain boundaries are interspersed, so that even if patterning is performed, the surface of the semiconductor layer becomes smooth. (Refer to FIG. 10 above.) Thereafter, both films 67 and 68 are etched using a resist 69, and a patterned film is formed on a portion corresponding to a predetermined external base and a LOCOS oxide film 57 adjacent to this region.
Extend up. The extended a-Si is used as an extraction electrode for the external base region.

This step is a feature of the present invention,
As described above, since the patterning is performed without converting a-Si into polysilicon, the surface of the extraction electrode 70 of the external base region and the surface of the intended active base region are smooth. Since the surface serving as the active base region is not uneven, the diffusion region after diffusion has a substantially uniform diffusion depth no matter where it is taken. Further, since the inner side surface of the extraction electrode 70 is not uneven, the shape of the oxide film 71 and the spacer 72 to be subsequently grown is not affected. (See FIG. 11 above.) Subsequently, the entire surface is thermally oxidized in a steam atmosphere of about 800 degrees,
A thermal oxide film 71 of about 100 to 200 ° is formed on the a-Si surface or the semiconductor layer 51 surface. At this point, the impurities in the extraction electrode 70 are slightly diffused, and the external base region 72
Are slightly formed. Further, using a resist 73 as a mask for ion implantation, BF2 as a base impurity is ion-implanted through the thermal oxide film 71. As a result, an active base region 74 is formed by a later heat treatment step.

Here, the surface of the semiconductor layer to be ion-implanted is
The bottom surface of the active base region has a uniform diffusion depth because it is formed not ruggedly but gently. Also, the junctions appearing on the surface of the semiconductor layer are not uneven, and can be formed according to the initially determined pattern. (See FIG. 12 above.) Subsequently, after removing the resist 73, a silicon oxide film is formed on the entire surface by CVD in consideration of insulation between a predetermined emitter electrode and a base extraction electrode 57, and further, a predetermined active base is formed. A spacer 72 is formed on a side wall corresponding to the region.

The spacer 72 is also formed of a-Si.
It is formed by being etched back by anisotropic etching. At this stage, since the thermal oxide film 71 on the surface of the active base region 74 remains, it is removed by, for example, wet etching. (See FIG. 13 above.) Subsequently, a silicon film made of polysilicon or a-Si is deposited to form the extraction electrode 75 of the intended emitter region. In addition, As is ion-implanted over the entire surface in consideration of the resistance value of the emitter electrode and the impurity concentration of the emitter region, and etched through the resist 76. (Refer to FIG. 14 above.) Subsequently, the insulating film 68 is partially etched to form the contact 77 of the extraction electrode 70 in the external base region, and insulating films 78 and 79 are formed on the entire surface. The insulating film 78 is a non-doped silicon glass film having a thickness of about 1000 to 1500
It is a BPSG film of about 00 to 6500 °.

The next step is contact photo etching, in which an opening is formed by dry etching. In particular, the contact 80 of the base electrode is formed inside the contact 77. The contact 81 of the emitter electrode exposes the extraction electrode 75 in the emitter region, and the contact 8
2 exposes the collector contact region 53.
(See FIG. 15 above.) Further, using a mask for ion implantation for the contact 80,
BF2 is ion-implanted. This is done to reduce the contact resistance.

For the emitter diffusion, the mask is removed and the entire substrate is heat-treated. As a result, the previously implanted ions are diffused to form an active base region 74,
At the same time, an emitter region 83 is formed by solid-phase diffusion from the emitter extraction electrode 75. The diffusion depth of the emitter region 83 is about 0.5 μm.
It is formed outside of 2.

Thereafter, a base electrode 84, an emitter electrode 85 and a collector electrode 86 are formed through light etching. In addition, there is a step in which heat treatment is applied before the electrodes are formed, so that the step coverage is made gentle.
The BPSG film 79 is a film that sags by heat, and the non-doped silicon glass film 78 is a film that does not sag. Therefore, a vertical step of about 1000 ° is formed in the contact portion, and the film 79 on the contact is sagged, so that a contact with improved step coverage can be formed.

Accordingly, the step coverage of the electrode is improved, and a finely processed high-frequency transistor can be manufactured. Here, the feature of the present invention is that, as described in the description of FIGS. 10 and 11, an a-Si film 67 or an a-Si film is applied as an extraction electrode of the base region and then converted to a single crystal film by heat treatment. Is to use a membrane.

Unlike a polysilicon film, an a-Si film and a single-crystal Si film have no grain or grain boundary, and therefore have a feature that an etched surface becomes gentle. As shown in FIG. 23, when polysilicon is etched, the grain boundary has a higher etching speed, so that the surface becomes a surface, which eventually makes the surface and interface of the active base region. Si can eliminate this.

Here, when the insulating film 68 is deposited at a high temperature, the tendency of conversion from a-Si to poly-Si is strong. Therefore, the insulating film 68 is deposited at a temperature as low as possible, and the state of the a-Si is changed. It is important to maintain. When high-temperature heat treatment is inevitably applied, single-crystal Si
What is necessary is just to convert it into a film. Hereinafter, the experimental result of the single crystallization will be described with reference to FIGS.

FIGS. 17 to 19 show the conversion state of the film. The left side shows a conventional method, which is grown directly from polysilicon, and the right side shows amorphous silicon (hereinafter a-type). (Referred to as Si) to after the heat treatment. Here, an experimental flow for converting a-Si to a single-crystal Si film will be described. A: A silicon oxide film of about 1000 ° is grown on a silicon substrate.

B: Mounted on LPCVD equipment, 540 degrees
At 580 degrees, 600 degrees, and 620 degrees, 100% silane gas (SiH4) is supplied to form a Si film. At this time, the film thicknesses were 2000 and 3000, respectively.
4000 $. C: BF2 is ion-implanted over the entire surface. 60 eV, 3 × 1
015 D: Anneal for 1 hour in a nitrogen atmosphere at 900 ° C.

E: Measurement of sheet resistance RS. FIG. 17 shows the steps up to the step B, FIG. 18 shows the state where the step C is completed, FIG. 19 shows the state where the step D is completed, and FIG. 20 (sheet resistance Rs) and FIG. (Variation in sheet resistance). 20 and 21
The horizontal axis indicates the film formation temperature in the step B.

Looking at the measurement results, the lower the film forming temperature,
It was found that the sheet resistance was low and the variation was small.
It was also found that the film formed in the step B was formed of amorphous silicon at about 520 to 580 degrees (hereinafter referred to as a low temperature region). Further, a region exceeding 590 degrees to 610 degrees (hereinafter referred to as a high-temperature region) has a greatly changed surface state and is made of polysilicon. About 580
It is considered that a region between about degrees and 600 degrees (hereinafter referred to as an intermediate region) is a transition region between polysilicon and amorphous silicon.

The surface condition of the silicon film is as follows:
As seen from the electron microscope (magnification: 50,000), as shown on the right side of FIG. 17 and FIG.
01 is formed. On the other hand, in the high temperature region, as shown in the left of FIG.
The (diameter) polysilicon film 103 can be observed. A grain boundary 104 exists between the grains 102.

Next, in the ion implantation in the step C, boron fluoride (BF 2+) 105 is ion-implanted as shown by the mark X, and the impurity dispersion state of the right a-Si film and the left polysilicon film is Are considered to be substantially the same. Here, if boron is ion-implanted, it penetrates the a-Si film or the polysilicon film. Therefore, boron fluoride having a large size to enter near the surface is employed. In addition, As ions, like boron fluoride, do not enter deeply and can be employed.

Further, the annealing step in the step D is about 800 to 1000 degrees, preferably about 900 degrees.
(Here, if a-Si is maintained, the annealing step is performed at the relatively low-temperature film formation described above, for example, 400.
This corresponds to the step of forming the insulating film 68 at different temperatures. The result here was unexpected. In the polysilicon film 103 on the left side of FIG. 19, the diameter of the grains slightly increased due to the heat treatment, but the grains were observed with an electron microscope (magnification of 50,000 times). However, a-Si on the right side of FIG. 19 is an electron microscope (magnification of 50,000 times).
Observed at, it was not possible to determine whether there was any grain. Since the heat treatment has been applied, it is difficult to imagine that a-Si remains as it is, and it can be determined that the substantially observed portion is a single crystal and a very large grain film. Also, no grain boundary was observed, and it was determined that the grain was large and almost occupied by one grain, and that there was substantially no grain boundary.

In general, the film after annealing is 5 ° C. in a high temperature region.
Grains of about 00 ° exist and the surface is rough, but the surface is much flatter in the low temperature region than in the high temperature region. Therefore, when the polysilicon film in the high-temperature region is etched, the grain boundary has a higher etching speed, so that the surface becomes observable when observed with an electron microscope. Also, the surface of the a-Si film in the low temperature region is
Almost flat. Also, single crystals with large grains do not have grain boundaries, so even if etched,
This is probably because a clean pattern with a flat and well-formed shape can be formed.

As described above, first, the a-Si film 67
Until it is deposited and patterned as shown in FIG.
When maintained in the state of a-Si, the active base region becomes flat, the shape of the active base region does not become uneven as in the conventional case, the variation can be reduced, and the contact resistance can be reduced. it can. When high temperature is applied to a-Si, if a-Si is made to be a single crystal, the active base region will not be uneven like etching a-Si even if it is etched.

Further, an a-Si film is formed by flowing a silane gas in a low temperature region on a wafer provided in a plasma CVD or LPCVD apparatus, and impurities are diffused while heat treatment is performed thereon. It is used as a diffusion source. As described above, this film has a small variation in sheet resistance and is a flat film whose surface state cannot be substantially distinguished from a-Si. High etching process is possible. Therefore, it can be used as an extraction electrode because of the small variation in sheet resistance and the fact that the shape can be etched accurately, and the semiconductor surface and the uneven diffusion surface as shown in FIG. 23 can be significantly reduced.

Therefore, variations in the area of the external base region and the area of the active base region are reduced, and the surface of the active base region is flattened, so that the contact resistance can be reduced. Furthermore, a film obtained by heat-treating a-Si,
That is, the film of FIG. 19 can lower the sheet resistance as compared with polysilicon, and can reduce the resistance of the extraction electrode.

[0040]

As described above, an amorphous silicon film in which an impurity of a predetermined external base region is introduced is formed on a semiconductor layer, and the second insulating film is formed at a temperature at which the amorphous silicon film can remain amorphous. By forming the surface, an active base region surface without unevenness can be realized even by etching.

Second, when the second insulating film and the amorphous silicon film are removed so that a predetermined active base region is exposed and an emitter electrode is formed through an opening surrounded by a spacer, the active base region is removed. Is maintained in the state of a-Si until is exposed, so that the portion of the active base region becomes flat. Therefore, even if the emitter electrode is formed, the contact resistance is reduced.

Further, plasma CVD is particularly characterized in that it can be formed at a low temperature. If a silicon oxide film is formed on a-Si by this method, the a-Si state can be maintained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 3 is a sectional view illustrating a method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 4 is a sectional view illustrating the method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 6 is a sectional view illustrating the method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 7 is a sectional view illustrating the method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 8 is a cross-sectional view illustrating the method of manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 9 is a cross-sectional view illustrating the method of manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 10 is a sectional view illustrating the method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 11 is a sectional view illustrating the method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 12 is a sectional view illustrating the method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 13 is a sectional view illustrating the method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 14 is a sectional view illustrating the method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 15 is a sectional view illustrating the method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 16 is a sectional view illustrating the method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 17 is a diagram illustrating a state when a-Si of the present invention and a conventional poly-Si film are attached.

18 is a diagram illustrating a state when ions are implanted into the two types of films in FIG.

FIG. 19 is a diagram illustrating a state when the two types of films in FIG. 18 are annealed.

FIG. 20 is a diagram illustrating the sheet resistance of the present invention and the conventional silicon film.

FIG. 21 is a diagram illustrating a variation in sheet resistance.

FIG. 22 is a cross-sectional view illustrating a manufacturing method of a conventional example.

FIG. 23 is a cross-sectional view illustrating a manufacturing method of a conventional example.

FIG. 24 is a cross-sectional view illustrating a manufacturing method of a conventional example.

FIG. 25 is a cross-sectional view illustrating a manufacturing method of a conventional example.

FIG. 26 is a cross-sectional view illustrating a manufacturing method of a conventional example.

Claims (6)

[Claims] A step of forming a first insulating film on the semiconductor layer so that a predetermined base region in the collector region is exposed; and a step of forming an external base region on the semiconductor layer to form the predetermined base region. Forming an amorphous silicon film into which impurities are introduced, and further forming a second insulating film at a temperature at which the amorphous silicon film can maintain an amorphous state; and an active base region to form the planned base region. Removing the second insulating film and the amorphous silicon film so as to be exposed; and diffusing the impurity into the predetermined active base region to form the active base region. A method for manufacturing a semiconductor integrated circuit. A step of forming a first insulating film on the semiconductor layer such that a predetermined base region in the collector region is exposed; and a step of forming an external base region on the semiconductor layer to form the predetermined base region. Forming an amorphous silicon film into which impurities are introduced, and further forming a second insulating film at a temperature at which the amorphous silicon film can maintain an amorphous state; and an active base region to form the planned base region. Removing the second insulating film and the amorphous silicon film so as to be exposed, and forming an extraction electrode of an external base region serving as a diffusion source; and forming the extraction electrode of the predetermined active base region and the extraction electrode of the external base region. Forming a third insulating film on the exposed portion; and a side of the external base region, which exposes the active base region, on an extraction electrode side. Forming an emitter electrode via a spacer provided on a side wall of the extraction electrode of the external base region, wherein the external base region is located at the extraction electrode of the external base region. The active base region is diffused by impurities and introduced through an opening surrounded by a lead-out electrode of the external base region or an opening surrounded by a third insulating film formed in the opening. A method of manufacturing a semiconductor integrated circuit, wherein an impurity is introduced into an emitter region formed in an active base region through an opening surrounded by the spacer. 3. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein said second insulating film is a silicon oxide film formed by a CVD method. 4. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein said second insulating film is a silicon oxide film formed by plasma CVD. 5. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the spacer maintains the amorphous silicon film at least before the formation of the extraction electrode in the emitter region. 6. The method according to claim 1, wherein the amorphous silicon film is converted into a single crystal silicon film by a heat treatment.