JPS59112616A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to form a shallow junction having high carrier density by heat treating a polycrystalline Si film in a heat treatment temperature range that the various porperties of the film abruptly vary in a short time. CONSTITUTION:After a boron implantation layer 12 is formed on an N type Si substrate 11, an Si oxidized film 13 is formed, the film 13 is then partly removed, and arsenic is implanted to the substrate 11 exposed in a hole and the film 13 in a polycrystalline film 14. Then, a heat treatment is executed at 1,100 deg.C or higher for 1-300sec to diffuse the arsenic in the film 14 into the substrate 11 to form an arsenic diffused layer 15. Then, the boron of the layer 12 is electrically activated to form an N-P-N type transistor. The film 14 indicated in a range 16 at this time is converted into single crystal. Thus, a shallow junction by the arsenic diffusion from the film 14 is formed without almost varying the layer 12.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and in particular, a method of manufacturing a semiconductor device suitable for forming a shallow junction on a silicon substrate and reducing the resistance of a polycrystalline silicon film. It is related to.

[Prior art]

When forming a polycrystalline silicon film into which impurities have been introduced on the surface of a silicon substrate and performing heat treatment to diffuse the impurities in the polycrystalline silicon film into the silicon substrate to form a shallow junction, the heat treatment temperature is conventionally set at 900 to 1000 ℃. ℃, 1
The heat treatment was performed for a heat treatment time of 0 minutes or more. For this reason, in the case of a silicon substrate, the carrier concentration generated in the polycrystalline/recon film was low. In particular, the carrier concentration in the polycrystalline/recon film greatly depends on the heat treatment temperature.
In the case of heat treatment at 000° C., the total number of carriers in the polycrystalline silicon film is low and the resistance of the polycrystalline silicon film becomes high. However, when forming shallow junctions and lowering the resistance of polycrystalline silicon films using the laser annealing method, which has been attracting attention in recent years, it is possible to obtain high carrier concentration and to convert polycrystalline silicon films into single crystals. While this method has advantages, it also has the disadvantage that the device structure may be destroyed by irradiation with a powerful laser beam.

[Purpose of the invention]

The purpose of the present invention is to form a shallow junction with a higher carrier concentration on a silicon substrate by diffusion of impurities from a polycrystalline silicon film into which impurities have been introduced, and to form a polycrystalline silicon film without changing the existing device structure. An object of the present invention is to obtain a method for manufacturing a semiconductor device that can reduce the resistance of the semiconductor device.

[Summary of the invention]

In order to achieve the above object, the present invention performs short-time heat treatment in a heat treatment temperature range where the various properties of polycrystalline silicon films suddenly change, and the diffusion of impurities from the polycrystalline silicon film causes the silicon substrate to carry more carriers than conventional methods. This method forms a shallow junction with high concentration and lowers the resistance of a polycrystalline silicon film without changing the existing device structure.

The present inventors formed a polycrystalline silicon film into which impurities were introduced on the surface of a silicon substrate and an insulating film on the surface of the substrate,
When diffusing impurities into the silicon substrate through heat treatment,
In the heat treatment temperature distribution 1 as shown in FIG. 1, especially when the heat treatment temperature is 1100°C or higher.

It has also been found that the following effects can be obtained when heat treatment is performed for a heat treatment time of 1 to 3C1O seconds.

A polycrystalline silicon film with a thickness of 0.16 μm is formed on the surface of a p-type silicon substrate, and 1,5
When arsenic of
] The gearia concentration of the shaped diffusion layer increases rapidly around 1100'C, as shown by carrier concentration curve 2 in FIG. Furthermore, as shown in FIG. 3, the layer resistance of the polycrystalline silicon film begins to drop sharply when the layer resistance 3 on the silicon substrate and the layer resistance 4 on the insulating film exceed 1100°C.
As shown in FIG. 4, the charge carrier concentration in the polycrystalline silicon film increases rapidly with the boundary of 1100'C as the carrier concentration 5 on the silicon substrate and the carrier concentration 6 on the insulating film. Furthermore, as shown in Figure 5, the crystal grain size of the polycrystalline silicon film changes rapidly when the crystal grain size 7 on the silicon substrate and the crystal grain size 8 on the insulating film exceed 1100°C. The crystal grain size 7 is 1150℃
The decrease in layer resistance and the increase in carrier concentration in the polycrystalline 7 Licon film as described above are due to the increase in the crystal grain size of the polycrystalline 7 Licon film, which becomes single crystallized (crystal grain size = 0) in the vicinity. Single crystallization of polycrystalline silicon on a monolithic silicon substrate causes rapid changes in layer resistance and carrier concentration. The phenomenon described above becomes noticeable when the heat treatment temperature distribution is 1 as shown in Figure 1 and the heat treatment temperature is 1100°C or higher, and the above phenomenon occurs without almost changing the existing structure within the silicon substrate. For this purpose, the heat treatment time is 1~
It is necessary that the time is 300 seconds.

When the heat treatment temperature exceeds 1150 DEG C., the layer resistance 9 of the polycrystalline silicon film-silicon substrate system increases rapidly as shown in FIG. This is because arsenic dissipates from the surface of the polycrystalline silicon film, and in order to prevent this arsenic from dissipating, a silicon oxide film or a silicon nitride film is deposited on the surface of the polycrystalline silicon film. The layer resistance above .degree. C. can be gradually reduced as shown by the solid line 10 in FIG.

1.5 x 1016 phosphorus in the above polycrystalline silicon film
ions/ci? , iQ, the layer resistance of the polycrystalline silicon film is as shown in Figure 7, the carrier concentration in the polycrystalline silicon film is as shown in Figure 8, and the average grain size of the polycrystalline silicon film is as shown in Figure 9. The layer resistance changes at lower temperatures than when the arsenic is introduced into the polycrystalline Noricon film.

The gearia concentration suddenly changes, and the polycrystalline/Noricon film turns into a single crystal. Indeed, when boron is introduced into the polycrystalline silicon film, the heat treatment temperature distribution at which various properties of the polycrystalline 7 silicon film suddenly change will be between those when phosphorus is introduced and when arsenic is introduced. .

As described above, a polycrystalline silicon film doped with impurities is formed on a silicon substrate and an insulating film.

The properties of the polycrystalline Noricon film suddenly change at 1 100'
In the heat treatment temperature range above CJ, 1/1 of the conventional heat treatment time
By performing the heat treatment with a heat treatment time of 1 to 300 seconds, which is less than 2, it is possible to form a shallow junction with a high carrier concentration in the silicon substrate in contact with the polycrystalline 7 silicon film. It becomes possible to lower the resistance of the polycrystalline silicon film without changing the element structure. Note that the heat treatment temperature needs to be below the melting temperature of silicon, but in practice it is set at 1300°C or below due to reasons such as the equipment used. If the heat treatment time exceeds 300 seconds, the extent to which impurities in the polycrystalline silicon film will diffuse into the silicon substrate will be limited.
This results in the formation of shallow junctions that are difficult to achieve, and also causes changes in the device structure within the silicon substrate.

[Embodiments of the invention]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 10 is an explanatory diagram of a first embodiment in which the present invention is applied to the manufacture of an npn transistor, where (aL(bL(C)) indicates each manufacturing process. As shown in FIG.
After forming the boron-introduced layer 12 by introducing 3 ions/d, a silicon oxide film 16 is formed, and a part of the silicon oxide film 13 is removed by etching, and the silicon substrate 11 and the silicon exposed in the opening are removed. Arsenic on the oxide film 16 at 1.5 x 1016 ions/c1? A polycrystalline silicon film 14 into which only L was introduced was formed. Next, according to the heat treatment temperature distribution 1 shown in FIG.
Heat treatment was performed for 30 seconds at a temperature not exceeding
), the arsenic in the polycrystalline silicon film 14 is diffused into the silicon substrate 11 to form the end diffusion layer 15.

Boron in the boron-introduced layer 12 is electrically activated.

npn with emitter depth 01μm and base depth 015μm
A transistor structure was formed. At this point, the polycrystalline silicon film 14 on the silicon substrate 11 indicated by the region 16 was made into a single crystal. Furthermore, as shown in FIG. 10(C), the polycrystalline silicon film 14 is removed leaving a region 16 by using the usual photoenotinking method, CVD method, and vapor deposition method, and a solicon oxide film 17 is formed in its place and then etched. After performing this, electrodes 18, 19, and 20 were provided, and a transistor was manufactured.

In the above embodiment, shallow junction formation by arsenic diffusion from the polycrystalline silicon film 14 is performed in the boron-introduced layer 1 of the silicon substrate 11.
Since the polycrystalline silicon film 14 under the emitter electrode 19 becomes monocrystalline, it can be used as the active region of the two emitters. Furthermore, only the region 16 of the polycrystalline silicon film 14 in contact with the silicon substrate 11 becomes monocrystalline.

The ratio of polycrystalline silicon to single crystal silicon is higher than the etching rate of the HF/HNO3 system, and the polycrystalline silicon film 14 is made into a monocrystalline region 16 in contact with the silicon substrate 11. without etching,
Since the other polycrystalline silicon film 14 can be etched, the process of photoetching the polycrystalline silicon film 14 can be simplified.

FIG. 11 is an explanatory diagram of another embodiment of the heat treatment of the above embodiment. After the process shown in FIG. 10(a), a 01 μm thick silicon oxide film (Amatake silicon nitride film) 21 was deposited on the polycrystalline silicon film 14, and the heat treatment temperature distribution 1 shown in FIG. 1200 which is even hotter than
Heat treatment was performed at °C for 15 seconds. In this example, 1200
Despite the high temperature heat treatment of °C.

By depositing the silicon oxide film (or silicon nitride film) 21, it is possible to prevent arsenic from escaping from the surface of the polycrystalline silicon film 14 and to reduce the layer resistance of the polycrystalline silicon film-silicon substrate system. The same effect as in the example shown in Fig. 10 above was obtained with a short heat treatment of 15 seconds. 6. In Fig. 12, a shallower bond was formed than in the example shown in Figs. 10 and 11 above. It is an explanatory view of another example. Boron-introduced layer 12 of n-type silicon substrate 11
' is formed shallower than the boron-introduced layer 12 of the above embodiment,
After forming a polycrystalline silicon film 14 doped with arsenic thereon.

According to the heat treatment temperature distribution 1 shown in FIG. 1, heat treatment is performed for 10 seconds at a temperature where the crystallinity of the heat treatment i' exceeds 1150'C, and arsenic is diffused into the upper F n-type/recon board 11 to form a deep diffusion layer. 15 was formed. At this point, the emitter depth of the transistor structure is 0.05 μm, the base depth is 0.01 μm, and the region 16' where the polycrystalline silicon film 14 on the silicon substrate 11 is made into a single crystal can be used as the active emitter region. Since shallow junctions are formed, the speed of semiconductor devices can be increased.

FIG. 16 is an explanatory diagram of a second embodiment in which the present invention is applied to the manufacture of MOS transistors, (a), (b), (C
) indicates each manufacturing process. Figure 13 (
As shown in a), a gate oxide film (005 μm thick) 23 and a field oxide film (
After forming O, allm thickness) 24, 3 X 1
A polycrystalline silicon film 25 doped with 0" 1 ons/(7) arsenic was formed to a thickness of 0.31 Lm. Next, as shown in FIG.
As shown in b), heat treatment is performed for 60 seconds at a heat treatment temperature that does not cause the heat treatment temperature distribution 1 to 1150°C as shown in FIG. S02Bm source and drain region 2
6 was formed, and the resistance of the polycrystalline silicon film 27, which is the gate, was lowered.

Polycrystalline soric film 27 on gate oxide film 23
The resistance was 5Ω/mouth. Further etching is performed to leave the polycrystalline silicon layer 1.27 on the gate oxide film 26, and after removing the other polycrystalline silicon film 25, a passover film 28 is formed as shown in FIG. 13(c). death,
An electrode 29 was formed using a photoetching method and a vapor deposition method to manufacture a Mos transistor.

As described above, the present invention can be used to manufacture a Mos+- transistor. In addition to forming shallow source and drain regions with a high carrier concentration, the resistance of the polycrystalline silicon gate 27 can be reduced, and furthermore, the resistance of the polycrystalline silicon gate 27 can be reduced. The diffusion of impurities into the silicon substrate has the effect of providing self-alignment in the formation of north and train formations in the silicon substrate.

〔Effect of the invention〕

As described above, the present invention is applied to a heat treatment temperature range of 1 1 D D 'C or above, where the characteristics of the polycrystalline silicon film into which impurities are introduced, on the surface of the solicon substrate and on the insulating film deposited on the surface of the substrate, suddenly change. Since the heat treatment is carried out at a temperature of 1 to 500 seconds, the polycrystalline silicon film becomes single crystallized, making it possible to form a shallow junction with a high carrier concentration, thereby making it possible to manufacture a semiconductor element with good characteristics at high speed. Also, polycrystalline silicon on a silicon substrate1. The single crystallization of the con film is
Since that portion can be used as an active region, it has a wide range of applications in semiconductor device manufacturing. Furthermore, since the resistance of the polycrystalline silicon film on the insulating film can be lowered without changing the structure of the existing element, the present invention has the advantage that it can be used for polycrystalline silicon wiring and electrodes with low resistance.

[Brief explanation of the drawing]

Figure 1 shows the heat treatment temperature distribution during impurity diffusion, Figure 2 shows the change in carrier concentration in the silicon substrate with respect to the heat treatment temperature, and Figure 6 shows the polycrystalline silicon film into which arsenic is introduced. FIG. 4 is a diagram showing changes in layer resistance, FIG. 4 is a diagram showing changes in carrier concentration in the polycrystalline silicon film, and FIG. 5 is a diagram showing changes in 5V average grain size of the polycrystalline silicon film. FIG. 6 is a diagram showing the change in layer resistance of the polycrystalline silicon film-silicon substrate system, FIG. Similarly, FIG. 9 is a diagram showing changes in the carrier concentration in the polycrystalline silicon film, FIG. 9 is a diagram similarly showing changes in the average crystal grain size of the polycrystalline silicon film, and FIG. The first applied
(a), (b), and (C) are diagrams showing the respective manufacturing steps, and FIG. 11 is a diagram showing the manufacturing process in which a silicon oxide film or a silicon nitride film is formed on a polycrystalline silicon film. Explanatory diagram of another example. FIG. 12 is an explanatory diagram of another embodiment in which a shallower junction than that of the above embodiment is formed, and FIG. 13 is an explanatory diagram of a second embodiment in which the present invention is applied to the manufacture of MO8I-Lancistor (a
), (b), and (C) are diagrams showing the respective manufacturing steps. 11.22.../recon board 15.25.24...insulating film (oxidation/recon film) 1
4.25 Polycrystalline silicon film representative patent attorney Junnosuke Nakamura ) 6th figure of the dragonfly cliff (°C) 177th figure of the koji force [°C]

Claims (1)

[Claims] After forming a polycrystalline silicon film into which impurities are introduced on the silicon substrate surface and an insulating film deposited on the silicon substrate surface, heat treatment is performed on the silicon substrate and polycrystalline silicon film to form a polycrystalline silicon film. When manufacturing semiconductor devices by diffusing impurities into the adjacent silicon substrate,
A method for manufacturing a semiconductor device, characterized in that the silicon substrate and the polycrystalline silicon film are heat-treated at a temperature of 1100° C. or higher and for a heat-treating time of 1 to 300 seconds.