JPH0750416A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To stably manufacture a MOS type transistor in excellent carrier mobility using polycrystalline silicon. CONSTITUTION:An etching stopper insulating film 14, a polycrystalline film 15 are selectively formed on a polycrystalline Si film 13 to be covered with another insulating film 16. Next, an amorphous Sr film is formed on the whole surface and then a polycrystalline Si film 18 is solid-grown using the polycrystalline Si film 13 as a seed crystal. Next, impurities are led into the polycrystalline Si film 15 by ion implanting step so as to form a source region 22, a drain region 23 and a channel region 24. At this time, the polycrystalline film 18 is grown using the polycrystalline Si film 13 as the seed crystal so that a crystal grain boundary may not be formed in the region in contact with the perpendicular wall of the insulating film 16. In such a constitution, when a channel is provided in this region wherein no crystal grain boundary disturbing a running carrier is formed, a MOS transistor in excellent carrier mobility equivalent to that of a single crystal transistor can be manufactured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device mainly composed of polycrystalline thin film transistors.

[0002]

2. Description of the Related Art Heretofore, as an example of a transistor using polycrystalline silicon, "Japanese Journal of Applied Physics" ((Japanese Jo
urnalof Applied Physics) Vol. 25, No. 2, L121-L123, 1986.
Year).

FIG. 5 is a sectional view showing the manufacturing method of the conventional semiconductor device in order of manufacturing steps. First, as shown in FIG. 5A, an insulating film 52 is formed on a silicon substrate 51, and an amorphous silicon layer 53 is formed thereon.
To form. As a method of forming the amorphous silicon layer 53, S
LPCVD (low pressure phase epitaxy) using iH4 or Si2 H6 is used. A gate oxide film 54 is formed on the amorphous silicon layer 53. A gate 55 is formed of polycrystalline silicon on the gate oxide film 54. An insulating film 56 is formed on the surface.

Next, as shown in FIG.
The amorphous silicon layer 53 is solid-phase-grown by performing a low temperature annealing heat treatment at about ° C to convert it into a polycrystalline silicon layer 57.

Next, as shown in FIG. 5C, an N-type (or P-type) impurity is introduced into the polycrystalline silicon layer 57 by an ion implantation method using the gate 55 as a mask to form a source region 58 and a drain. A region 59 and a channel region 60 are formed. Next, an interlayer insulating film 61 is deposited to cover the entire surface.

Next, as shown in FIG. 5D, the interlayer insulating film 61 and the gate oxide film 54 on the source region 58 and the drain region 59 are etched to form a contact opening, and metal deposition is performed. Then, selective etching is performed to form the source electrode 62 and the drain electrode 63. Then, the protective insulating film 64 is formed on the entire surface. Since the polycrystalline silicon transistor manufactured by such a manufacturing method can be formed on an insulating film, it is expected to be applied to a three-dimensional device or the like.

However, the polycrystalline silicon transistor is
Unlike a single crystal silicon transistor, a grain boundary exists in the active portion of the element, and carriers are captured at this grain boundary. This capture charges the grain boundaries positively or negatively, and forms a barrier potential that hinders carrier conduction. Therefore, the carrier mobility in the polycrystalline silicon transistor is lower than that in the single crystal transistor. That is, in the case of the device having the MOS structure as shown in FIG. 5, the number of crystal grain boundaries of the channel region 60 affects the characteristics of the transistor.

As a conventional example to improve this point, a material (for example, a silicon nitride film) having a high crystal nucleus generation rate is formed in advance at a predetermined position on the insulating film 52, and then the amorphous silicon layer 53 is formed. A method of forming on it, polycrystallizing it by heat treatment, and solid-phase growing only the active region of the device into a polycrystal with a large grain size was announced in 1990 in Solid State Device Material Conference Abstracts, page 1160. There is.

In such a manufacturing method, the grain size of the polycrystalline silicon layer 57 formed on the material having a high crystal nucleus generation rate is large, and the grain size of other regions is small. It is possible to control the particle size by using this method.

[0010]

However, in such a conventional polycrystalline film thin film transistor, since crystal nuclei are randomly generated during the heat treatment for polycrystallizing the amorphous layer, the crystal grain boundaries are not formed. There is a problem in that the number of devices varies and the device characteristics are not stable. In addition, when forming a material with a fast generation of crystal nuclei to control the crystal grain size, it is necessary to perform alignment when forming the crystal grain.

However, in the case of a crystal growth distance of about 1 μm, which is well known in the ordinary solid phase growth method, the active region of the element and the crystal grain boundary are strictly controlled due to the error in the mask alignment accuracy. It is difficult to control, and it is difficult to stably manufacture a transistor having desired characteristics. Therefore, the present invention is to provide a method of manufacturing a semiconductor device, which can stably manufacture a semiconductor device mainly using a polycrystalline thin film transistor having desired characteristics, using polycrystalline silicon.

[0012]

Therefore, in the method of manufacturing a semiconductor device according to the present invention as defined in claim 1, a first polycrystalline silicon film is formed on the upper surface of a substrate having at least an upper surface made of an insulator. Forming step, forming a first insulating film on the first polycrystalline silicon film, and second polycrystalline silicon film having a side wall perpendicular to a part of the first insulating film And a step of forming a second insulating film on the surface of the second polycrystalline silicon film, and removing the first insulating film in a region not in contact with the second polycrystalline silicon film. A step of forming an amorphous silicon film in contact with the second insulating film and the first polycrystalline silicon film, and the amorphous silicon film using the first polycrystalline silicon film as a seed crystal A heat treatment step of solid phase growing a third polycrystalline silicon film on the third polycrystalline silicon film, Configured to include a step of introducing an impurity into regions of the third polycrystalline silicon film of the upper portion and the third polycrystalline silicon film in contact with the first polycrystalline silicon film.

The method of the present invention according to claim 2 is characterized in that the first surface is formed on the upper surface of the substrate whose upper surface is at least an insulator.
Forming a polycrystalline silicon film, forming a first insulating film having a sidewall perpendicular to a part of the first polycrystalline silicon film, the first insulating film and the first insulating film, 1
Forming an amorphous silicon film in contact with the polycrystalline silicon film, and solid-phase growing the amorphous silicon film on the second polycrystalline silicon film by using the first polycrystalline silicon film as a seed crystal. A step of forming a second insulating film on the surface of the second polycrystalline silicon film, and an ion implantation of N-type or P-type impurities to form an upper portion of the first insulating film and the first polycrystalline film. A step of forming an impurity-doped region in a region of the second polycrystalline silicon film in a portion in contact with the crystalline silicon film; and a polycrystalline silicon film only on a side surface of the first insulating film next to the second insulating film. And a step of forming a side wall.

[0014]

According to the present invention, a method of converting the amorphous silicon into polycrystalline silicon and controlling the generation site of the crystal grain boundary is adopted. The first polycrystalline silicon film is used as a seed crystal for solid-phase growth to be converted into polycrystalline silicon, and a part of the amorphous silicon film is brought into contact with the first polycrystalline silicon film, but carriers travel and The channel region, which has a great influence on the characteristics, is formed in a region of the vertical wall in contact with the insulating film so as not to contact the first polycrystalline silicon film. Therefore, no crystal grain boundary is generated in the channel region. Therefore, a barrier potential that hinders carrier travel is not formed in the channel region, and a MOS semiconductor device having characteristics comparable to those of single crystal silicon can be obtained.

[0015]

1 and 2 are cross-sectional views showing a first embodiment of the present invention in the order of manufacturing steps. First,
As shown in FIG. 1A, a polycrystalline silicon film 13 is formed on a silicon substrate 11 having an insulating film 12. An insulating film 14 for an etch stopper is formed on this. As the etch stopper, for example, Si3 N4 is selected. A polycrystalline silicon film 15 is deposited on the etching stopper insulating film 14.

It is preferable to introduce impurities such as phosphorus in advance to reduce the resistance of the polycrystalline silicon film 15 and the thickness W is preferably 4 to 5 μm or less for the reason described later. This polycrystalline silicon film 15 is selectively etched to form islands having vertical walls. At this time, since the etching stopper insulating film 14 acts as an etching stopper, there is an advantage that the polycrystalline silicon film 13 thereunder is not etched. An insulating film 16 is formed on the surface of the polycrystalline silicon film 15.

Next, as shown in FIG. 1B, the exposed portion of the etching stopper insulating film 14 is removed by etching using the insulating film 16 as a mask. Next, the amorphous silicon film 17 is deposited on the entire surface.

Next, as shown in FIG. 2C, the silicon substrate 11 is heat-treated. Then, the amorphous silicon film 1
7, solid-phase growth occurs from the portion in contact with the polycrystalline silicon film 13, and the polycrystalline silicon film 18 is formed. Since the thickness of the polycrystalline silicon film 15 is set to about 4 to 5 μm or less, the crystal grain boundary 20 which is the boundary of the crystal grains 19 contacts the upper portion of the polycrystalline silicon film 15 and the polycrystalline silicon film 13. It is formed in the region of the polycrystalline silicon film 18 and is not formed in the region of the polycrystalline silicon film 18 on the side surface of the polycrystalline silicon film 15.

If the thickness W of the polycrystalline silicon film 15 is 4
When the thickness is more than 5 μm, crystal nuclei are generated on the side surface portion of the polycrystalline silicon film 15 in the solid phase growth process of converting amorphous silicon into polycrystalline silicon, and the side surface portion of the polycrystalline silicon film 15 is crystallized. There is a risk that grain boundaries will form. The thickness W of the polycrystalline silicon film 15 is set to 4 to 5 so that crystal grain boundaries are not formed on the side surfaces of the polycrystalline silicon film 15.
It is about μm or less.

Next, as shown in FIG. 2D, after an insulating film 21 is formed on the surface of the polycrystalline silicon film 18, the upper portion of the polycrystalline silicon film 15 and the polycrystalline silicon film 13 are formed by ion implantation. Polycrystalline silicon film 18 in contact with
N-type or P-type impurities are introduced into the region. At this time,
Impurities are not introduced into the side surface portion of the polycrystalline silicon film 15 to form the channel region 24. The source region 22 and the drain region 23 are formed by self-alignment by activating the implanted impurities by heat treatment.

Next, as shown in FIG. 2E, after the interlayer insulating film 25 is formed on the upper surface, the interlayer insulating film 25 and a part of the insulating film 21 are selectively etched and removed.
6 is formed. Then, the protective insulating film 27 is formed on the entire surface to complete the process.

As described above, in this embodiment, when the amorphous silicon film is converted into polycrystalline silicon as a layer forming each region of the transistor, it does not come into contact with the polycrystalline silicon film as a seed crystal for solid phase growth. Since the vertical wall is provided with a region in contact with the insulating film and the portion to be the channel region is located there, no crystal grain boundary is generated in this channel region. Therefore, a barrier potential that hinders the traveling of carriers is not formed in the channel region, a MOS semiconductor device having the same characteristics as single crystal silicon can be obtained, and the variation is very small, and the controllable manufacturing is possible. You can

FIGS. 3 and 4 are sectional views showing a second embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG. 3A, the insulating film 32 is formed on the upper surface of the silicon substrate 31, and the polycrystalline silicon film 33 is formed thereon. An insulating film is deposited on this, and anisotropic etching is performed to form an insulating film 34 having vertical walls.

Next, as shown in FIG. 3B, an amorphous silicon film 35 is deposited on the entire surface. Then, as shown in FIG. 4C, when the silicon substrate 31 is heat-treated, solid phase growth occurs in the amorphous silicon film 35 starting from the portion in contact with the polycrystalline silicon film 33, and the polycrystalline silicon film 36. Is formed. At this time, the crystal grain boundaries 38, which are boundaries of the crystal grains 37, are formed above the insulating film 34 and the polycrystalline silicon film
6 is formed in a region in contact with the polycrystalline silicon film 33, and is not formed in a region of the polycrystalline silicon film 36 in contact with the side surface of the insulating film 34.

Next, as shown in FIG. 4D, an insulating film 39 is formed on the surface of the polycrystalline silicon film 36. By ion implantation, the upper part of the insulating film 34 and the polycrystalline silicon film 33
An N-type or P-type impurity is introduced into the region of the polycrystalline silicon film 36 which is in contact with. At this time, no impurity is introduced into the region of the polycrystalline silicon film 36 on the side surface of the insulating film 34, which becomes the channel region 42. The source region 40 and the drain region 41 are self-aligned by heat treatment to activate the impurities.

Next, as shown in FIG. 4E, a polycrystalline silicon film is deposited on the entire surface, impurities such as phosphorus are introduced by a diffusion method or the like to reduce the resistance, and then the anisotropy is obtained. Etching is performed to form polycrystalline silicon sidewalls 43. Thereafter, as in the first embodiment, an interlayer insulating film is deposited, selective etching is performed to form a contact opening in the drain region, metal wiring is formed, and a protective insulating film is deposited on the entire surface to complete the process. To do. Also by this, the same effect as the previous embodiment can be obtained.

Although the silicon substrate having the insulating film on the upper surface is used as the substrate in the first and second embodiments, an insulating substrate may be used instead of this, and the same effect can be obtained.

[0028]

As described above, the present invention adopts the method of converting amorphous silicon into polycrystalline silicon.
Forming a second polycrystalline silicon film having a vertical side wall and covered with an insulating film on the polycrystalline silicon film, and forming an amorphous silicon film on the second polycrystalline silicon film; Since the solid phase growth is performed on the polycrystalline silicon, and the starting point of the crystal growth is limited to the portion in contact with the first and second polycrystalline silicon films excluding the side wall portion.
A polycrystalline silicon film having no grain boundaries on the vertical sidewalls is obtained. By using this portion as the active region of the element, the problem that the characteristics are unstable due to the capture of carriers at the crystal grain boundaries is solved, and the effect that the semiconductor device with good carrier mobility and stable characteristics can be easily manufactured. Have.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 4 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 5 is a diagram showing a manufacturing process of a conventional example.

[Explanation of symbols]

 11 Silicon Substrate 12 Insulating Film 13 Polycrystalline Silicon Film (First Polycrystalline Silicon) 14 Insulating Film for Etch Stopper (First Insulating Film) 15 Polycrystalline Silicon Film (Second Polycrystalline Silicon Film) 16 Insulating Film ( Second insulating film) 17 Amorphous silicon film 18 Polycrystalline silicon film (third polycrystalline silicon film) 19 Crystal grain 20 Crystal grain boundary 21 Insulating film 22 Source region 23 Drain region 24 Channel region 25 Interlayer insulating film 26 Metal wiring 27 Protective insulating film 31 Silicon substrate 32 Insulating film 33 Polycrystalline silicon film (first polycrystalline silicon film) 34 Insulating film (first insulating film) 35 Amorphous silicon film 36 Polycrystalline silicon film (second Polycrystalline silicon film) 37 crystal grains 38 crystal grain boundaries 39 insulating film (second insulating film) 40 source region 41 drain region 42 channel region 4 3 Sidewalls 51 Silicon Substrate 52 Insulating Film 53 Amorphous Silicon Layer 54 Gate Oxide Film 55 Gate 56 Insulating Film 57 Polycrystalline Silicon Layer 58 Source Region 59 Drain Region 60 Channel Region 61 Interlayer Insulating Film 62 Source Electrode 63 Drain Electrode 64 Protection Insulation film

Claims (3)

[Claims] 1. A step of forming a first polycrystalline silicon film on the upper surface of a substrate at least an upper surface of which is an insulator, and a first insulating film on the first polycrystalline silicon film. Forming a second polycrystalline silicon film having a side wall perpendicular to the first insulating film, and forming a second insulating film on the surface of the second polycrystalline silicon film. A step of forming a film, a step of removing the first insulating film in a region not in contact with the second polycrystalline silicon film, and a step of contacting with the second insulating film and the first polycrystalline silicon film A step of forming an amorphous silicon film, a heat treatment step of solid-phase growing the amorphous silicon film on a third polycrystalline silicon film by using the first polycrystalline silicon film as a seed crystal, and the third heat treatment step. Before contacting the upper part of the polycrystalline silicon film and the first polycrystalline silicon film And a step of introducing an impurity into the region of the third polycrystalline silicon film. 2. A step of forming a first polycrystalline silicon film on the upper surface of a substrate, at least an upper surface of which is an insulator, and a step of forming a first polycrystalline silicon film on a part of the first polycrystalline silicon film perpendicular to the upper surface. Forming a first insulating film having a side wall;
Forming an amorphous silicon film in contact with the insulating film and the first polycrystalline silicon film, and using the first polycrystalline silicon film as a seed crystal to form the amorphous silicon film into a second polycrystalline film. Solid phase growth on a silicon film, forming a second insulating film on the surface of the second polycrystalline silicon film, and ion-implanting N-type or P-type impurities into the first insulating film. Forming an impurity-doped region in a region of the second polycrystalline silicon film in a portion in contact with the upper portion and the first polycrystalline silicon film; and the second insulating film on a side surface of the first insulating film. And a step of forming a side wall of polycrystalline silicon only on the side of the semiconductor device. 3. The substrate having an insulator at least on the upper surface is a silicon substrate having an insulating film formed on the surface or an insulator substrate having an insulator as a whole.
Alternatively, the method of manufacturing the semiconductor device according to claim 2.