JPS59113619A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59113619A JPS59113619A JP22437182A JP22437182A JPS59113619A JP S59113619 A JPS59113619 A JP S59113619A JP 22437182 A JP22437182 A JP 22437182A JP 22437182 A JP22437182 A JP 22437182A JP S59113619 A JPS59113619 A JP S59113619A
- Authority
- JP
- Japan
- Prior art keywords
- amorphous silicon
- layer
- silicon layer
- impurity
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 23
- 238000009792 diffusion process Methods 0.000 claims abstract description 20
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims 2
- 230000008018 melting Effects 0.000 claims 2
- 239000012535 impurity Substances 0.000 abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052796 boron Inorganic materials 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 abstract description 4
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 229910021344 molybdenum silicide Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野 一
本発明は、主としてプレーナ型構造のきわめて浅い接合
領域を形成する拡散技術に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a diffusion technique for forming extremely shallow junction regions of primarily planar structures.
従来例の構成とその問題点
通常の拡散長の浅いプレーナ型装置においては、第１図
の断面図で示されるように、シリコン基板１に二酸化シ
リコン（５ｉＯ２）膜２をマスクとして開孔部を選択的
に設けた後、モリプシリサイドのようなシリサイド３を
開孔部に付着してこの上より不純物源４をイオン注入し
てから適轟な熱処理で不純物源４を活性化することによ
り、拡散ＰＮ接合領域５が形成されていた。Structure of the conventional example and its problems In a normal planar type device with a shallow diffusion length, as shown in the cross-sectional view of FIG. After being selectively provided, a silicide 3 such as molypsilicide is attached to the opening, an impurity source 4 is ion-implanted from above, and the impurity source 4 is activated by appropriate heat treatment. A diffused PN junction region 5 was formed.
この時拡散性さＸｊ はシリコン基板１に直接不純物
源４をイオン注入した場合に較べて、シリサイド層４の
ある場合の方が精度よく制御することができる。しかし
、ショートチャネル効果の殆んどないＭＯＳ ）ランシ
スターのソース、ドレーン領域やＧ［Ｉｚ帯で使用され
る。超高周波バイポーラトランジスタのエミッター、ベ
ース領域は、従来よシも更に拡散深さＸｊを小さくする
必要があり、又拡散領域の欠陥密度を一層減らす必要が
あった。At this time, the diffusivity Xj can be controlled more accurately when the silicide layer 4 is present than when the impurity source 4 is ion-implanted directly into the silicon substrate 1. However, it is used in the source and drain regions of MOS transistors (MOS transistors), which have almost no short channel effect, and in the G[Iz band. In the emitter and base regions of a super high frequency bipolar transistor, it is necessary to further reduce the diffusion depth Xj than in the past, and it is also necessary to further reduce the defect density in the diffusion region.
シリサイド層の存在はこれらの要求にある程度は応えて
きたが、性能の改善を図る上から、改良の余地があった
。Although the presence of a silicide layer has met these demands to some extent, there is still room for improvement in terms of improving performance.
発明の目的
本発明は上述のようなプレーナ型拡散接合の特性の向上
を図シ、極めて浅い拡散接合を有した半導体装置の製造
方法を提供するものである。OBJECTS OF THE INVENTION The present invention aims to improve the characteristics of the planar diffusion junction as described above and provides a method for manufacturing a semiconductor device having an extremely shallow diffusion junction.
発明の構成
本発明は、半導体基板に選択的開孔部を設ける工程、前
記開孔部にアモルファスシリコン層、及び高融点金属又
は高融点金属のシリサイド層を連続して付着する工程、
イオン注入及び熱処理工程をそなえた半導体装置の製造
方法であり、とくにアモルファスシリコン層を基板とシ
リサイド層間に設けてイオン注入拡散層の制御精度の向
上と結晶欠陥減少をはかることを特徴とする。Structure of the Invention The present invention comprises the steps of: providing a selective opening in a semiconductor substrate; successively depositing an amorphous silicon layer and a refractory metal or a silicide layer of a refractory metal in the opening;
A method for manufacturing a semiconductor device that includes ion implantation and heat treatment steps, and is particularly characterized by providing an amorphous silicon layer between a substrate and a silicide layer to improve control accuracy of the ion implantation diffusion layer and reduce crystal defects.
実施例の説明
第２図は本発明の実施例で製作された半導体装置の断面
図であり、第３図はイオン注入後の不純物濃度分布を示
す説明図である。まず第２図のように、Ｎ型シリコン基
板１０表面に通常の熱酸化法によって８０００人の厚さ
のＳｉＯ２膜２を形成し、ついでこの５ｉＯｚ膜２に周
知の方法によって開孔部を形成し、この開孔部内にアモ
ルファスシリコン層６を１００ＯＡ低温ＣＶＤ法で付着
後、引き続いてモリブデンシリサイド層３を約２００人
スパッター法で付着する。この後Ｐ型不純物であるボロ
ン４をアモルファスシリコン層６、モリブデンシリサイ
ド層３の付着された開孔部よりイオン注入し、熱処理を
行なうと、アモルファスシリコンは結晶化すると共に不
純物ボロンは活性化さもしＰ型シリコン基板１を使用し
た場合にはＰＮ接′合を形成するためイオン注入不純物
源としてＮ型不純物であるＡｓをボロンの代りに用いれ
ば良い。この時のイオン注入不純物の深さ方向の濃度分
布を第３図に示す。注入条件を適当に選んで不純物濃度
の最大になる位置がアモルファスシリコン層内６にくる
ようにするとシリサイド層３及び基板シリコンの拡散領
域５内の不純物濃度はアモルファスシリコン層６との界
面よりはなれるに従って減少する。この時第３図よシ分
かるようにアモルファスシリコン層６の存在によυ拡散
法さＸｊを極めて小さくすることができる。即ち浅い拡
散領域５を精度よく制御しながら実現することができる
ので、Ｘｊが１０００人より小さいような半導体素子も
可能になる。又イオン注入時に見られるチャネリング現
象もアモルファスシリコン層の存在によりほとんど緩和
されるので、濃度分布の再現性も良くなる。アモルファ
スシリコン層の存在はＸｊの制御に役立つのみならず、
イオン注入時に基板７リコン１に導入される結晶欠陥の
数も減少する。又アモルファスシリコン層６は熱処理す
ることにより結晶化するので電子及び正孔の拡散距離も
増大する。これらの事実、即ち結晶欠陥の数が減少する
こと、拡散距離が増大することは電気特性の改善、特に
逆方向漏洩電流の減少に大きく寄与する。発明者による
試作結果でも約１桁逆方向漏洩電流が小さくなることが
認められた。DESCRIPTION OF EMBODIMENTS FIG. 2 is a cross-sectional view of a semiconductor device manufactured according to an embodiment of the present invention, and FIG. 3 is an explanatory diagram showing an impurity concentration distribution after ion implantation. First, as shown in FIG. 2, a SiO2 film 2 with a thickness of 8,000 nm is formed on the surface of an N-type silicon substrate 10 by a normal thermal oxidation method, and then an opening is formed in this 5iOz film 2 by a well-known method. After an amorphous silicon layer 6 is deposited in this opening by a 100 OA low temperature CVD method, a molybdenum silicide layer 3 is subsequently deposited by a sputtering method using about 200 OA. After this, boron 4, which is a P-type impurity, is ion-implanted through the apertures where the amorphous silicon layer 6 and molybdenum silicide layer 3 are attached, and heat treatment is performed. As a result, the amorphous silicon crystallizes and the impurity boron is activated. When a P-type silicon substrate 1 is used, As, which is an N-type impurity, may be used instead of boron as an ion-implanted impurity source to form a PN junction. The concentration distribution of the ion-implanted impurity in the depth direction at this time is shown in FIG. If the implantation conditions are appropriately selected so that the maximum impurity concentration is located in the amorphous silicon layer 6, the impurity concentration in the silicide layer 3 and the diffusion region 5 of the substrate silicon will be lower than at the interface with the amorphous silicon layer 6. decreases according to At this time, as can be seen from FIG. 3, the presence of the amorphous silicon layer 6 allows the υ diffusion method length Xj to be made extremely small. That is, since the shallow diffusion region 5 can be realized while being controlled with high precision, a semiconductor device in which Xj is smaller than 1000 is also possible. Furthermore, since the channeling phenomenon observed during ion implantation is almost alleviated by the presence of the amorphous silicon layer, the reproducibility of the concentration distribution is also improved. The presence of the amorphous silicon layer not only helps control Xj, but also
The number of crystal defects introduced into the substrate 7 silicon 1 during ion implantation is also reduced. Furthermore, since the amorphous silicon layer 6 is crystallized by heat treatment, the diffusion distance of electrons and holes also increases. These facts, ie, a decrease in the number of crystal defects and an increase in the diffusion distance, greatly contribute to the improvement of electrical characteristics, particularly to the reduction of reverse leakage current. The inventor's trial production results also showed that the reverse leakage current was reduced by about one order of magnitude.
熱処理の役目はアモルファスシリコンの結晶化とイオン
注入不純物の活性イヒであるが、今この熱処理を二段階
に分けて６００−７００°Ｃでのアモ・レファスシリコ
ンの結晶化、９００〜１０００℃のイオン注入不純物の
活性化及び拡散としてもよい。The role of heat treatment is to crystallize amorphous silicon and activate the ion-implanted impurities, but this heat treatment is now divided into two stages: crystallization of amorphous silicon at 600-700°C, and crystallization of amorphous silicon at 900-1000°C. Activation and diffusion of ion-implanted impurities may also be used.
二段階熱処理の場合は多少Ｘｊが増大するが、あらかじ
めアモルファスシリコン層を通して十分に制御された量
の不純物がイオン注入されているので、浅い拡散接合を
作る点からみてなんら不都合は認められなかった。In the case of the two-step heat treatment, Xj increases somewhat, but since a well-controlled amount of impurity ions are implanted in advance through the amorphous silicon layer, no disadvantage was observed from the point of view of forming a shallow diffusion junction.
一方アモルファスシリコン層の上部に付着したシリサイ
ド層はパターンの微細化に伴なうコンタクト抵抗の増大
を防ぎ、電極金属としてアルミを使用した場合、実用上
問題のないオーミック配線が得られた。On the other hand, the silicide layer attached to the top of the amorphous silicon layer prevented an increase in contact resistance due to pattern miniaturization, and when aluminum was used as the electrode metal, an ohmic interconnect with no practical problems was obtained.
発明の効果
本発明によればアモルフ、アスシリコン層、シリサイド
層の上よりイオン注入したことにより、極めて浅いＰＮ
接合を精度よく制御しながら作れるので、微細パターン
の半導体装置の実現が可能である。とりわけノヨートチ
ャネル効果のないＭＯＳトランジスターや、浅いエミッ
ター、ベース接合の超高周波バイポーラトランジスタに
有効で、配線抵抗が小さくなる他、逆方向電流の減少と
、特性のバラツキが小さくなる。Effects of the Invention According to the present invention, by implanting ions from above the amorph, asilicon layer, and silicide layer, extremely shallow PN
Since the bonding can be manufactured while precisely controlling it, it is possible to realize semiconductor devices with fine patterns. It is particularly effective for MOS transistors without the Noyoto channel effect and ultra-high frequency bipolar transistors with shallow emitter and base junctions, reducing wiring resistance, reducing reverse current, and reducing variation in characteristics.
第１図は従来例選択ＰＮ接合拡散領域を形成した半導体
装置の断面図、第２図は本発明実施例で得られる半導体
装置の断面図、第３図は本発明の実施例で得られるイオ
ン注入熱処理後の不純物濃度分布図である。
１・・・シリコン基板、２・・・・ＳｉＯ２膜、３・・
・シリサイド層、４・・・・イオン注入不純物、５・・
・・拡散領域、６・・・・アモルファスシリコン層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名−城
藪 ２ ′FIG. 1 is a cross-sectional view of a semiconductor device in which a conventional selective PN junction diffusion region is formed, FIG. 2 is a cross-sectional view of a semiconductor device obtained in an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a semiconductor device obtained in an embodiment of the present invention. FIG. 3 is an impurity concentration distribution diagram after implantation heat treatment. 1... Silicon substrate, 2... SiO2 film, 3...
・Silicide layer, 4...Ion implantation impurity, 5...
...Diffusion region, 6...Amorphous silicon layer. Name of agent: Patent attorney Toshio Nakao and one other person - Shiroyabu 2'
Claims (2)
開孔部にアモルファスシリコン、高融点金属又は高融点
金属のシリサイド層をこの順序に付着する工程、イオン
注入及び熱処理により前記開孔部直下にＰＮ接合拡散領
域を形成する工程をそなえた半導体装置の製造方法。(1) A step of selectively forming an opening in a semiconductor substrate, a step of attaching amorphous silicon, a high melting point metal, or a silicide layer of a high melting point metal to the opening in this order, and a step of forming the opening by ion implantation and heat treatment. A method for manufacturing a semiconductor device comprising a step of forming a PN junction diffusion region immediately below the part.
程、９００°Ｃ〜１ｏ００°Ｃの第二熱処理工程の二段
階を有した特許請求の範囲第１項に記載の半導体装置の
製造方法。(2) Manufacturing a semiconductor device according to claim 1, in which the heat treatment has two steps: a first heat treatment step at 60°C to 700°C, and a second heat treatment step at 900°C to 100°C. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22437182A JPS59113619A (en) | 1982-12-20 | 1982-12-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22437182A JPS59113619A (en) | 1982-12-20 | 1982-12-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59113619A true JPS59113619A (en) | 1984-06-30 |
Family
ID=16812702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22437182A Pending JPS59113619A (en) | 1982-12-20 | 1982-12-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59113619A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6293929A (en) * | 1985-10-21 | 1987-04-30 | Toshiba Corp | Manufacture of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5165561A (en) * | 1974-10-18 | 1976-06-07 | Siemens Ag | |
| JPS5780768A (en) * | 1980-11-07 | 1982-05-20 | Fujitsu Ltd | Semiconductor device |
-
1982
- 1982-12-20 JP JP22437182A patent/JPS59113619A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5165561A (en) * | 1974-10-18 | 1976-06-07 | Siemens Ag | |
| JPS5780768A (en) * | 1980-11-07 | 1982-05-20 | Fujitsu Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6293929A (en) * | 1985-10-21 | 1987-04-30 | Toshiba Corp | Manufacture of semiconductor device |
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