JPH04130731A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize that the formation position of a gettering site and the defect density at the gettering site are made optimum by a method wherein the gettering site is formed by an ion implantation operation. CONSTITUTION:For example, boron ions or the like are first implanted, from the main face side, into a semiconductor substrate 1 made of a p-type silicon wafer. At this time, their ion implantation amount is set in such a way that a crystal structure is not made continuously amorphous. Then, the semiconductor substrate 1 is heat-treated in an inert-gas atmosphere. At this time, a gettering site 2 is formed in a region into which the ions have been implanted, and the main-face-side outer layer of the semiconductor substrate 1 damaged by the implanted ions is made defectless. Then, an epitaxial growth film 3 is formed on the semiconductor substrate 1; and an element formation layer 4 is formed of the layer and of the main-face-side outer layer at the defectfree semiconductor substrate 1. After that, a MOSFET 10 is formed on the semiconductor substrate 1 by an ordinary manufacturing process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a manufacturing technology for semiconductor integrated circuit devices, and particularly to gettering technology.

[Conventional technology]

In recent years, in semiconductor integrated circuit devices, element miniaturization,
High integration is progressing. However, as elements become smaller and more highly integrated, the margin for noise that degrades signal charge retention characteristics, for example, is becoming smaller and smaller. Therefore, it is necessary to reduce the density of crystal defects that are centers of charge generation and recombination that induce noise. The crystal defects that induce this noise may exist alone in the semiconductor substrate, but in many cases, crystal defects and iron (Fe) or tungsten (
It exists in a complex with heavy metal atoms such as W). The latter defect is more electrically active than the former, and p
Increase in leakage current in n-junction and DRAM (D
dynamic RAM) is a main factor in deteriorating the electrical characteristics of the device, such as shortening the time. In order to avoid such problems, gettering technology that inactivates crystal defects or harmful impurities has become increasingly important in recent years.

For gettering technology, see, for example, "Journal of Applied Physics," published by the Japan Society of Applied Physics, February 1978, P139-P1.
42, mechanical gettering (hereinafter referred to as
MG) method, intrinsic gettering (hereinafter referred to as MG) method, etc.

The MG method is a technique in which a strain field is formed on the back side of a semiconductor substrate and the strain field is used as a gettering site.

To form a strain field on the back surface of a semiconductor substrate, there are, for example, a method of ion-implanting predetermined atoms from the back surface side of the semiconductor substrate, a method of polishing the back surface of the semiconductor substrate, and the like.

By the way, in order to improve the gettering effect, it is effective to reduce the distance between the element and the gettering site as much as possible. However, in the MG method, the gettering site is formed on the back side of the semiconductor substrate, so the distance between the element and the gettering site cannot be shortened. That is,
The MG method does not provide a sufficient gettering effect. Therefore, the IC method is adopted, which allows the distance between the element and the gettering site to be relatively short. According to the IC method, the distance can be reduced to about 1/10 of the MG method.

In the IG method, oxygen dissolved in a semiconductor substrate is precipitated by heat treatment, and a complex of the precipitate and secondary defects such as dislocations generated due to the precipitation is formed in the semiconductor substrate, and this is used as a gettering site. This is a technology that The IC method consists of low temperature heat treatment, high temperature heat treatment and medium temperature heat treatment. The first low-temperature heat treatment is a heat treatment to form precipitation nuclei,
Heat treatment is carried out at about 600 to 800°C for about 2 hours. The subsequent high-temperature heat treatment is a heat treatment that reduces oxygen on the surface of the semiconductor substrate by outward diffusion and eliminates oxygen precipitation nuclei.

At this time, a secondary defect layer that becomes a gettering site is formed in the semiconductor substrate, and a defect-free layer that becomes an element formation region is formed on the surface layer on the main surface side of the semiconductor substrate. According to the IC method, the thickness of the defect-free layer can be approximately 10 μm. The high-temperature heat treatment is performed at about 1100° C. or higher for about 1 hour. The final medium-temperature heat treatment is a treatment that aggregates oxygen to the precipitation nuclei and increases the precipitation, thereby increasing the gettering effect. The medium temperature heat treatment includes heat treatment at about 950 to 1000°C for 5 to 6 hours.

[Problem to be solved by the invention]

However, in the above conventional IG method, the following (1)
The present inventor has discovered that there are the following problems.

(1) In the case of the IG method, the surface layer of the semiconductor substrate is made defect-free by outward diffusion of oxygen, but due to non-uniform oxygen concentration and oxygen precipitation in the substrate crystal and lowering of the process temperature, the semiconductor substrate becomes defect-free. It is becoming difficult to form a defect-free layer with a uniform thickness on the surface. For this reason, a certain margin must be allowed for the thickness of the defect-free layer, and it is impossible to form the defect-free layer any thinner (eg, 10 μm or less). That is, the distance between the gettering site and the element cannot be made any thinner. For this reason, there was a problem in that the improvement of the gettering effect was inhibited.

(2) In recent years, for example, MG3・F
In some cases, an ET and a bipolar transistor are formed. In such a case, the optimal position for forming the gettering site (plane position, right side of the lid and depth position) differs depending on each element. However, since the conventional IG method cannot control the formation position of the gettering site, it cannot cope with such a case and has the problem of not being able to obtain a sufficient gettering effect.

(3) Furthermore, in the conventional IC method, it is difficult to control the defect density at the gettering site, and there is a problem in that the defect density is excessive or insufficient. That is, if the defect density is too low, the gettering effect will be reduced, and if the defect density is too high, the plastic deformation strength of the crystal will be weakened, causing problems such as thermal stress dislocation.

(4) Furthermore, in the conventional IG method, gettering sites are formed using precipitation due to supersaturation of oxygen contained in the semiconductor substrate, so for example, FZ (Floating
Zone) law and MCZ (Magnetic field) law
d Semiconductor substrates with low oxygen content manufactured by the Czochralski method or SOI (Sil
There is a problem in that it cannot be applied to an icon-on-insulator (icon-on-insulator) substrate.

The present invention has been made with attention to the above-mentioned problems, and its purpose is to provide a technique that can optimize the formation position of gettering sites.

Another object of the present invention is to provide a technique that can improve the gettering effect.

Another object of the present invention is to provide a technique that can optimize not only the formation position of gettering sites but also the defect density.

Still another object of the present invention is to provide a technique that can form gettering sites even in semiconductor substrates and SOI substrates with low oxygen concentrations.

The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the invention as claimed in claim 1 provides that after ion-implanting predetermined atoms from the main surface side of the semiconductor substrate so that the crystal structure thereof does not become continuously amorphous, the semiconductor substrate is ion-implanted in a non-oxidizing gas atmosphere. A method for manufacturing a semiconductor integrated circuit device, wherein a heat treatment is performed to make a surface layer on a main surface side of the semiconductor substrate defect-free, a gettering site is formed in the semiconductor substrate, and an epitaxial growth film is formed on the semiconductor substrate. be.

[Effect]

According to the first aspect of the invention, since the gettering site is formed by ion implantation, the planar position of the gettering site can be controlled with high accuracy. Further, by controlling the ion implantation depth and the film thickness of the epitaxially grown film, the depth position of the gettering site can also be controlled with high precision. Furthermore, in the case of ion implantation,
Since the concentration of the implanted impurity and the in-plane uniformity of the concentration can be controlled with high precision, the defect density at the gettering site can also be controlled with high precision. Since the amount of ion implantation is set so that the crystal structure in the surface layer on the main surface side of the semiconductor substrate immediately after ion implantation does not become continuous and amorphous, no dislocation or the like occurs in the epitaxially grown film. Furthermore, since gettering sites are formed by ion implantation, it can also be applied to semiconductor substrates and SOI substrates with low oxygen concentrations.

[Embodiment 1] FIGS. 11(a) to 11(d) are sectional views of essential parts of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

Hereinafter, in Example 1, a MOS-F is provided on the semiconductor substrate.
A method of manufacturing a semiconductor integrated circuit device will be described using an example of forming an ET.

First, as shown in FIG. 1(a), for example, boron (B)
ion or carbon (C) ion at 50 to 15 QKe
It is accelerated to approximately V and is implanted into a semiconductor substrate 1 made of a p-type silicon (Sl) wafer from its main surface side.

At this time, care should be taken to keep the ion implantation amount to a low concentration. That is, the ion implantation amount is set to such an extent that the crystal structure in the surface layer on the main surface side of the semiconductor substrate 1 immediately after ion implantation does not become continuously amorphous. This is because if the crystal structure in the surface layer on the main surface side of the semiconductor substrate 1 is continuously amorphous, dislocations etc. will be formed in the film when an epitaxially grown film is formed on the main surface side of the semiconductor substrate 1 as described later. This is to suppress such phenomena.

In Example 1, for example, the ion implantation amount is set to (2 to 1
0) X 10'4 pieces/cII+2 approximately.

Subsequently, the semiconductor substrate 1 is subjected to, for example, RTA (Rap
id Thermal Anneal) or the like. PTA is a method of heat-treating semiconductor substrates 1 one by one. The method is as follows, for example.

That is, the semiconductor substrate 1 is housed in an inert gas atmosphere such as nitrogen (N2) gas, and the processing temperature is set to 1000 to 1
Heat treatment is performed for a short time of about 5 to 60 seconds at a temperature of about 200°C. At this time, as shown in Fig. 1 et al., gettering sites 2 are formed in the region of the semiconductor substrate 1 into which ions have been implanted, and the surface layer on the main surface side of the semiconductor substrate 1, which has been damaged by the ion implantation, is made defect-free. do. In this case, defect-free means MOS
- This means that it does not adversely affect the electrical characteristics of the FET and does not cause dislocations in the epitaxially grown film.

Note that the heat treatment is not limited to PTA.

Next, as shown in FIG. 1(C), for example, silane (S
An epitaxial growth film 3 is formed on a semiconductor substrate 1 by a CVD method using iH, hydrogen (N2) based gas. In Example 1, the element forming layer 4 is formed by the surface layer on the main surface side of the semiconductor substrate 1 which has been made defect-free and the epitaxially grown film 3. Here, the depth position of the gettering site 2 can be set with high precision using acceleration energy during ion implantation. Further, the thickness of the epitaxially grown film 3 can also be set with high precision. Therefore, according to the first embodiment, the thickness of the element forming layer 4 can be set with high precision, and the MOS-FE
It becomes possible to make the distance between T and gettering site 2 very short. In the first embodiment, it is also possible to set the distance to about 0.2 μm. However, the thickness of the element formation layer 4 is made to be thicker than the depletion layer of the MOS-FET.

After that, through the normal manufacturing process of MOS-FET,
As shown in FIG. 1(6), after the field insulating film 5 is formed in the element isolation region, there is a leak in the element formation region. I(AS
) and an n-type impurity such as phosphorus (P), and further a gate insulating film 7, a gate electrode 8,
A source electrode 9a and a drain electrode 9b are formed and MO
An S-FETl0 is formed on a semiconductor substrate 1.

As described above, according to the first embodiment, it is possible to obtain the following effects.

(1) The depth position of the gettering site 2 can be controlled with high precision by setting the ion implantation conditions and the thickness of the epitaxially grown film 3.

That is, the depth position of the gettering site 2 can be optimized. Therefore, gettering site 2 is MO
It becomes possible to form the S-FETIO in close proximity to the S-FETIO.

(2) In the case of ion implantation, since the concentration of the implanted impurity and the in-plane uniformity of the concentration can be controlled with high precision, the defect density at the gettering site 2 can also be controlled with high precision. That is, the defect density at the gettering site 2 can be optimized.

(3) According to (2) above, it becomes possible to suppress a decrease in the gettering effect due to insufficient defect density at the gettering site 2.

(4) According to (2) above, it becomes possible to suppress the occurrence of thermal stress dislocation caused by excessive defect density at the gettering site 2.

(5), the above (1), and (3) make it possible to significantly improve the gettering effect. For example, conventional 1
The leakage current of the pn junction, which was about 0'A/cm'', was determined by IQ.
-'A/cm''.

(6) By setting the ion implantation amount so that the crystal structure in the surface layer on the main surface side of the semiconductor substrate 1 immediately after ion implantation does not become continuous and amorphous, the phenomenon of dislocations etc. occurring in the epitaxially grown film 3 is suppressed. becomes possible.

(7) With the above (1) to (6), it is possible to significantly improve the yield and reliability of semiconductor integrated circuit devices.

(8) Since the gettering site 2 is formed by ion implantation, it is possible to form the gettering site 2 even in a semiconductor substrate with a low oxygen concentration manufactured by the FZ method, the MCZ method, or the like.

[Example 2] '! 21! I(a) to I(a) are sectional views of main parts of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

In the second embodiment, a method for manufacturing a semiconductor integrated circuit device will be described below, taking as an example a case in which a bipolar transistor is formed on an SOI substrate (semiconductor substrate) formed by forming a single crystal S1 layer on an insulating film.

The SOI substrate 11 is shown in FIG. 2(a). SOI substrate 11
is a semiconductor layer 12, an insulating film layer 13 formed on the semiconductor layer 12, and a semiconductor layer 14 formed on the insulating film layer 13.
It is composed of. The semiconductor layer 12.14 is made of, for example, single crystal s1. The thickness of the semiconductor layer 14 is, for example, 1
It is about μm.

Further, the insulating film layer 13 is made of, for example, silicon dioxide (S102
).

After forming a photoresist (hereinafter simply referred to as resist) pattern 15a on the semiconductor layer 14 of the SOI substrate 11, using the resist pattern 15a as a mask, carbon ions or S1 ions are applied to the semiconductor layer 14.
selectively introduced into four predetermined planar positions. The acceleration energy and the amount of ions introduced at this time are the same as in Example 1 above.

Subsequently, after removing the resist pattern 15a and cleaning the SOI substrate 11, the SOI substrate 11 is subjected to heat treatment such as RTA as in the first embodiment. At this time, as shown in FIG. 2 et al., gettering sites 2 are formed at predetermined planar positions of the semiconductor layer 14, and the surface layer on the main surface side of the semiconductor layer 14, which has been damaged by the ion implantation, is made defect-free. .

Next, as shown in FIG. 2C, a first epitaxial growth film 3a is formed on the semiconductor layer 14 of the SOI substrate 11 by, for example, a CVD method using SIH4Ha-based gas. The thickness of the first epitaxially grown film 3a is
For example, it is about 1 μm.

Subsequently, the first epitaxially grown film 3a is coated with, for example, A.
An n-type impurity such as s is diffused to form a collector buried layer BL. Then, N2 is applied to the Sol substrate 11.
Heat treatment is performed in an inert gas atmosphere such as gas. At this time, the impurity ions implanted into the epitaxially grown film 3a are electrically activated.

Thereafter, as shown in FIG. 2(d), a second epitaxial growth film 3b is formed on the first epitaxial growth film 3a in the same manner as the first epitaxial growth film 3a. The thickness of the second epitaxially grown film 3b is, for example, 1
It is about μm.

Next, as shown in FIG. 2(e), grooves 16 for element isolation (and electrode isolation) are formed. Next, the second
As shown in Figure (f), an oxide film 17 is buried in the groove 16. Thereafter, using the resist pattern 15b as a mask, p-type impurities such as boron are ion-implanted into predetermined planar positions of the second epitaxial growth film 3b. Then, heat treatment is performed on the SOI substrate 11 in an inert gas atmosphere to form a base region 18 in the second epitaxial growth film 3b as shown in FIG. After removing the resist 15b shown in FIG. 2 and cleaning the SO substrate 11, an emitter region 19 is formed in the base region 18 as shown in FIG. A collector electrode 20c is formed to form a bipolar transistor 21.

As described above, according to the second embodiment, it is possible to obtain the following effects.

(1) The gettering site 2 can be formed very close to the bipolar transistor 21, and the defect density in the gettering site 2 can be optimized.

[2) With the above (1), it becomes possible to significantly improve the gettering effect. As a result, it is possible to suppress the occurrence of breakdown voltage defects between the collector region, the base region 18, and the emitter region 19, for example.

(3) Since the gettering sites 2 are formed by ion implantation, the gettering sites 2 can also be formed on the SOI substrate 11.

(4) According to (1) to (3) above, it is possible to improve the yield and reliability of a semiconductor integrated circuit device using the SOI substrate 11.

[Embodiment 3] FIGS. 3(a) to 3(f) are sectional views of essential parts of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

In the third embodiment, a case will be described in which gettering sites are formed at predetermined planar and depth positions of a semiconductor substrate.

First, as shown in FIG. 3(a), after forming a resist pattern 15C on the semiconductor substrate 1, using the resist pattern 15C as a mask, for example, boron ions, carbon ions, or Si ions are applied to the main surface of the semiconductor substrate 1. selectively introduced into a predetermined position on the side. The acceleration energy and ion implantation amount at this time are the same as those in Example 1.2.

Subsequently, after removing the resist pattern 15C and cleaning the semiconductor substrate 1, the semiconductor substrate 1 is subjected to heat treatment such as RTA as in the first and second embodiments. At this time, as shown in FIG. 3(c), a first gettering site 2a is formed at a predetermined planar position of the semiconductor substrate l, and the surface of the main surface of the semiconductor substrate 1 damaged by the ion implantation is to be defect-free.

Thereafter, as shown in FIG. 3(C), a first epitaxial growth film 3a is formed on the semiconductor substrate 1 in the same manner as in the second embodiment. The thickness of the first epitaxially grown film 3a is, for example, about 1 μm.

Next, as shown in FIG. 3(d), a resist pattern 15d is formed on the first epitaxially grown film 3a. The resist pattern 15d is formed so as to be located above the above-mentioned gettering ring 2a.

Next, using the resist pattern 15d as a mask,
For example, boron ions, carbon ions, or Si ions are selectively introduced into predetermined planar positions of the epitaxially grown film 3a. The acceleration energy and the amount of ions introduced at this time were the same as those in Example 1.2.

After that, the resist 15d is removed and the semiconductor substrate 1 is cleaned, and then the semiconductor substrate 1 is subjected to heat treatment such as RTA in the same manner as in Example 1.2. At this time, as shown in Figure 3 (
As shown in e), a second gettering site 2b is formed at a predetermined planar position of the epitaxially grown film 3a, and the surface layer on the main surface side of the epitaxially grown film 3a damaged by ion implantation is made defect-free.

Next, as shown in FIG. 3 (0), a second epitaxial growth film 3b is formed on the first epitaxial growth film 3a in the same manner as the first epitaxial growth film 3a.

The thickness of the second epitaxially grown film 3b is, for example, 1μ.
It is about m. In this way, the semiconductor substrate 1 is provided with gettering rings (2a, 2) with different planar positions and depth positions.
form b. After that, predetermined elements are formed in region A and region C. Region B is an element isolation region.

In this way, according to the third embodiment, gettering sites 2a having different planar positions and depth positions are provided on the semiconductor substrate 1.
2b can be formed.

Therefore, even if, for example, a MOS-FET and a bipolar transistor are formed on the semiconductor substrate 1, the gettering sites 2a and 2b can be formed at optimal positions for these elements, improving the gettering effect. It becomes possible to do so.

The invention made by the present inventor has been specifically explained based on Examples above, but the present invention is not limited to Examples 1 to 3, and can be modified in various ways without departing from the gist thereof. Needless to say.

For example, in Examples 1 to 3, the case where the ion implantation method was used to form the gettering site was described, but the invention is not limited to this. For example, the focused ion beam implantation method may also be used. good. In this case, it becomes possible to cope with higher integration and thinner films.

Further, in Examples 1 to 3, a heat treatment process such as RTA is added after ion implantation, and then epitaxial growth is performed, but the following method is also possible. That is, before performing epitaxial growth, the semiconductor substrate is usually subjected to preheating treatment in a non-oxidizing gas atmosphere such as H2 gas from the viewpoint of cleaning the semiconductor substrate surface, but at that time, ion It is also possible to make the surface of the semiconductor substrate defect-free after implantation and to form gettering sites. In this case, it becomes possible to reduce the number of processing steps.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

That is, according to the first aspect of the invention, since the gettering site is formed by ion implantation, the planar position of the gettering site can be controlled with high precision. Also,
By controlling the ion implantation depth and the film thickness of the epitaxially grown film, the depth position of the gettering site can also be controlled with high precision. That is, it becomes possible to optimize the formation position of the gettering site. For this reason,
It becomes possible to form gettering sites near the element. Furthermore, even in the case where MOS-FETs and bipolar transistors are mixed on a semiconductor substrate, gettering sites can be formed at optimal positions according to each element. These make it possible to significantly improve the gettering effect.

In addition, in the case of ion implantation, the concentration of implanted impurities and the in-plane uniformity of that concentration can be controlled with high precision.
Defect density at gettering sites can also be optimized.

Since the amount of ion implantation is set so that the crystal structure on the main surface side of the semiconductor substrate immediately after ion implantation does not become continuous and amorphous, no dislocation or the like occurs in the epitaxially grown film. As a result, the gettering effect decreases due to insufficient defect density at the gettering site, thermal stress dislocation occurs due to excessive defect density, and dislocations etc. occur in the epitaxially grown film due to implantation of high concentration ions. It becomes possible to suppress the phenomenon of formation.

Furthermore, since gettering sites are formed by ion implantation, gettering sites can be formed even in semiconductor substrates and SOI substrates with low oxygen concentrations.

[Brief explanation of the drawing]

1(a) to 1(d) are cross-sectional views of essential parts of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. A cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention, FIGS. 1 is a cross-sectional view of essential parts of a semiconductor substrate shown in FIG. ...field insulating film, 6
... Diffusion layer, 7... Gate insulating film, 8... Gate electrode, 9a... Source electrode, 9b... Drain electrode, 10... MOS-FET, 11... SOI substrate< semiconductor substrate), 12.14... semiconductor layer, 13...
・Insulating film layer, 15a to 15d...Resist, 16...
groove, 17... oxide film, 18... base region, 19.
...Emitter region, 20a...Base electrode, 20b.
...Emitter electrode, 20c...Collector electrode, 21.
...Bipolar transistor, BL...''Rector buried layer, A-C...area.

Claims (1)

[Claims] 1. After ion-implanting predetermined atoms from the main surface side of the semiconductor substrate so that the crystal structure does not become continuously amorphous, the semiconductor substrate is heat-treated in a non-oxidizing gas atmosphere. A semiconductor integrated circuit device, characterized in that the surface layer on the main surface side of the semiconductor substrate is made defect-free by performing the following steps, a gettering site is formed in the semiconductor substrate, and an epitaxially grown film is further formed on the semiconductor substrate. Production method. 2. The gettering site was formed at a predetermined planar position of the semiconductor substrate, and predetermined atoms were ion-implanted into a planar position different from the gettering site in the epitaxially grown film so that the crystal structure did not become continuous and amorphous. After that, the semiconductor substrate is heat-treated in a non-oxidizing gas atmosphere to make the surface layer on the main surface side of the epitaxially grown film defect-free and to form a second gettering site in the epitaxially grown film. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising forming gettering sites at different planar positions and depth positions on the semiconductor substrate.