WO2010016457A1 - Epitaxial silicon wafer and method for production thereof - Google Patents

Epitaxial silicon wafer and method for production thereof Download PDF

Info

Publication number
WO2010016457A1
WO2010016457A1 PCT/JP2009/063740 JP2009063740W WO2010016457A1 WO 2010016457 A1 WO2010016457 A1 WO 2010016457A1 JP 2009063740 W JP2009063740 W JP 2009063740W WO 2010016457 A1 WO2010016457 A1 WO 2010016457A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
epitaxial
carrier dopant
silicon
single crystal
Prior art date
Application number
PCT/JP2009/063740
Other languages
French (fr)
Japanese (ja)
Inventor
英一 浅山
尚志 足立
民雄 本山
光二 松本
和尚 鳥越
Original Assignee
株式会社Sumco
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社Sumco filed Critical 株式会社Sumco
Publication of WO2010016457A1 publication Critical patent/WO2010016457A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

Definitions

  • the present invention relates to an epitaxial silicon wafer and a manufacturing method thereof.
  • CZ-Si substrates grown by the CZ method have been used for highly integrated silicon semiconductor devices.
  • supersaturated interstitial oxygen is in the order of about 10 18 atoms / cm 3 for these CZ-Si substrates. It is well known that crystal defects such as oxygen precipitates, dislocations and stacking faults are induced in the device manufacturing process.
  • an epitaxial silicon wafer obtained by growing an epitaxial layer almost completely free of crystal defects on a CZ-Si substrate is often used for highly integrated devices.
  • Gettering technologies include intrinsic gettering (IG) using crystal defects caused by oxygen naturally induced during heat treatment of device processes as a sink, and sand blasting, Si 3 N 4 film, or Poly-Si film growth. There is an extrinsic gettering (EG) typified by back surface distortion.
  • IG intrinsic gettering
  • EG extrinsic gettering
  • MCPs multi-chip packages
  • Patent Document 1 and Patent Document 2 propose an epitaxial wafer including a layer containing a non-carrier dopant on a Si substrate.
  • the problem to be solved by the present invention is to provide an epitaxial silicon wafer having high gettering ability even if the integrated circuit substrate is thinned.
  • An epitaxial silicon wafer and a manufacturing method thereof according to the present invention are epitaxial silicon wafers having a silicon epitaxial layer on a main surface of a silicon single crystal substrate, and at least a non-carrier dopant is added to the silicon single crystal substrate and the silicon epitaxial layer.
  • a first layer including a second layer including a non-carrier dopant is formed.
  • the first layer containing at least the non-carrier dopant and the second layer containing the non-carrier dopant are formed on the silicon single crystal substrate and the silicon epitaxial layer
  • heat treatment such as an epitaxial growth step or a subsequent device step is performed.
  • Oxygen contained in the silicon single crystal substrate flows into the first layer containing the non-carrier dopant, and the distortion of the first layer containing the non-carrier dopant is relaxed. Almost no oxygen flows into the second layer containing the non-carrier dopant formed in (1).
  • the strain of the second layer containing the non-carrier dopant is maintained, and as a result, the gettering ability of the impurity metal by the second layer containing the non-carrier dopant is maintained in a high state.
  • an epitaxial silicon wafer having high gettering ability can be obtained even if the integrated circuit substrate is thinned.
  • 1A to 1E are sectional views of a wafer showing a method of manufacturing an epitaxial silicon wafer according to the first embodiment.
  • the silicon single crystal grown by the CZ method is first subjected to processing such as slicing, grinding, etching, mirror polishing, and the like to obtain the silicon single crystal substrate 1.
  • the diameter and thickness of the silicon single crystal substrate 1 are not particularly limited, but the initial interstitial oxygen concentration is limited to 2.7 ⁇ 10 18 atoms / cc (ASTM F-121, 1979) or less from the solid solubility.
  • the silicon single crystal substrate 1 is set in an ion implantation apparatus, and carbon ions are ion-implanted into one surface (upper surface in FIG. 1) of the silicon single crystal substrate 1 as shown in FIG. 1A, as shown in FIG. 1B.
  • a first layer 2 containing a non-carrier dopant is formed near the surface of the silicon single crystal substrate 1.
  • Carbon ions can be implanted under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2.0 ⁇ m.
  • ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used.
  • the first layer 2 including the non-carrier dopant of this example has a function of capturing oxygen existing in the silicon single crystal substrate 1, it is more preferable to use a dopant such as carbon that easily binds to the oxygen. preferable.
  • the depth of the first layer 2 containing the non-carrier dopant is not particularly limited, but in consideration of the function of capturing oxygen present in the silicon single crystal substrate 1, it is formed as close to the surface of the silicon single crystal substrate 1 as possible. More preferably.
  • the silicon single crystal substrate 1 on which the first layer 2 containing the non-carrier dopant is formed is set in a vapor phase growth apparatus, and the silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 as shown in FIG. 1C. Form.
  • a monosilane gas or a hydrogen-diluted chlorosilane-based gas added with a diborane (P-type) or phosphine or arsine (N-type) dopant source gas is used.
  • a silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 by a thermal CVD reaction. The thickness of the silicon epitaxial layer 3 is appropriately selected according to the target device.
  • the silicon single crystal substrate 1 on which the silicon epitaxial layer 3 is formed is set in an ion implantation apparatus, and as shown in FIG. 1D, carbon ions are ion-implanted into the surface of the silicon epitaxial layer 3 (upper surface in the figure).
  • a second layer 4 containing a non-carrier dopant is formed in the silicon epitaxial layer 3.
  • This carbon ion implantation can be performed under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2 ⁇ m.
  • ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe and the like can also be used.
  • the second layer 4 containing a non-carrier dopant in this example is responsible for the function of trapping metal impurities in the device process. It is more preferable to use a dopant that easily binds to impurities.
  • the depth of the second layer 4 containing the non-carrier dopant is not particularly limited, but in consideration of the metal impurity trapping function, the second layer 4 is formed at a position deeper than the device active region and in the vicinity of the device active region. Is more preferable.
  • the oxygen present in the silicon single crystal substrate 1 tends to diffuse outward by the heat treatment in the vapor phase growth process and the heat treatment in the subsequent device process, but as shown by arrows in FIG. 1E, Oxygen present on the back side of the first layer 2 containing the non-carrier dopant is attracted to the strain generated by the first layer 2 containing the non-carrier dopant and is bonded to carbon.
  • the second layer 4 containing the non-carrier dopant formed in the silicon epitaxial layer 3 is very small. Since only a small amount of oxygen is captured (oxygen present in the region on the surface side of the silicon single crystal substrate 1 from the first layer 2 containing the non-carrier dopant), the non-carrier dopant is It is possible to suppress a decrease in the metal impurity capturing function of the second layer 4 that is included.
  • the initial oxygen concentration of the silicon single crystal substrate 1 is high, oxygen can be captured by the first layer 2 containing the non-carrier dopant, and the second layer 4 containing the non-carrier dopant exhibits the gettering function. Therefore, a wafer having a high gettering ability can be obtained without using a silicon single crystal having a low initial oxygen concentration.
  • the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant can be formed even if the wafer itself is thinned, it is applied to a device wafer such as MCP. be able to.
  • Second Embodiment are cross-sectional views of a wafer showing a method of manufacturing an epitaxial silicon wafer according to the second embodiment.
  • a first layer 2 containing a non-carrier dopant and a second layer 4 containing a non-carrier dopant are formed on the silicon epitaxial layer 3.
  • the silicon single crystal grown by the CZ method is subjected to processing such as slicing, grinding, etching, mirror polishing, etc., and the silicon single crystal substrate 1 is obtained.
  • the diameter and thickness of the silicon single crystal substrate 1 are not particularly limited, but the initial interstitial oxygen concentration is limited to 2.7 ⁇ 10 18 atoms / cc (ASTM F-121, 1979) or less from the solid solubility. This is the same as in the first embodiment.
  • this silicon single crystal substrate 1 is set in a vapor phase growth apparatus, and a silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 as shown in FIG. 2B.
  • diborane (P-type) or phosphine or arsine (N-type) is added to a monosilane gas or a hydrogen-diluted chlorosilane-based gas, as in the first embodiment.
  • a material to which a dopant source gas is added can be used.
  • a silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 by a thermal CVD reaction. The thickness of the silicon epitaxial layer 3 is appropriately selected according to the target device.
  • the silicon single crystal substrate 1 on which the silicon epitaxial layer 3 is formed is set in an ion implantation apparatus, and as shown in FIG. 2C, carbon ions are ion-implanted into the surface of the silicon epitaxial layer 3 (upper surface in the figure).
  • a first layer 2 containing a non-carrier dopant is formed in the silicon epitaxial layer 3.
  • This carbon ion implantation can be performed under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2 ⁇ m.
  • ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used.
  • the first layer 2 including the non-carrier dopant of this example has a function of capturing oxygen existing in the silicon single crystal substrate 1, it is more preferable to use a dopant such as carbon that easily binds to the oxygen. preferable.
  • the depth of the first layer 2 containing the non-carrier dopant is not particularly limited, but in consideration of the function of capturing oxygen present in the silicon single crystal substrate 1, it is formed as close to the surface of the silicon single crystal substrate 1 as possible. More preferably.
  • carbon ions are ion-implanted into the surface (upper surface in FIG. 2) of the silicon epitaxial layer 3 on which the first layer 2 containing the non-carrier dopant is formed by an ion implantation apparatus.
  • the second layer 4 containing the non-carrier dopant is formed on the surface side of the first layer 2 containing the non-carrier dopant of the silicon epitaxial layer 3.
  • This carbon ion implantation can be performed under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2 ⁇ m.
  • ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used.
  • the second layer 4 containing a non-carrier dopant in this example is responsible for the function of trapping metal impurities in the device process. It is more preferable to use a dopant that easily binds to impurities.
  • the depth of the second layer 4 containing the non-carrier dopant is not particularly limited, but in consideration of the metal impurity trapping function, the second layer 4 is formed at a position deeper than the device active region and in the vicinity of the device active region. Is more preferable.
  • a wafer is obtained in which the first layer 2 containing a non-carrier dopant is formed at a deep position of the silicon epitaxial layer 3 and the second layer 4 containing a non-carrier dopant is formed at a shallow position. .
  • the oxygen present in the silicon single crystal substrate 1 tends to diffuse outward by the heat treatment in the subsequent device process, but as shown by the arrow in FIG. 2F, the oxygen present in the silicon single crystal substrate 1 Is attracted to the strain generated by the first layer 2 containing a non-carrier dopant and bonds to carbon.
  • the second layer 4 containing the non-carrier dopant formed in a shallow position of the silicon epitaxial layer 3. In this case, almost no oxygen is trapped (the silicon epitaxial layer does not contain oxygen), so that the metal impurity trapping function of the second layer 4 containing the non-carrier dopant can be maintained.
  • the initial oxygen concentration of the silicon single crystal substrate 1 is high, oxygen can be captured by the first layer 2 containing the non-carrier dopant, and the second layer 4 containing the non-carrier dopant exhibits the gettering function. Therefore, a wafer having a high gettering ability can be obtained without using a silicon single crystal having a low initial oxygen concentration.
  • the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant can be formed even if the wafer itself is thinned, it is applied to a device wafer such as MCP. be able to.
  • 3A to 3E are cross-sectional views of a wafer showing a method of manufacturing an epitaxial silicon wafer according to a third embodiment.
  • a first layer 2 containing a non-carrier dopant and a second layer 4 containing a non-carrier dopant are formed on a silicon single crystal substrate 1.
  • a silicon single crystal grown by the CZ method is subjected to processing such as slicing, grinding, etching, mirror polishing, and the like to obtain a silicon single crystal substrate 1.
  • the diameter and thickness of the silicon single crystal substrate 1 are not particularly limited, but the initial interstitial oxygen concentration is limited to 2.7 ⁇ 10 18 atoms / cc (ASTM F-121, 1979) or less from the solid solubility. This is the same as in the first embodiment.
  • the silicon single crystal substrate 1 is set in an ion implantation apparatus, and carbon ions are ion-implanted into one surface (upper surface in FIG. 3) of the silicon single crystal substrate 1 as shown in FIG. First, a first layer 2 containing a non-carrier dopant is formed near the surface of the silicon single crystal substrate 1.
  • Carbon ions can be implanted under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2000 ⁇ m.
  • ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used.
  • the first layer 2 including the non-carrier dopant of this example has a function of capturing oxygen existing in the silicon single crystal substrate 1, it is more preferable to use a dopant such as carbon that easily binds to the oxygen. preferable.
  • the depth of the first layer 2 containing the non-carrier dopant is not particularly limited, but in consideration of the function of capturing oxygen present in the silicon single crystal substrate 1, it is formed as close to the surface of the silicon single crystal substrate 1 as possible. More preferably.
  • carbon ions are ion-implanted into the surface of the silicon single crystal substrate 1 on which the first layer 2 containing the non-carrier dopant is formed by an ion implantation apparatus, as shown in FIG. 3D.
  • the second layer 4 containing the non-carrier dopant is formed on the surface side of the first layer 2 containing the non-carrier dopant.
  • This carbon ion implantation can be performed under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2 ⁇ m.
  • ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used.
  • the second layer 4 containing a non-carrier dopant in this example is responsible for the function of trapping metal impurities in the device process. It is more preferable to use a dopant that easily binds to impurities.
  • the depth of the second layer 4 containing the non-carrier dopant is not particularly limited, but considering the metal impurity trapping function, the depth is deeper than the device active region and in the vicinity of the device active region, that is, silicon single layer. More preferably, it is formed near the surface of the crystal substrate 1.
  • the silicon single crystal substrate 1 on which the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant are formed is set in a vapor phase growth apparatus, and silicon as shown in FIG. 3E. Silicon epitaxial layer 3 is formed on the surface of single crystal substrate 1.
  • diborane (P-type) or phosphine or arsine (N-type) is added to a monosilane gas or a hydrogen-diluted chlorosilane-based gas, as in the first embodiment.
  • a material to which a dopant source gas is added can be used.
  • a silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 by a thermal CVD reaction. The thickness of the silicon epitaxial layer 3 is appropriately selected according to the target device.
  • oxygen present in the silicon single crystal substrate 1 tends to diffuse outward by the heat treatment in the vapor phase growth process and the heat treatment in the subsequent device process, but as shown by arrows in FIG. Oxygen present on the back side of the first layer 2 containing the non-carrier dopant is attracted to the strain generated by the first layer 2 containing the non-carrier dopant and is bonded to carbon.
  • the distortion of the first layer 2 containing the non-carrier dopant is relaxed and the function of capturing the metal impurity is lowered, the first layer 2 containing the non-carrier dopant formed on the silicon epitaxial layer 3 side of the silicon single crystal substrate 1 is reduced. Only a small amount of oxygen is trapped in the second layer 4 (oxygen present in the region on the surface side of the silicon single crystal substrate 1 from the layer 2 containing the first non-carrier dopant is trapped). Therefore, it is possible to suppress a decrease in the function of trapping metal impurities in the second layer 4 containing the non-carrier dopant.
  • the initial oxygen concentration of the silicon single crystal substrate 1 is high, oxygen can be captured by the first layer 2 containing the non-carrier dopant, and the second layer 4 containing the non-carrier dopant exhibits the gettering function. Therefore, a wafer having a high gettering ability can be obtained without using a silicon single crystal having a low initial oxygen concentration.
  • the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant can be formed even if the wafer itself is thinned, it is applied to a device wafer such as MCP. be able to.
  • ⁇ 4th Embodiment are sectional views of a wafer showing a method for manufacturing an epitaxial silicon wafer according to the fourth embodiment.
  • a first layer 2 containing a non-carrier dopant and a second layer 4 containing a non-carrier dopant are formed on a silicon epitaxial layer 3, and the structure is the same as in the second embodiment.
  • the first and second layers 2 and 4 containing a non-carrier dopant are formed by vapor deposition instead of ion implantation.
  • the silicon single crystal grown by the CZ method is subjected to processing such as slicing, grinding, etching, mirror polishing, and the like to obtain the silicon single crystal substrate 1.
  • the diameter and thickness of the silicon single crystal substrate 1 are not particularly limited, but the initial interstitial oxygen concentration is limited to 2.7 ⁇ 10 18 atoms / cc (ASTM F-121, 1979) or less from the solid solubility. This is the same as in the second embodiment.
  • this silicon single crystal substrate 1 is set in a vapor phase growth apparatus, and a silicon epitaxial layer 3a is formed on the surface of the silicon single crystal substrate 1 as shown in FIG. 4B.
  • diborane (P-type) or phosphine or arsine (N-type) is added to monosilane gas or hydrogen-diluted chlorosilane-based gas, as in the second embodiment.
  • a material to which a dopant source gas is added can be used.
  • a silicon epitaxial layer 3a is formed on the surface of the silicon single crystal substrate 1 by a thermal CVD reaction.
  • reaction gas of the vapor phase growth apparatus is switched, carbon as a non-carrier dopant is contained in the reaction gas, and vapor phase growth is performed, whereby non-carriers are formed on the surface of the silicon epitaxial layer 3a as shown in FIG. 4C.
  • a first layer 2 containing a conductive dopant is formed.
  • the reaction gas of the vapor phase growth apparatus is switched to the reaction gas in which the silicon epitaxial layer 3a is grown, and the silicon epitaxial layer 3b is formed on the surface of the first layer 2 containing the non-carrier dopant as shown in FIG. 4D. It is formed by vapor phase growth.
  • reaction gas of the vapor phase growth apparatus is switched, carbon as a non-carrier dopant is contained in the reaction gas, and vapor phase growth is performed, whereby non-carrier is formed on the surface of the silicon epitaxial layer 3b as shown in FIG. 4E.
  • a second layer 4 containing a conductive dopant is formed.
  • the reaction gas of the vapor phase growth apparatus is switched to the reaction gas in which the silicon epitaxial layers 3a and 3b are grown, and a silicon epitaxial layer is formed on the surface of the second layer 4 containing a non-carrier dopant as shown in FIG. 4F. 3c is formed by vapor phase growth.
  • the total thickness of the silicon epitaxial layers 3a, 3b, 3c, the first layer 2 containing a non-carrier dopant, and the second layer 4 containing a non-carrier dopant is appropriately selected according to the target device. .
  • the first layer 2 containing the non-carrier dopant is formed in the deep position of the silicon epitaxial layer 3, and the second layer containing the non-carrier dopant in the shallow position.
  • a wafer having 4 formed thereon is obtained.
  • oxygen existing in the silicon single crystal substrate 1 tends to diffuse outward by the heat treatment in the subsequent device process.
  • oxygen present in the silicon single crystal substrate 1 Is attracted to the strain generated by the first layer 2 containing a non-carrier dopant and bonds to carbon.
  • the second layer 4 containing the non-carrier dopant formed at a shallow position of the silicon epitaxial layer 3. Almost no oxygen is trapped (the silicon epitaxial layers 3a, 3b, 3c do not contain oxygen), so that the function of trapping metal impurities of the second layer 4 containing the non-carrier dopant can be maintained. .
  • the initial oxygen concentration of the silicon single crystal substrate 1 is high, oxygen can be captured by the first layer 2 containing the non-carrier dopant, and the second layer 4 containing the non-carrier dopant exhibits the gettering function. Therefore, a wafer having a high gettering ability can be obtained without using a silicon single crystal having a low initial oxygen concentration.
  • the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant can be formed even if the wafer itself is thinned, it is applied to a device wafer such as MCP. be able to.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Chemical Vapour Deposition (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

Disclosed is an epitaxial silicon wafer.  Also disclosed is a method for producing the epitaxial silicon wafer.  The epitaxial silicon wafer is characterized by comprising a silicon monocrystal base plate (1) and a silicon epitaxial layer (3) arranged on the main surface of the base plate (1), and is also characterized by having at least a first layer (2) containing a non-carrier dopant and a second layer (4) containing a non-carrier dopant formed on the silicon monocrystal base plate and the silicon epitaxial layer.

Description

エピタキシャルシリコンウェーハ及びその製造方法Epitaxial silicon wafer and manufacturing method thereof
　本発明は、エピタキシャルシリコンウェーハ及びその製造方法に関するものである。 The present invention relates to an epitaxial silicon wafer and a manufacturing method thereof.
　高集積化デバイスにおいて、デバイス活性領域に結晶欠陥あるいはドーパント以外の金属不純物が含まれていると、リーク電流の増大などのデバイスの電気的特性の劣化を招く。従来、高集積化シリコン半導体デバイスは、ＣＺ法で育成されたＣＺ－Ｓｉ基板が用いられてきたが、これらのＣＺ－Ｓｉ基板には過飽和の格子間酸素が約１０１８ａｔｏｍｓ／ｃｍ３のオーダーで含まれており、デバイス製造プロセスにおいて酸素析出物や転位、積層欠陥などの結晶欠陥が誘起されることは良く知られている。 In a highly integrated device, if a metal impurity other than crystal defects or dopants is contained in the device active region, the electrical characteristics of the device such as an increase in leakage current are deteriorated. Conventionally, CZ-Si substrates grown by the CZ method have been used for highly integrated silicon semiconductor devices. However, supersaturated interstitial oxygen is in the order of about 10 18 atoms / cm 3 for these CZ-Si substrates. It is well known that crystal defects such as oxygen precipitates, dislocations and stacking faults are induced in the device manufacturing process.
　従来、ＬＯＣＯＳ(Local Oxidation of Silicon)形成やＷＥＬＬ拡散層形成のために１１００～１２００℃の高温で数時間の熱処理が行われていたため、基板表面近傍では格子間酸素の外方拡散によって表面近傍数１０μｍには結晶欠陥のないいわゆるＤＺ(Denuded Zone)層が自然に形成され、ウェーハ表面のデバイス活性領域での結晶欠陥の発生が自然に抑制されていた。 Conventionally, heat treatment has been performed for several hours at a high temperature of 1100 to 1200 ° C. for forming LOCOS (Local Oxidation of Silicon) or WELL diffusion layer. A so-called DZ (Denuded Zone) layer having no crystal defects was naturally formed at 10 μm, and generation of crystal defects in the device active region on the wafer surface was naturally suppressed.
　しかし、半導体デバイスの微細化に伴い、ＷＥＬＬ形成に高エネルギーイオン注入が用いられ、デバイスプロセスが１０００℃以下の低温で行われるようになると、上記の酸素外方拡散が充分に起こらず表面近傍でのＤＺ層の形成が困難となってきた。このためにＳｉ基板の低酸素化が行われてきたが、結晶欠陥の発生を完全に抑制することは困難であった。 However, with the miniaturization of semiconductor devices, high energy ion implantation is used for WELL formation, and when the device process is performed at a low temperature of 1000 ° C. or less, the above-described oxygen out-diffusion does not occur sufficiently and near the surface. It has become difficult to form a DZ layer. For this reason, the oxygen reduction of the Si substrate has been performed, but it has been difficult to completely suppress the generation of crystal defects.
　このようなことから、結晶欠陥をほぼ完全に含まないエピタキシャル層をＣＺ－Ｓｉ基板上に成長させたエピタキシャルシリコンウェーハが、高集積化デバイスに多用されている。 For this reason, an epitaxial silicon wafer obtained by growing an epitaxial layer almost completely free of crystal defects on a CZ-Si substrate is often used for highly integrated devices.
　ところで、結晶の完全性が高いエピタキシャルウェーハを用いても、その後のデバイス工程におけるエピタキシャル膜の金属不純物汚染はデバイスの特性を悪化させる。従って、金属不純物をデバイス活性領域から離れた場所（シンク）に捕獲させる、いわゆるゲッタリング技術が必要となる。 By the way, even if an epitaxial wafer having high crystal integrity is used, the metal impurity contamination of the epitaxial film in the subsequent device process deteriorates the device characteristics. Therefore, a so-called gettering technique for capturing metal impurities at a place (sink) away from the device active region is required.
　ゲッタリング技術としては、デバイスプロセスの熱処理中に自然に誘起される酸素起因の結晶欠陥をシンクとするイントリンシックゲッタリング（ＩＧ）と、サンドブラスト、Ｓｉ３Ｎ４膜あるいはＰｏｌｙ－Ｓｉ膜の成長などによる裏面歪付けに代表されるイクストリンシックゲッタリング（ＥＧ）とがある。 Gettering technologies include intrinsic gettering (IG) using crystal defects caused by oxygen naturally induced during heat treatment of device processes as a sink, and sand blasting, Si 3 N 4 film, or Poly-Si film growth. There is an extrinsic gettering (EG) typified by back surface distortion.
　しかしながら、高集積化デバイスが薄型化されると、Ｓｉ基板に分散して存在していたシンクの数が減少するためＩＧ効果が期待できないという問題がある。また、抗折強度維持のため研削後のダメージが除去されることになり、ＥＧ効果も期待できないという問題がある。 However, when the highly integrated device is thinned, there is a problem that the IG effect cannot be expected because the number of sinks that exist dispersedly on the Si substrate decreases. In addition, there is a problem that damage after grinding is removed to maintain the bending strength, and the EG effect cannot be expected.
　こうした高集積化デバイスの薄型化は、高画素カメラや音楽プレーヤー等が搭載された携帯電話などの小型モバイル機器に特に顕著である。大容量データを保存・高速処理する能力が求められているため、１パッケージあたりに複数タイプのメモリを搭載するＭＣＰ（マルチチップパッケージ）のニーズが高まっている。 Such thinning of highly integrated devices is particularly noticeable in small mobile devices such as mobile phones equipped with high pixel cameras and music players. Since there is a demand for the ability to store and process large amounts of data at high speed, there is an increasing need for MCPs (multi-chip packages) in which multiple types of memory are mounted per package.
　特許文献１や特許文献２には、Ｓｉ基板に非キャリア性ドーパントを含む層を含むエピタキシャルウェーハが提案されている。 Patent Document 1 and Patent Document 2 propose an epitaxial wafer including a layer containing a non-carrier dopant on a Si substrate.
特開２００６－２１６９３４号公報JP 2006-216934 A 特開２００７－３６２５０号公報JP 2007-36250 A
　しかしながら、上記特許文献１及び２に記載されたウェーハでは、その後のエピタキシャル成長を含む熱プロセスの際に、非キャリア性ドーパントを含む層及びその周辺の歪により、Ｓｉ基板中の酸素が非キャリア性ドーパントを含む層に引き寄せられる。 However, in the wafers described in Patent Documents 1 and 2, oxygen in the Si substrate is converted into a non-carrier dopant due to strain in the layer including the non-carrier dopant and its surrounding strain during a thermal process including subsequent epitaxial growth. Drawn to the layer containing.
　したがって、金属不純物ゲッタリングのために導入した非キャリア性ドーパントを含む層による歪が拡散してきた酸素により緩和されてしまい、金属不純物をゲッタリングする能力が低減してしまうという問題があった。 Therefore, there is a problem that strain due to the layer containing the non-carrier dopant introduced for metal impurity gettering is relaxed by the diffused oxygen, and the ability to getter metal impurities is reduced.
　本発明が解決しようとする課題は、集積回路基板が薄型化しても高いゲッタリング能力を有するエピタキシャルシリコンウェーハを提供することである。 The problem to be solved by the present invention is to provide an epitaxial silicon wafer having high gettering ability even if the integrated circuit substrate is thinned.
　本発明のエピタキシャルシリコンウェーハ及びその製造方法は、シリコン単結晶基板の主面にシリコンエピタキシャル層を有するエピタキシャルシリコンウェーハであって、前記シリコン単結晶基板及び前記シリコンエピタキシャル層に、少なくとも非キャリア性ドーパントを含む第１の層と非キャリア性ドーパントを含む第２の層が形成されていることを特徴とする。 An epitaxial silicon wafer and a manufacturing method thereof according to the present invention are epitaxial silicon wafers having a silicon epitaxial layer on a main surface of a silicon single crystal substrate, and at least a non-carrier dopant is added to the silicon single crystal substrate and the silicon epitaxial layer. A first layer including a second layer including a non-carrier dopant is formed.
　このようにシリコン単結晶基板及びシリコンエピタキシャル層に、少なくとも非キャリア性ドーパントを含む第１の層と非キャリア性ドーパントを含む第２の層を形成すると、エピタキシャル成長工程やその後のデバイス工程などの熱処理により非キャリア性ドーパントを含む第１の層にシリコン単結晶基板に含まれる酸素が流入し、当該非キャリア性ドーパントを含む第１の層の歪が緩和されていくが、それよりもウェーハの表面側に形成された非キャリア性ドーパントを含む第２の層へは酸素の流入は殆ど生じない。 As described above, when the first layer containing at least the non-carrier dopant and the second layer containing the non-carrier dopant are formed on the silicon single crystal substrate and the silicon epitaxial layer, heat treatment such as an epitaxial growth step or a subsequent device step is performed. Oxygen contained in the silicon single crystal substrate flows into the first layer containing the non-carrier dopant, and the distortion of the first layer containing the non-carrier dopant is relaxed. Almost no oxygen flows into the second layer containing the non-carrier dopant formed in (1).
　したがって、非キャリア性ドーパントを含む第２の層の歪は維持され、その結果、当該非キャリア性ドーパントを含む第２の層による不純物金属のゲッタリング能力は高い状態で維持される。 Therefore, the strain of the second layer containing the non-carrier dopant is maintained, and as a result, the gettering ability of the impurity metal by the second layer containing the non-carrier dopant is maintained in a high state.
　本発明によれば、集積回路基板が薄型化しても高いゲッタリング能力を有するエピタキシャルシリコンウェーハを得ることができる。 According to the present invention, an epitaxial silicon wafer having high gettering ability can be obtained even if the integrated circuit substrate is thinned.
発明の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on embodiment of invention. 発明の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on embodiment of invention. 発明の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on embodiment of invention. 発明の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on embodiment of invention. 発明の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on embodiment of invention. 発明の他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明の他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明の他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明の他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明の他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明の他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明のさらに他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明のさらに他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明のさらに他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明のさらに他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明のさらに他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明のさらに他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明のさらに他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明のさらに他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明のさらに他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明のさらに他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention. 発明のさらに他の実施形態に係る製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method which concerns on other embodiment of invention.
　以下、本発明の実施形態を図面に基づいて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
《第１実施形態》
　図１Ａ～図１Ｅは第１実施形態に係るエピタキシャルシリコンウェーハの製造方法を示すウェーハの断面図である。 << First Embodiment >>
1A to 1E are sectional views of a wafer showing a method of manufacturing an epitaxial silicon wafer according to the first embodiment.
　本例の製造方法では、まずＣＺ法により育成されたシリコン単結晶にスライス、研削、エッチング、鏡面研磨等の処理を施し、シリコン単結晶基板１を得る。シリコン単結晶基板１の直径や厚さは特に限定されないが、固溶度から初期格子間酸素濃度は２．７×１０１８ａｔｏｍｓ／ｃｃ（ＡＳＴＭ　Ｆ－１２１，１９７９）以下に限定される。 In the manufacturing method of this example, the silicon single crystal grown by the CZ method is first subjected to processing such as slicing, grinding, etching, mirror polishing, and the like to obtain the silicon single crystal substrate 1. The diameter and thickness of the silicon single crystal substrate 1 are not particularly limited, but the initial interstitial oxygen concentration is limited to 2.7 × 10 18 atoms / cc (ASTM F-121, 1979) or less from the solid solubility.
　次いで、上記シリコン単結晶基板１をイオン注入装置にセットし、図１Ａに示すようにシリコン単結晶基板１の一方の表面（同図の上面）に炭素イオンをイオン注入し、図１Ｂに示すようにシリコン単結晶基板１の表面近傍に非キャリア性ドーパントを含む第１の層２を形成する。 Next, the silicon single crystal substrate 1 is set in an ion implantation apparatus, and carbon ions are ion-implanted into one surface (upper surface in FIG. 1) of the silicon single crystal substrate 1 as shown in FIG. 1A, as shown in FIG. 1B. First, a first layer 2 containing a non-carrier dopant is formed near the surface of the silicon single crystal substrate 1.
　炭素イオンの注入は、加速エネルギが１～２０００ｋｅＶ、ピーク密度が１０１５～１０２２ａｔｏｍｓ／ｃｃ、表面からの深さが０．０１～２．０μｍの条件ですることができる。 Carbon ions can be implanted under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2.0 μm.
　また、イオン注入されるイオンは炭素以外にも非キャリア性を有するドーパントであればよく、Ｓｉ，Ｇｅ，Ｓｎ，Ｐｂ，Ｈｅ，Ｎｅ，Ａｒ，Ｋｒ，Ｘｅなども用いることができる。ただし、本例の非キャリア性ドーパントを含む第１の層２はシリコン単結晶基板１に存在する酸素を捕獲する機能を司ることから、当該酸素と結合し易い炭素などのドーパントを用いることがより好ましい。 In addition to carbon, ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used. However, since the first layer 2 including the non-carrier dopant of this example has a function of capturing oxygen existing in the silicon single crystal substrate 1, it is more preferable to use a dopant such as carbon that easily binds to the oxygen. preferable.
　また、非キャリア性ドーパントを含む第１の層２の深さは特に限定されないが、シリコン単結晶基板１に存在する酸素の捕獲機能を考慮すると、できる限りシリコン単結晶基板１の表面近傍に形成することがより好ましい。 Further, the depth of the first layer 2 containing the non-carrier dopant is not particularly limited, but in consideration of the function of capturing oxygen present in the silicon single crystal substrate 1, it is formed as close to the surface of the silicon single crystal substrate 1 as possible. More preferably.
　次いで、非キャリア性ドーパントを含む第１の層２が形成されたシリコン単結晶基板１を気相成長装置にセットし、図１Ｃに示すようにシリコン単結晶基板１の表面にシリコンエピタキシャル層３を形成する。 Next, the silicon single crystal substrate 1 on which the first layer 2 containing the non-carrier dopant is formed is set in a vapor phase growth apparatus, and the silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 as shown in FIG. 1C. Form.
　この気相成長反応の原料ガスとしては、目的とするデバイスに応じて、モノシランガスや水素希釈したクロロシラン系ガスにジボラン（Ｐ型）又はホスフィンやアルシン（Ｎ型）のドーパント原料ガスを添加したものを使用することができる。これにより、シリコン単結晶基板１の表面において熱ＣＶＤ反応によるシリコンエピタキシャル層３が形成される。なお、シリコンエピタキシャル層３の厚さは目的とするデバイスに応じて適宜選択される。 As a source gas for this vapor phase growth reaction, a monosilane gas or a hydrogen-diluted chlorosilane-based gas added with a diborane (P-type) or phosphine or arsine (N-type) dopant source gas is used. Can be used. Thereby, a silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 by a thermal CVD reaction. The thickness of the silicon epitaxial layer 3 is appropriately selected according to the target device.
　次いで、上記シリコンエピタキシャル層３が形成されたシリコン単結晶基板１をイオン注入装置にセットし、図１Ｄに示すようにシリコンエピタキシャル層３の表面（同図の上面）に炭素イオンをイオン注入し、図１Ｅに示すようにシリコンエピタキシャル層３に非キャリア性ドーパントを含む第２の層４を形成する。 Next, the silicon single crystal substrate 1 on which the silicon epitaxial layer 3 is formed is set in an ion implantation apparatus, and as shown in FIG. 1D, carbon ions are ion-implanted into the surface of the silicon epitaxial layer 3 (upper surface in the figure). As shown in FIG. 1E, a second layer 4 containing a non-carrier dopant is formed in the silicon epitaxial layer 3.
　この炭素イオンの注入は、加速エネルギが１～２０００ｋｅＶ、ピーク密度が１０１５～１０２２ａｔｏｍｓ／ｃｃ、表面からの深さが０．０１～２μｍの条件ですることができる。 This carbon ion implantation can be performed under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2 μm.
　また、イオン注入されるイオンは炭素以外にも非キャリア性を有するドーパントであればよく、Ｓｉ，Ｇｅ，Ｓｎ，Ｐｂ，Ｈｅ，Ｎｅ，Ａｒ，Ｋｒ，Ｘｅなども用いることができる。特に上述した非キャリア性ドーパントを含む第１の層２とは異なり、本例の非キャリア性ドーパントを含む第２の層４は、デバイスプロセスにおける金属不純物を捕獲する機能を司ることから、当該金属不純物と結合し易いドーパントを用いることがより好ましい。 In addition to carbon, ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe and the like can also be used. In particular, unlike the above-described first layer 2 containing a non-carrier dopant, the second layer 4 containing a non-carrier dopant in this example is responsible for the function of trapping metal impurities in the device process. It is more preferable to use a dopant that easily binds to impurities.
　また、非キャリア性ドーパントを含む第２の層４の深さは特に限定されないが、金属不純物の捕獲機能を考慮すると、デバイス活性領域より深い位置であって当該デバイス活性領域の近傍に形成することがより好ましい。 Further, the depth of the second layer 4 containing the non-carrier dopant is not particularly limited, but in consideration of the metal impurity trapping function, the second layer 4 is formed at a position deeper than the device active region and in the vicinity of the device active region. Is more preferable.
　以上の工程により、シリコン単結晶基板１に非キャリア性ドーパントを含む第１の層２が形成され、シリコンエピタキシャル層３に非キャリア性ドーパントを含む第２の層４が形成されたウェーハが得られる。 Through the above steps, a wafer in which the first layer 2 containing the non-carrier dopant is formed on the silicon single crystal substrate 1 and the second layer 4 containing the non-carrier dopant is formed on the silicon epitaxial layer 3 is obtained. .
　このウェーハによれば、上述した気相成長工程の熱処理やその後のデバイス工程の熱処理によって、シリコン単結晶基板１に存在する酸素は外方拡散しようとするが、図１Ｅに矢印で示すように、非キャリア性ドーパントを含む第１の層２よりも裏面側に存在する酸素は非キャリア性ドーパントを含む第１の層２により発生している歪に引き寄せられて炭素と結合する。 According to this wafer, the oxygen present in the silicon single crystal substrate 1 tends to diffuse outward by the heat treatment in the vapor phase growth process and the heat treatment in the subsequent device process, but as shown by arrows in FIG. 1E, Oxygen present on the back side of the first layer 2 containing the non-carrier dopant is attracted to the strain generated by the first layer 2 containing the non-carrier dopant and is bonded to carbon.
　これにより非キャリア性ドーパントを含む第１の層２の歪みは緩和され金属不純物の捕獲機能は低下するものの、シリコンエピタキシャル層３に形成された非キャリア性ドーパントを含む第２の層４にはごく少数の酸素が捕獲されるだけであるため（非キャリア性ドーパントを含む第１の層２よりシリコン単結晶基板１の表面側の領域に存在する酸素が捕獲される）、当該非キャリア性ドーパントを含む第２の層４の金属不純物の捕獲機能の低下を抑制することができる。 Thereby, although the distortion of the first layer 2 containing the non-carrier dopant is relaxed and the function of capturing the metal impurities is lowered, the second layer 4 containing the non-carrier dopant formed in the silicon epitaxial layer 3 is very small. Since only a small amount of oxygen is captured (oxygen present in the region on the surface side of the silicon single crystal substrate 1 from the first layer 2 containing the non-carrier dopant), the non-carrier dopant is It is possible to suppress a decrease in the metal impurity capturing function of the second layer 4 that is included.
　また、シリコン単結晶基板１の初期酸素濃度が高くても非キャリア性ドーパントを含む第１の層２により酸素を捕獲でき、非キャリア性ドーパントを含む第２の層４がゲッタリング機能を発揮するので、初期酸素濃度が低いシリコン単結晶を用いなくても高いゲッタリング能力を有するウェーハを得ることができる。 Further, even when the initial oxygen concentration of the silicon single crystal substrate 1 is high, oxygen can be captured by the first layer 2 containing the non-carrier dopant, and the second layer 4 containing the non-carrier dopant exhibits the gettering function. Therefore, a wafer having a high gettering ability can be obtained without using a silicon single crystal having a low initial oxygen concentration.
　特に、ウェーハ自体が薄型化しても非キャリア性ドーパントを含む第１の層２及び非キャリア性ドーパントを含む第２の層４は形成可能であることから、たとえばＭＣＰなどのデバイス用ウェーハに適用することができる。 In particular, since the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant can be formed even if the wafer itself is thinned, it is applied to a device wafer such as MCP. be able to.
《第２実施形態》
　図２Ａ～図２Ｆは第２実施形態に係るエピタキシャルシリコンウェーハの製造方法を示すウェーハの断面図である。本例はシリコンエピタキシャル層３に非キャリア性ドーパントを含む第１の層２と非キャリア性ドーパントを含む第２の層４を形成したものである。 << Second Embodiment >>
2A to 2F are cross-sectional views of a wafer showing a method of manufacturing an epitaxial silicon wafer according to the second embodiment. In this example, a first layer 2 containing a non-carrier dopant and a second layer 4 containing a non-carrier dopant are formed on the silicon epitaxial layer 3.
　本例の製造方法では、図２Ａに示すように、ＣＺ法により育成されたシリコン単結晶にスライス、研削、エッチング、鏡面研磨等の処理を施し、シリコン単結晶基板１を得る。シリコン単結晶基板１の直径や厚さは特に限定されないが、固溶度から初期格子間酸素濃度は２．７×１０１８ａｔｏｍｓ／ｃｃ（ＡＳＴＭ　Ｆ－１２１，１９７９）以下に限定される。これについては上記第１実施形態と同様である。 In the manufacturing method of this example, as shown in FIG. 2A, the silicon single crystal grown by the CZ method is subjected to processing such as slicing, grinding, etching, mirror polishing, etc., and the silicon single crystal substrate 1 is obtained. The diameter and thickness of the silicon single crystal substrate 1 are not particularly limited, but the initial interstitial oxygen concentration is limited to 2.7 × 10 18 atoms / cc (ASTM F-121, 1979) or less from the solid solubility. This is the same as in the first embodiment.
　次いで、このシリコン単結晶基板１を気相成長装置にセットし、図２Ｂに示すようにシリコン単結晶基板１の表面にシリコンエピタキシャル層３を形成する。 Next, this silicon single crystal substrate 1 is set in a vapor phase growth apparatus, and a silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 as shown in FIG. 2B.
　この気相成長反応の原料ガスとしては、上記第１実施形態と同様に、目的とするデバイスに応じて、モノシランガスや水素希釈したクロロシラン系ガスにジボラン（Ｐ型）又はホスフィンやアルシン（Ｎ型）のドーパント原料ガスを添加したものを使用することができる。これにより、シリコン単結晶基板１の表面において熱ＣＶＤ反応によるシリコンエピタキシャル層３が形成される。なお、シリコンエピタキシャル層３の厚さは目的とするデバイスに応じて適宜選択される。 As a raw material gas for this vapor phase growth reaction, diborane (P-type) or phosphine or arsine (N-type) is added to a monosilane gas or a hydrogen-diluted chlorosilane-based gas, as in the first embodiment. A material to which a dopant source gas is added can be used. Thereby, a silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 by a thermal CVD reaction. The thickness of the silicon epitaxial layer 3 is appropriately selected according to the target device.
　次いで、上記シリコンエピタキシャル層３が形成されたシリコン単結晶基板１をイオン注入装置にセットし、図２Ｃに示すようにシリコンエピタキシャル層３の表面（同図の上面）に炭素イオンをイオン注入し、図２Ｄに示すようにシリコンエピタキシャル層３に非キャリア性ドーパントを含む第１の層２を形成する。 Next, the silicon single crystal substrate 1 on which the silicon epitaxial layer 3 is formed is set in an ion implantation apparatus, and as shown in FIG. 2C, carbon ions are ion-implanted into the surface of the silicon epitaxial layer 3 (upper surface in the figure). As shown in FIG. 2D, a first layer 2 containing a non-carrier dopant is formed in the silicon epitaxial layer 3.
　この炭素イオンの注入は、加速エネルギが１～２０００ｋｅＶ、ピーク密度が１０１５～１０２２ａｔｏｍｓ／ｃｃ、表面からの深さが０．０１～２μｍの条件ですることができる。 This carbon ion implantation can be performed under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2 μm.
　また、イオン注入されるイオンは炭素以外にも非キャリア性を有するドーパントであればよく、Ｓｉ，Ｇｅ，Ｓｎ，Ｐｂ，Ｈｅ，Ｎｅ，Ａｒ，Ｋｒ，Ｘｅなども用いることができる。ただし、本例の非キャリア性ドーパントを含む第１の層２はシリコン単結晶基板１に存在する酸素を捕獲する機能を司ることから、当該酸素と結合し易い炭素などのドーパントを用いることがより好ましい。 In addition to carbon, ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used. However, since the first layer 2 including the non-carrier dopant of this example has a function of capturing oxygen existing in the silicon single crystal substrate 1, it is more preferable to use a dopant such as carbon that easily binds to the oxygen. preferable.
　また、非キャリア性ドーパントを含む第１の層２の深さは特に限定されないが、シリコン単結晶基板１に存在する酸素の捕獲機能を考慮すると、できる限りシリコン単結晶基板１の表面近傍に形成することがより好ましい。 Further, the depth of the first layer 2 containing the non-carrier dopant is not particularly limited, but in consideration of the function of capturing oxygen present in the silicon single crystal substrate 1, it is formed as close to the surface of the silicon single crystal substrate 1 as possible. More preferably.
　続いて、図２Ｅに示すように、イオン注入装置により、非キャリア性ドーパントを含む第１の層２が形成されたシリコンエピタキシャル層３の表面（同図の上面）に炭素イオンをイオン注入し、図２Ｆに示すようにシリコンエピタキシャル層３の非キャリア性ドーパントを含む第１の層２より表面側に非キャリア性ドーパントを含む第２の層４を形成する。 Subsequently, as shown in FIG. 2E, carbon ions are ion-implanted into the surface (upper surface in FIG. 2) of the silicon epitaxial layer 3 on which the first layer 2 containing the non-carrier dopant is formed by an ion implantation apparatus. As shown in FIG. 2F, the second layer 4 containing the non-carrier dopant is formed on the surface side of the first layer 2 containing the non-carrier dopant of the silicon epitaxial layer 3.
　この炭素イオンの注入は、加速エネルギが１～２０００ｋｅＶ、ピーク密度が１０１５～１０２２ａｔｏｍｓ／ｃｃ、表面からの深さが０．０１～２μｍの条件ですることができる。 This carbon ion implantation can be performed under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2 μm.
　また、イオン注入されるイオンは炭素以外にも非キャリア性を有するドーパントであればよく、Ｓｉ，Ｇｅ，Ｓｎ，Ｐｂ，Ｈｅ，Ｎｅ，Ａｒ，Ｋｒ，Ｘｅなども用いることができる。特に上述した非キャリア性ドーパントを含む第１の層２とは異なり、本例の非キャリア性ドーパントを含む第２の層４は、デバイスプロセスにおける金属不純物を捕獲する機能を司ることから、当該金属不純物と結合し易いドーパントを用いることがより好ましい。 In addition to carbon, ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used. In particular, unlike the above-described first layer 2 containing a non-carrier dopant, the second layer 4 containing a non-carrier dopant in this example is responsible for the function of trapping metal impurities in the device process. It is more preferable to use a dopant that easily binds to impurities.
　また、非キャリア性ドーパントを含む第２の層４の深さは特に限定されないが、金属不純物の捕獲機能を考慮すると、デバイス活性領域より深い位置であって当該デバイス活性領域の近傍に形成することがより好ましい。 Further, the depth of the second layer 4 containing the non-carrier dopant is not particularly limited, but in consideration of the metal impurity trapping function, the second layer 4 is formed at a position deeper than the device active region and in the vicinity of the device active region. Is more preferable.
　以上の工程により、シリコンエピタキシャル層３の深い位置に非キャリア性ドーパントを含む第１の層２が形成され、浅い位置に非キャリア性ドーパントを含む第２の層４が形成されたウェーハが得られる。 Through the above steps, a wafer is obtained in which the first layer 2 containing a non-carrier dopant is formed at a deep position of the silicon epitaxial layer 3 and the second layer 4 containing a non-carrier dopant is formed at a shallow position. .
　このウェーハによれば、その後のデバイス工程の熱処理によって、シリコン単結晶基板１に存在する酸素は外方拡散しようとするが、図２Ｆに矢印で示すように、シリコン単結晶基板１に存在する酸素は非キャリア性ドーパントを含む第１の層２により発生している歪に引き寄せられて炭素と結合する。 According to this wafer, the oxygen present in the silicon single crystal substrate 1 tends to diffuse outward by the heat treatment in the subsequent device process, but as shown by the arrow in FIG. 2F, the oxygen present in the silicon single crystal substrate 1 Is attracted to the strain generated by the first layer 2 containing a non-carrier dopant and bonds to carbon.
　これにより非キャリア性ドーパントを含む第１の層２の歪みは緩和され金属不純物の捕獲機能は低下するものの、シリコンエピタキシャル層３の浅い位置に形成された非キャリア性ドーパントを含む第２の層４には殆ど酸素が捕獲されないため（シリコンエピタキシャル層には酸素が含まれない）、当該非キャリア性ドーパントを含む第２の層４の金属不純物の捕獲機能を維持することができる。 Thereby, although the distortion of the first layer 2 containing the non-carrier dopant is relaxed and the function of capturing the metal impurity is lowered, the second layer 4 containing the non-carrier dopant formed in a shallow position of the silicon epitaxial layer 3. In this case, almost no oxygen is trapped (the silicon epitaxial layer does not contain oxygen), so that the metal impurity trapping function of the second layer 4 containing the non-carrier dopant can be maintained.
　また、シリコン単結晶基板１の初期酸素濃度が高くても非キャリア性ドーパントを含む第１の層２により酸素を捕獲でき、非キャリア性ドーパントを含む第２の層４がゲッタリング機能を発揮するので、初期酸素濃度が低いシリコン単結晶を用いなくても高いゲッタリング能力を有するウェーハを得ることができる。 Further, even when the initial oxygen concentration of the silicon single crystal substrate 1 is high, oxygen can be captured by the first layer 2 containing the non-carrier dopant, and the second layer 4 containing the non-carrier dopant exhibits the gettering function. Therefore, a wafer having a high gettering ability can be obtained without using a silicon single crystal having a low initial oxygen concentration.
　特に、ウェーハ自体が薄型化しても非キャリア性ドーパントを含む第１の層２及び非キャリア性ドーパントを含む第２の層４は形成可能であることから、たとえばＭＣＰなどのデバイス用ウェーハに適用することができる。 In particular, since the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant can be formed even if the wafer itself is thinned, it is applied to a device wafer such as MCP. be able to.
《第３実施形態》
　図３Ａ～図３Ｅは第３実施形態に係るエピタキシャルシリコンウェーハの製造方法を示すウェーハの断面図である。本例はシリコン単結晶基板１に非キャリア性ドーパントを含む第１の層２と非キャリア性ドーパントを含む第２の層４を形成したものである。 << Third Embodiment >>
3A to 3E are cross-sectional views of a wafer showing a method of manufacturing an epitaxial silicon wafer according to a third embodiment. In this example, a first layer 2 containing a non-carrier dopant and a second layer 4 containing a non-carrier dopant are formed on a silicon single crystal substrate 1.
　本例の製造方法では、図３Ａに示すように、ＣＺ法により育成されたシリコン単結晶にスライス、研削、エッチング、鏡面研磨等の処理を施し、シリコン単結晶基板１を得る。シリコン単結晶基板１の直径や厚さは特に限定されないが、固溶度から初期格子間酸素濃度は２．７×１０１８ａｔｏｍｓ／ｃｃ（ＡＳＴＭ　Ｆ－１２１，１９７９）以下に限定される。これについては上記第１実施形態と同様である。 In the manufacturing method of this example, as shown in FIG. 3A, a silicon single crystal grown by the CZ method is subjected to processing such as slicing, grinding, etching, mirror polishing, and the like to obtain a silicon single crystal substrate 1. The diameter and thickness of the silicon single crystal substrate 1 are not particularly limited, but the initial interstitial oxygen concentration is limited to 2.7 × 10 18 atoms / cc (ASTM F-121, 1979) or less from the solid solubility. This is the same as in the first embodiment.
　次いで、上記シリコン単結晶基板１をイオン注入装置にセットし、図３Ａに示すようにシリコン単結晶基板１の一方の表面（同図の上面）に炭素イオンをイオン注入し、図３Ｂに示すようにシリコン単結晶基板１の表面近傍に非キャリア性ドーパントを含む第１の層２を形成する。 Next, the silicon single crystal substrate 1 is set in an ion implantation apparatus, and carbon ions are ion-implanted into one surface (upper surface in FIG. 3) of the silicon single crystal substrate 1 as shown in FIG. First, a first layer 2 containing a non-carrier dopant is formed near the surface of the silicon single crystal substrate 1.
　炭素イオンの注入は、加速エネルギが１～２０００ｋｅＶ、ピーク密度が１０１５～１０２２ａｔｏｍｓ／ｃｃ、表面からの深さが０．０１～２０００μｍの条件ですることができる。 Carbon ions can be implanted under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2000 μm.
　また、イオン注入されるイオンは炭素以外にも非キャリア性を有するドーパントであればよく、Ｓｉ，Ｇｅ，Ｓｎ，Ｐｂ，Ｈｅ，Ｎｅ，Ａｒ，Ｋｒ，Ｘｅなども用いることができる。ただし、本例の非キャリア性ドーパントを含む第１の層２はシリコン単結晶基板１に存在する酸素を捕獲する機能を司ることから、当該酸素と結合し易い炭素などのドーパントを用いることがより好ましい。 In addition to carbon, ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used. However, since the first layer 2 including the non-carrier dopant of this example has a function of capturing oxygen existing in the silicon single crystal substrate 1, it is more preferable to use a dopant such as carbon that easily binds to the oxygen. preferable.
　また、非キャリア性ドーパントを含む第１の層２の深さは特に限定されないが、シリコン単結晶基板１に存在する酸素の捕獲機能を考慮すると、できる限りシリコン単結晶基板１の表面近傍に形成することがより好ましい。 Further, the depth of the first layer 2 containing the non-carrier dopant is not particularly limited, but in consideration of the function of capturing oxygen present in the silicon single crystal substrate 1, it is formed as close to the surface of the silicon single crystal substrate 1 as possible. More preferably.
　続いて、図３Ｃに示すように、イオン注入装置により、非キャリア性ドーパントを含む第１の層２が形成されたシリコン単結晶基板１の表面に炭素イオンをイオン注入し、図３Ｄに示すように非キャリア性ドーパントを含む第１の層２より表面側に非キャリア性ドーパントを含む第２の層４を形成する。 Subsequently, as shown in FIG. 3C, carbon ions are ion-implanted into the surface of the silicon single crystal substrate 1 on which the first layer 2 containing the non-carrier dopant is formed by an ion implantation apparatus, as shown in FIG. 3D. The second layer 4 containing the non-carrier dopant is formed on the surface side of the first layer 2 containing the non-carrier dopant.
　この炭素イオンの注入は、加速エネルギが１～２０００ｋｅＶ、ピーク密度が１０１５～１０２２ａｔｏｍｓ／ｃｃ、表面からの深さが０．０１～２μｍの条件ですることができる。 This carbon ion implantation can be performed under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2 μm.
　また、イオン注入されるイオンは炭素以外にも非キャリア性を有するドーパントであればよく、Ｓｉ，Ｇｅ，Ｓｎ，Ｐｂ，Ｈｅ，Ｎｅ，Ａｒ，Ｋｒ，Ｘｅなども用いることができる。特に上述した非キャリア性ドーパントを含む第１の層２とは異なり、本例の非キャリア性ドーパントを含む第２の層４は、デバイスプロセスにおける金属不純物を捕獲する機能を司ることから、当該金属不純物と結合し易いドーパントを用いることがより好ましい。 In addition to carbon, ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used. In particular, unlike the above-described first layer 2 containing a non-carrier dopant, the second layer 4 containing a non-carrier dopant in this example is responsible for the function of trapping metal impurities in the device process. It is more preferable to use a dopant that easily binds to impurities.
　また、非キャリア性ドーパントを含む第２の層４の深さは特に限定されないが、金属不純物の捕獲機能を考慮すると、デバイス活性領域より深い位置であって当該デバイス活性領域の近傍、すなわちシリコン単結晶基板１の表面近傍に形成することがより好ましい。 In addition, the depth of the second layer 4 containing the non-carrier dopant is not particularly limited, but considering the metal impurity trapping function, the depth is deeper than the device active region and in the vicinity of the device active region, that is, silicon single layer. More preferably, it is formed near the surface of the crystal substrate 1.
　次いで、非キャリア性ドーパントを含む第１の層２及び非キャリア性ドーパントを含む第２の層４が形成されたシリコン単結晶基板１を気相成長装置にセットし、図３Ｅに示すようにシリコン単結晶基板１の表面にシリコンエピタキシャル層３を形成する。 Next, the silicon single crystal substrate 1 on which the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant are formed is set in a vapor phase growth apparatus, and silicon as shown in FIG. 3E. Silicon epitaxial layer 3 is formed on the surface of single crystal substrate 1.
　この気相成長反応の原料ガスとしては、上記第１実施形態と同様に、目的とするデバイスに応じて、モノシランガスや水素希釈したクロロシラン系ガスにジボラン（Ｐ型）又はホスフィンやアルシン（Ｎ型）のドーパント原料ガスを添加したものを使用することができる。これにより、シリコン単結晶基板１の表面において熱ＣＶＤ反応によるシリコンエピタキシャル層３が形成される。なお、シリコンエピタキシャル層３の厚さは目的とするデバイスに応じて適宜選択される。 As a raw material gas for this vapor phase growth reaction, diborane (P-type) or phosphine or arsine (N-type) is added to a monosilane gas or a hydrogen-diluted chlorosilane-based gas, as in the first embodiment. A material to which a dopant source gas is added can be used. Thereby, a silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 by a thermal CVD reaction. The thickness of the silicon epitaxial layer 3 is appropriately selected according to the target device.
　以上の工程により、シリコン単結晶基板１に非キャリア性ドーパントを含む第１の層２と非キャリア性ドーパントを含む第２の層４が形成された、シリコンエピタキシャル層３を有するウェーハが得られる。 Through the above steps, a wafer having the silicon epitaxial layer 3 in which the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant are formed on the silicon single crystal substrate 1 is obtained.
　このウェーハによれば、上述した気相成長工程の熱処理やその後のデバイス工程の熱処理によって、シリコン単結晶基板１に存在する酸素は外方拡散しようとするが、図３Ｅに矢印で示すように、非キャリア性ドーパントを含む第１の層２よりも裏面側に存在する酸素は非キャリア性ドーパントを含む第１の層２により発生している歪に引き寄せられて炭素と結合する。 According to this wafer, oxygen present in the silicon single crystal substrate 1 tends to diffuse outward by the heat treatment in the vapor phase growth process and the heat treatment in the subsequent device process, but as shown by arrows in FIG. Oxygen present on the back side of the first layer 2 containing the non-carrier dopant is attracted to the strain generated by the first layer 2 containing the non-carrier dopant and is bonded to carbon.
　これにより非キャリア性ドーパントを含む第１の層２の歪みは緩和され金属不純物の捕獲機能は低下するものの、シリコン単結晶基板１のシリコンエピタキシャル層３側に形成された非キャリア性ドーパントを含む第２の層４にはごく少数の酸素が捕獲されるだけであるため（第１の非キャリア性ドーパントを含む層２よりシリコン単結晶基板１の表面側の領域に存在する酸素が捕獲される）、当該非キャリア性ドーパントを含む第２の層４の金属不純物の捕獲機能の低下を抑制することができる。 Thereby, although the distortion of the first layer 2 containing the non-carrier dopant is relaxed and the function of capturing the metal impurity is lowered, the first layer 2 containing the non-carrier dopant formed on the silicon epitaxial layer 3 side of the silicon single crystal substrate 1 is reduced. Only a small amount of oxygen is trapped in the second layer 4 (oxygen present in the region on the surface side of the silicon single crystal substrate 1 from the layer 2 containing the first non-carrier dopant is trapped). Therefore, it is possible to suppress a decrease in the function of trapping metal impurities in the second layer 4 containing the non-carrier dopant.
　また、シリコン単結晶基板１の初期酸素濃度が高くても非キャリア性ドーパントを含む第１の層２により酸素を捕獲でき、非キャリア性ドーパントを含む第２の層４がゲッタリング機能を発揮するので、初期酸素濃度が低いシリコン単結晶を用いなくても高いゲッタリング能力を有するウェーハを得ることができる。 Further, even when the initial oxygen concentration of the silicon single crystal substrate 1 is high, oxygen can be captured by the first layer 2 containing the non-carrier dopant, and the second layer 4 containing the non-carrier dopant exhibits the gettering function. Therefore, a wafer having a high gettering ability can be obtained without using a silicon single crystal having a low initial oxygen concentration.
　特に、ウェーハ自体が薄型化しても非キャリア性ドーパントを含む第１の層２及び非キャリア性ドーパントを含む第２の層４は形成可能であることから、たとえばＭＣＰなどのデバイス用ウェーハに適用することができる。 In particular, since the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant can be formed even if the wafer itself is thinned, it is applied to a device wafer such as MCP. be able to.
《第４実施形態》
　図４Ａ～図４Ｆは第４実施形態に係るエピタキシャルシリコンウェーハの製造方法を示すウェーハの断面図である。本例はシリコンエピタキシャル層３に非キャリア性ドーパントを含む第１の層２と非キャリア性ドーパントを含む第２の層４を形成したものであり、構造的には上記第２実施形態と同じであるが、非キャリア性ドーパントを含む第１及び第２の層２，４をイオン注入法に代えて気相成長法により形成したものである。 << 4th Embodiment >>
4A to 4F are sectional views of a wafer showing a method for manufacturing an epitaxial silicon wafer according to the fourth embodiment. In this example, a first layer 2 containing a non-carrier dopant and a second layer 4 containing a non-carrier dopant are formed on a silicon epitaxial layer 3, and the structure is the same as in the second embodiment. However, the first and second layers 2 and 4 containing a non-carrier dopant are formed by vapor deposition instead of ion implantation.
　本例の製造方法では、図４Ａに示すように、ＣＺ法により育成されたシリコン単結晶にスライス、研削、エッチング、鏡面研磨等の処理を施し、シリコン単結晶基板１を得る。シリコン単結晶基板１の直径や厚さは特に限定されないが、固溶度から初期格子間酸素濃度は２．７×１０１８ａｔｏｍｓ／ｃｃ（ＡＳＴＭ　Ｆ－１２１，１９７９）以下に限定される。これについては上記第２実施形態と同様である。 In the manufacturing method of this example, as shown in FIG. 4A, the silicon single crystal grown by the CZ method is subjected to processing such as slicing, grinding, etching, mirror polishing, and the like to obtain the silicon single crystal substrate 1. The diameter and thickness of the silicon single crystal substrate 1 are not particularly limited, but the initial interstitial oxygen concentration is limited to 2.7 × 10 18 atoms / cc (ASTM F-121, 1979) or less from the solid solubility. This is the same as in the second embodiment.
　次いで、このシリコン単結晶基板１を気相成長装置にセットし、図４Ｂに示すようにシリコン単結晶基板１の表面にシリコンエピタキシャル層３ａを形成する。 Next, this silicon single crystal substrate 1 is set in a vapor phase growth apparatus, and a silicon epitaxial layer 3a is formed on the surface of the silicon single crystal substrate 1 as shown in FIG. 4B.
　この気相成長反応の原料ガスとしては、上記第２実施形態と同様に、目的とするデバイスに応じて、モノシランガスや水素希釈したクロロシラン系ガスにジボラン（Ｐ型）又はホスフィンやアルシン（Ｎ型）のドーパント原料ガスを添加したものを使用することができる。これにより、シリコン単結晶基板１の表面において熱ＣＶＤ反応によるシリコンエピタキシャル層３ａが形成される。 As a raw material gas for this vapor phase growth reaction, diborane (P-type) or phosphine or arsine (N-type) is added to monosilane gas or hydrogen-diluted chlorosilane-based gas, as in the second embodiment. A material to which a dopant source gas is added can be used. Thereby, a silicon epitaxial layer 3a is formed on the surface of the silicon single crystal substrate 1 by a thermal CVD reaction.
　次いで、気相成長装置の反応ガスを切り替え、非キャリア性ドーパントである炭素を上記反応ガスに含有させ、気相成長を行うことにより、図４Ｃに示すようにシリコンエピタキシャル層３ａの表面に非キャリア性ドーパントを含む第１の層２を形成する。 Next, the reaction gas of the vapor phase growth apparatus is switched, carbon as a non-carrier dopant is contained in the reaction gas, and vapor phase growth is performed, whereby non-carriers are formed on the surface of the silicon epitaxial layer 3a as shown in FIG. 4C. A first layer 2 containing a conductive dopant is formed.
　次いで、気相成長装置の反応ガスを、上記シリコンエピタキシャル層３ａを成長させた反応ガスに切り替え、図４Ｄに示すように非キャリア性ドーパントを含む第１の層２の表面にシリコンエピタキシャル層３ｂを気相成長により形成する。 Next, the reaction gas of the vapor phase growth apparatus is switched to the reaction gas in which the silicon epitaxial layer 3a is grown, and the silicon epitaxial layer 3b is formed on the surface of the first layer 2 containing the non-carrier dopant as shown in FIG. 4D. It is formed by vapor phase growth.
　次いで、気相成長装置の反応ガスを切り替え、非キャリア性ドーパントである炭素を上記反応ガスに含有させ、気相成長を行うことにより、図４Ｅに示すようにシリコンエピタキシャル層３ｂの表面に非キャリア性ドーパントを含む第２の層４を形成する。 Next, the reaction gas of the vapor phase growth apparatus is switched, carbon as a non-carrier dopant is contained in the reaction gas, and vapor phase growth is performed, whereby non-carrier is formed on the surface of the silicon epitaxial layer 3b as shown in FIG. 4E. A second layer 4 containing a conductive dopant is formed.
　次いで、気相成長装置の反応ガスを、上記シリコンエピタキシャル層３ａ，３ｂを成長させた反応ガスに切り替え、図４Ｆに示すように非キャリア性ドーパントを含む第２の層４の表面にシリコンエピタキシャル層３ｃを気相成長により形成する。 Next, the reaction gas of the vapor phase growth apparatus is switched to the reaction gas in which the silicon epitaxial layers 3a and 3b are grown, and a silicon epitaxial layer is formed on the surface of the second layer 4 containing a non-carrier dopant as shown in FIG. 4F. 3c is formed by vapor phase growth.
　なお、シリコンエピタキシャル層３ａ，３ｂ，３ｃ及び非キャリア性ドーパントを含む第１の層２、非キャリア性ドーパントを含む第２の層４の総合厚さは目的とするデバイスに応じて適宜選択される。 The total thickness of the silicon epitaxial layers 3a, 3b, 3c, the first layer 2 containing a non-carrier dopant, and the second layer 4 containing a non-carrier dopant is appropriately selected according to the target device. .
　以上の工程により、上記第２実施形態と同様に、シリコンエピタキシャル層３の深い位置に非キャリア性ドーパントを含む第１の層２が形成され、浅い位置に非キャリア性ドーパントを含む第２の層４が形成されたウェーハが得られる。 Through the above steps, as in the second embodiment, the first layer 2 containing the non-carrier dopant is formed in the deep position of the silicon epitaxial layer 3, and the second layer containing the non-carrier dopant in the shallow position. A wafer having 4 formed thereon is obtained.
　このウェーハによれば、その後のデバイス工程の熱処理によって、シリコン単結晶基板１に存在する酸素は外方拡散しようとするが、図４Ｆに矢印で示すように、シリコン単結晶基板１に存在する酸素は非キャリア性ドーパントを含む第１の層２により発生している歪に引き寄せられて炭素と結合する。 According to this wafer, oxygen existing in the silicon single crystal substrate 1 tends to diffuse outward by the heat treatment in the subsequent device process. However, as shown by an arrow in FIG. 4F, oxygen present in the silicon single crystal substrate 1 Is attracted to the strain generated by the first layer 2 containing a non-carrier dopant and bonds to carbon.
　これにより非キャリア性ドーパントを含む第１の層２の歪みは緩和され金属不純物の捕獲機能は低下するものの、シリコンエピタキシャル層３の浅い位置に形成された非キャリア性ドーパントを含む第２の層４には殆ど酸素が捕獲されないため（シリコンエピタキシャル層３ａ，３ｂ，３ｃには酸素が含まれない）、当該非キャリア性ドーパントを含む第２の層４の金属不純物の捕獲機能を維持することができる。 Thereby, although the distortion of the first layer 2 containing the non-carrier dopant is relaxed and the metal impurity trapping function is lowered, the second layer 4 containing the non-carrier dopant formed at a shallow position of the silicon epitaxial layer 3. Almost no oxygen is trapped (the silicon epitaxial layers 3a, 3b, 3c do not contain oxygen), so that the function of trapping metal impurities of the second layer 4 containing the non-carrier dopant can be maintained. .
　また、シリコン単結晶基板１の初期酸素濃度が高くても非キャリア性ドーパントを含む第１の層２により酸素を捕獲でき、非キャリア性ドーパントを含む第２の層４がゲッタリング機能を発揮するので、初期酸素濃度が低いシリコン単結晶を用いなくても高いゲッタリング能力を有するウェーハを得ることができる。 Further, even when the initial oxygen concentration of the silicon single crystal substrate 1 is high, oxygen can be captured by the first layer 2 containing the non-carrier dopant, and the second layer 4 containing the non-carrier dopant exhibits the gettering function. Therefore, a wafer having a high gettering ability can be obtained without using a silicon single crystal having a low initial oxygen concentration.
　特に、ウェーハ自体が薄型化しても非キャリア性ドーパントを含む第１の層２及び非キャリア性ドーパントを含む第２の層４は形成可能であることから、たとえばＭＣＰなどのデバイス用ウェーハに適用することができる。 In particular, since the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant can be formed even if the wafer itself is thinned, it is applied to a device wafer such as MCP. be able to.
１…シリコン単結晶基板
２…非キャリア性ドーパントを含む第１の層
３…シリコンエピタキシャル層
４…非キャリア性ドーパントを含む第２の層 DESCRIPTION OF SYMBOLS 1 ... Silicon single crystal substrate 2 ... 1st layer 3 containing a non-carrier-type dopant 3 ... Silicon epitaxial layer 4 ... 2nd layer containing a non-carrier-type dopant

Claims (17)

  1. 　シリコン単結晶基板の主面にシリコンエピタキシャル層を有するエピタキシャルシリコンウェーハであって、
    　前記シリコン単結晶基板及び前記シリコンエピタキシャル層に、少なくとも非キャリア性ドーパントを含む第１の層と非キャリア性ドーパントを含む第２の層が形成されていることを特徴とするエピタキシャルシリコンウェーハ。     An epitaxial silicon wafer having a silicon epitaxial layer on the main surface of a silicon single crystal substrate,
    An epitaxial silicon wafer, wherein a first layer containing at least a non-carrier dopant and a second layer containing a non-carrier dopant are formed on the silicon single crystal substrate and the silicon epitaxial layer.
  2. 　請求項１に記載のエピタキシャルシリコンウェーハにおいて、
    　前記非キャリア性ドーパントを含む第１の層は前記シリコン単結晶基板に形成され、前記非キャリア性ドーパントを含む第２の層は前記シリコンエピタキシャル層に形成されていることを特徴とするエピタキシャルシリコンウェーハ。     The epitaxial silicon wafer according to claim 1,
    An epitaxial silicon wafer, wherein the first layer containing the non-carrier dopant is formed on the silicon single crystal substrate, and the second layer containing the non-carrier dopant is formed on the silicon epitaxial layer. .
  3. 　請求項１に記載のエピタキシャルシリコンウェーハにおいて、
    　前記非キャリア性ドーパントを含む第１の層及び前記非キャリア性ドーパントを含む第２の層は前記シリコン単結晶基板に形成されていることを特徴とするエピタキシャルシリコンウェーハ。     The epitaxial silicon wafer according to claim 1,
    The epitaxial silicon wafer, wherein the first layer containing the non-carrier dopant and the second layer containing the non-carrier dopant are formed on the silicon single crystal substrate.
  4. 　請求項１に記載のエピタキシャルシリコンウェーハにおいて、
    　前記非キャリア性ドーパントを含む第１の層及び前記非キャリア性ドーパントを含む第２の層は前記シリコンエピタキシャル層に形成されていることを特徴とするエピタキシャルシリコンウェーハ。     The epitaxial silicon wafer according to claim 1,
    The epitaxial silicon wafer, wherein the first layer containing the non-carrier dopant and the second layer containing the non-carrier dopant are formed in the silicon epitaxial layer.
  5. 　請求項１に記載のエピタキシャルシリコンウェーハにおいて、
    　前記シリコン単結晶基板の初期格子間酸素濃度が２．７×１０１８ａｔｏｍｓ／ｃｃ（ＡＳＴＭ　Ｆ－１２１，１９７９）以下であることを特徴とするエピタキシャルシリコンウェーハ。     The epitaxial silicon wafer according to claim 1,
    An epitaxial silicon wafer, wherein an initial interstitial oxygen concentration of the silicon single crystal substrate is 2.7 × 10 18 atoms / cc (ASTM F-121, 1979) or less.
  6. 　請求項１～５のいずれか一項に記載のエピタキシャルシリコンウェーハにおいて、
    　前記非キャリア性ドーパントを含む第１及び第２の層は、非キャリア性ドーパントをイオン注入することにより形成されることを特徴とするエピタキシャルシリコンウェーハ。     In the epitaxial silicon wafer according to any one of claims 1 to 5,
    The epitaxial silicon wafer according to claim 1, wherein the first and second layers containing the non-carrier dopant are formed by ion-implanting the non-carrier dopant.
  7. 　請求項６に記載のエピタキシャルシリコンウェーハにおいて、
    　前記非キャリア性ドーパントを含む第１及び第２の層は、炭素イオンをイオン注入することにより形成されることを特徴とするエピタキシャルシリコンウェーハ。     In the epitaxial silicon wafer according to claim 6,
    The epitaxial silicon wafer, wherein the first and second layers containing the non-carrier dopant are formed by ion implantation of carbon ions.
  8. 　請求項２に記載のエピタキシャルシリコンウェーハにおいて、
    　前記非キャリア性ドーパントを含む第２の層は、非キャリア性ドーパントを含有する反応ガスを用いたエピタキシャル成長により形成されることを特徴とするエピタキシャルシリコンウェーハ。     In the epitaxial silicon wafer according to claim 2,
    The second layer containing a non-carrier dopant is formed by epitaxial growth using a reaction gas containing a non-carrier dopant.
  9. 　請求項４に記載のエピタキシャルシリコンウェーハにおいて、
    　前記非キャリア性ドーパントを含む第１及び第２の層は、非キャリア性ドーパントを含有する反応ガスを用いたエピタキシャル成長により形成されることを特徴とするエピタキシャルシリコンウェーハ。     The epitaxial silicon wafer according to claim 4,
    The first and second layers containing the non-carrier dopant are formed by epitaxial growth using a reaction gas containing the non-carrier dopant.
  10. 　シリコン単結晶基板の主面にシリコンエピタキシャル層を有するエピタキシャルシリコンウェーハの製造方法であって、
    　前記シリコン単結晶基板に非キャリア性ドーパントを含む第１の層を形成する工程と、
    　前記シリコン単結晶基板の主面にシリコンエピタキシャル層を形成する工程と、
    　前記シリコンエピタキシャル層に非キャリア性ドーパントを含む第２の層を形成する工程と、を備えたことを特徴とするエピタキシャルシリコンウェーハの製造方法。     A method for producing an epitaxial silicon wafer having a silicon epitaxial layer on a main surface of a silicon single crystal substrate,
    Forming a first layer containing a non-carrier dopant on the silicon single crystal substrate;
    Forming a silicon epitaxial layer on the main surface of the silicon single crystal substrate;
    Forming a second layer containing a non-carrier dopant in the silicon epitaxial layer. A method for producing an epitaxial silicon wafer, comprising:
  11. 　シリコン単結晶基板の主面にシリコンエピタキシャル層を有するエピタキシャルシリコンウェーハの製造方法であって、
    　前記シリコン単結晶基板の主面にシリコンエピタキシャル層を形成する工程と、
    　前記シリコンエピタキシャル層に非キャリア性ドーパントを含む第１の層を形成する工程と、
    　前記シリコンエピタキシャル層に非キャリア性ドーパントを含む第２の層を形成する工程と、を備えたことを特徴とするエピタキシャルシリコンウェーハの製造方法。     A method for producing an epitaxial silicon wafer having a silicon epitaxial layer on a main surface of a silicon single crystal substrate,
    Forming a silicon epitaxial layer on the main surface of the silicon single crystal substrate;
    Forming a first layer containing a non-carrier dopant in the silicon epitaxial layer;
    Forming a second layer containing a non-carrier dopant in the silicon epitaxial layer. A method for producing an epitaxial silicon wafer, comprising:
  12. 　シリコン単結晶基板の主面にシリコンエピタキシャル層を有するエピタキシャルシリコンウェーハの製造方法であって、
    　前記シリコン単結晶基板に非キャリア性ドーパントを含む第１の層を形成する工程と、
    　前記シリコン単結晶基板に非キャリア性ドーパントを含む第２の層を形成する工程と、
    　前記シリコン単結晶基板の主面にシリコンエピタキシャル層を形成する工程と、を備えたことを特徴とするエピタキシャルシリコンウェーハの製造方法。     A method for producing an epitaxial silicon wafer having a silicon epitaxial layer on a main surface of a silicon single crystal substrate,
    Forming a first layer containing a non-carrier dopant on the silicon single crystal substrate;
    Forming a second layer containing a non-carrier dopant on the silicon single crystal substrate;
    And a step of forming a silicon epitaxial layer on a main surface of the silicon single crystal substrate.
  13. 　請求項１０に記載のエピタキシャルシリコンウェーハの製造方法において、
    　前記シリコン単結晶基板の初期格子間酸素濃度が２．７×１０１８ａｔｏｍｓ／ｃｃ（ＡＳＴＭ　Ｆ－１２１，１９７９）以下であることを特徴とするエピタキシャルシリコンウェーハの製造方法。     In the manufacturing method of the epitaxial silicon wafer according to claim 10,
    An epitaxial silicon wafer manufacturing method, wherein an initial interstitial oxygen concentration of the silicon single crystal substrate is 2.7 × 10 18 atoms / cc (ASTM F-121, 1979) or less.
  14. 　請求項１０～１３のいずれか一項に記載のエピタキシャルシリコンウェーハの製造方法において、
    　前記非キャリア性ドーパントを含む第１及び第２の層は、非キャリア性ドーパントをイオン注入することにより形成することを特徴とするエピタキシャルシリコンウェーハの製造方法。     The method of manufacturing an epitaxial silicon wafer according to any one of claims 10 to 13,
    The method for producing an epitaxial silicon wafer, wherein the first and second layers containing the non-carrier dopant are formed by ion implantation of the non-carrier dopant.
  15. 　請求項１４に記載のエピタキシャルシリコンウェーハの製造方法において、
    　前記非キャリア性ドーパントを含む第１及び第２の層は、炭素イオンをイオン注入することにより形成されることを特徴とするエピタキシャルシリコンウェーハの製造方法。     In the manufacturing method of the epitaxial silicon wafer according to claim 14,
    The method for producing an epitaxial silicon wafer, wherein the first and second layers containing the non-carrier dopant are formed by ion implantation of carbon ions.
  16. 　請求項１０に記載のエピタキシャルシリコンウェーハの製造方法において、
    　前記非キャリア性ドーパントを含む第２の層は、非キャリア性ドーパントを含有する反応ガスを用いたエピタキシャル成長により形成することを特徴とするエピタキシャルシリコンウェーハの製造方法。     In the manufacturing method of the epitaxial silicon wafer according to claim 10,
    The method for producing an epitaxial silicon wafer, wherein the second layer containing the non-carrier dopant is formed by epitaxial growth using a reaction gas containing the non-carrier dopant.
  17. 　請求項１１に記載のエピタキシャルシリコンウェーハの製造方法において、
    　前記非キャリア性ドーパントを含む第１及び第２の層は、非キャリア性ドーパントを含有する反応ガスを用いたエピタキシャル成長により形成することを特徴とするエピタキシャルシリコンウェーハの製造方法。     In the manufacturing method of the epitaxial silicon wafer according to claim 11,
    The method for producing an epitaxial silicon wafer, wherein the first and second layers containing the non-carrier dopant are formed by epitaxial growth using a reaction gas containing the non-carrier dopant.
PCT/JP2009/063740 2008-08-06 2009-08-03 Epitaxial silicon wafer and method for production thereof WO2010016457A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008203402A JP2010040864A (en) 2008-08-06 2008-08-06 Epitaxial silicon wafer and method of manufacturing the same
JP2008-203402 2008-08-06

Publications (1)

Publication Number Publication Date
WO2010016457A1 true WO2010016457A1 (en) 2010-02-11

Family

ID=41663674

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/063740 WO2010016457A1 (en) 2008-08-06 2009-08-03 Epitaxial silicon wafer and method for production thereof

Country Status (3)

Country Link
JP (1) JP2010040864A (en)
TW (1) TW201013753A (en)
WO (1) WO2010016457A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014099456A (en) * 2012-11-13 2014-05-29 Sumco Corp Method for manufacturing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and method for manufacturing solid state image sensor
JP2014099457A (en) * 2012-11-13 2014-05-29 Sumco Corp Method for manufacturing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and method for manufacturing solid state image sensor
JP2017175145A (en) * 2017-05-01 2017-09-28 株式会社Sumco Semiconductor epitaxial wafer manufacturing method, semiconductor epitaxial wafer, and solid-state imaging element manufacturing method
JP2017183736A (en) * 2017-05-11 2017-10-05 株式会社Sumco Method for manufacturing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and method for manufacturing solid state image sensor

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012059849A (en) * 2010-09-08 2012-03-22 Shin Etsu Handotai Co Ltd Silicon epitaxial wafer and manufacturing method thereof
DE112012002072B4 (en) * 2011-05-13 2023-11-16 Sumco Corp. Method for producing an epitaxial silicon wafer, epitaxial silicon wafer and method for producing a solid-state image pickup device
JP6278591B2 (en) * 2012-11-13 2018-02-14 株式会社Sumco Manufacturing method of semiconductor epitaxial wafer, semiconductor epitaxial wafer, and manufacturing method of solid-state imaging device
JP5776669B2 (en) * 2012-11-13 2015-09-09 株式会社Sumco Epitaxial silicon wafer manufacturing method, epitaxial silicon wafer, and solid-state imaging device manufacturing method
JP5799935B2 (en) * 2012-11-13 2015-10-28 株式会社Sumco Manufacturing method of semiconductor epitaxial wafer, semiconductor epitaxial wafer, and manufacturing method of solid-state imaging device
JP6107068B2 (en) * 2012-11-13 2017-04-05 株式会社Sumco Epitaxial silicon wafer manufacturing method, epitaxial silicon wafer, and solid-state imaging device manufacturing method
JP5776670B2 (en) * 2012-11-13 2015-09-09 株式会社Sumco Epitaxial silicon wafer manufacturing method, epitaxial silicon wafer, and solid-state imaging device manufacturing method
JP5799936B2 (en) * 2012-11-13 2015-10-28 株式会社Sumco Manufacturing method of semiconductor epitaxial wafer, semiconductor epitaxial wafer, and manufacturing method of solid-state imaging device
JP6065848B2 (en) 2014-01-07 2017-01-25 株式会社Sumco Manufacturing method of semiconductor epitaxial wafer, semiconductor epitaxial wafer, and manufacturing method of solid-state imaging device
JP6427894B2 (en) * 2014-02-21 2018-11-28 株式会社Sumco Epitaxial wafer manufacturing method
JP2015220242A (en) * 2014-05-14 2015-12-07 株式会社Sumco Semiconductor epitaxial wafer manufacturing method and solid state image pickup element manufacturing method
JP2018098266A (en) * 2016-12-08 2018-06-21 キヤノン株式会社 Photoelectric conversion device, method of manufacturing photoelectric conversion device, and camera

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166032A (en) * 1985-01-17 1986-07-26 Matsushita Electronics Corp Semiconductor substrate
JPH04130731A (en) * 1990-09-21 1992-05-01 Hitachi Ltd Manufacture of semiconductor integrated circuit device
JP2001177086A (en) * 1999-12-21 2001-06-29 Sony Corp Image pickup element and its manufacturing method
JP2004281591A (en) * 2003-03-14 2004-10-07 Hitachi Ltd Semiconductor epitaxial wafer, its manufacturing method, semiconductor device, and its manufacturing method
WO2009004889A1 (en) * 2007-07-04 2009-01-08 Shin-Etsu Handotai Co., Ltd. Thin film silicon wafer and its fabricating method
JP2009164590A (en) * 2007-12-13 2009-07-23 Sumco Corp Epitaxial wafer and method of producing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166032A (en) * 1985-01-17 1986-07-26 Matsushita Electronics Corp Semiconductor substrate
JPH04130731A (en) * 1990-09-21 1992-05-01 Hitachi Ltd Manufacture of semiconductor integrated circuit device
JP2001177086A (en) * 1999-12-21 2001-06-29 Sony Corp Image pickup element and its manufacturing method
JP2004281591A (en) * 2003-03-14 2004-10-07 Hitachi Ltd Semiconductor epitaxial wafer, its manufacturing method, semiconductor device, and its manufacturing method
WO2009004889A1 (en) * 2007-07-04 2009-01-08 Shin-Etsu Handotai Co., Ltd. Thin film silicon wafer and its fabricating method
JP2009164590A (en) * 2007-12-13 2009-07-23 Sumco Corp Epitaxial wafer and method of producing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014099456A (en) * 2012-11-13 2014-05-29 Sumco Corp Method for manufacturing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and method for manufacturing solid state image sensor
JP2014099457A (en) * 2012-11-13 2014-05-29 Sumco Corp Method for manufacturing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and method for manufacturing solid state image sensor
JP2017175145A (en) * 2017-05-01 2017-09-28 株式会社Sumco Semiconductor epitaxial wafer manufacturing method, semiconductor epitaxial wafer, and solid-state imaging element manufacturing method
JP2017183736A (en) * 2017-05-11 2017-10-05 株式会社Sumco Method for manufacturing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and method for manufacturing solid state image sensor

Also Published As

Publication number Publication date
TW201013753A (en) 2010-04-01
JP2010040864A (en) 2010-02-18

Similar Documents

Publication Publication Date Title
WO2010016457A1 (en) Epitaxial silicon wafer and method for production thereof
US7776723B2 (en) Method of manufacturing an epitaxial semiconductor substrate and method of manufacturing a semiconductor device
US7755085B2 (en) Semiconductor device and method for fabricating same
WO2015034075A1 (en) Silicon wafer and method for producing same
WO2007125863A1 (en) Soi wafer manufacturing method
JP2010010615A (en) Silicon substrate for solid-state imaging element, and method of manufacturing the same
US7910455B2 (en) Method for producing SOI wafer
JP2010153815A6 (en) Semiconductor substrate manufacturing method and semiconductor substrate
US6339011B1 (en) Method of forming semiconductive active area having a proximity gettering region therein and method of processing a monocrystalline silicon substrate to have a proximity gettering region
JP6442818B2 (en) Silicon wafer and manufacturing method thereof
JP5439801B2 (en) Epitaxial wafer and method for manufacturing the same
TWI688002B (en) Method for manufacturing epitaxial silicon wafer, method for manufacturing epitaxial silicon wafer and solid imaging element
JP2006216934A (en) Method of manufacturing epitaxial semiconductor substrate and method of manufacturing semiconductor device
JP5625239B2 (en) Manufacturing method of bonded wafer
JP5292810B2 (en) Manufacturing method of SOI substrate
CN111108583B (en) Semiconductor epitaxial wafer, method for producing same, and method for producing solid-state imaging element
TWI643250B (en) Method for manufacturing epitaxial wafer and epitaxial wafer
WO2012086122A1 (en) Method for manufacturing soi wafer
KR101184380B1 (en) Method of manufacturing an epitaxial wafer and the epitaxial wafer applying the same and semiconductor device
JP7334698B2 (en) SOI WAFER MANUFACTURING METHOD AND SOI WAFER
US20110298094A1 (en) Epitaxial wafer and method of producing the same
JP7380517B2 (en) SOI wafer manufacturing method and SOI wafer
JP2018137278A (en) Bonded soi wafer manufacturing method
JPWO2004086488A1 (en) Semiconductor epitaxial wafer
JP2011054654A (en) Method of manufacturing silicon wafer for thinned device element

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09804940

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09804940

Country of ref document: EP

Kind code of ref document: A1