WO2010016457A1 - Tranche de silicium épitaxiale et son procédé de fabrication - Google Patents

Tranche de silicium épitaxiale et son procédé de fabrication Download PDF

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WO2010016457A1
WO2010016457A1 PCT/JP2009/063740 JP2009063740W WO2010016457A1 WO 2010016457 A1 WO2010016457 A1 WO 2010016457A1 JP 2009063740 W JP2009063740 W JP 2009063740W WO 2010016457 A1 WO2010016457 A1 WO 2010016457A1
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layer
epitaxial
carrier dopant
silicon
single crystal
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Japanese (ja)
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英一 浅山
尚志 足立
民雄 本山
光二 松本
和尚 鳥越
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株式会社Sumco
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

Definitions

  • the present invention relates to an epitaxial silicon wafer and a manufacturing method thereof.
  • CZ-Si substrates grown by the CZ method have been used for highly integrated silicon semiconductor devices.
  • supersaturated interstitial oxygen is in the order of about 10 18 atoms / cm 3 for these CZ-Si substrates. It is well known that crystal defects such as oxygen precipitates, dislocations and stacking faults are induced in the device manufacturing process.
  • an epitaxial silicon wafer obtained by growing an epitaxial layer almost completely free of crystal defects on a CZ-Si substrate is often used for highly integrated devices.
  • Gettering technologies include intrinsic gettering (IG) using crystal defects caused by oxygen naturally induced during heat treatment of device processes as a sink, and sand blasting, Si 3 N 4 film, or Poly-Si film growth. There is an extrinsic gettering (EG) typified by back surface distortion.
  • IG intrinsic gettering
  • EG extrinsic gettering
  • MCPs multi-chip packages
  • Patent Document 1 and Patent Document 2 propose an epitaxial wafer including a layer containing a non-carrier dopant on a Si substrate.
  • the problem to be solved by the present invention is to provide an epitaxial silicon wafer having high gettering ability even if the integrated circuit substrate is thinned.
  • An epitaxial silicon wafer and a manufacturing method thereof according to the present invention are epitaxial silicon wafers having a silicon epitaxial layer on a main surface of a silicon single crystal substrate, and at least a non-carrier dopant is added to the silicon single crystal substrate and the silicon epitaxial layer.
  • a first layer including a second layer including a non-carrier dopant is formed.
  • the first layer containing at least the non-carrier dopant and the second layer containing the non-carrier dopant are formed on the silicon single crystal substrate and the silicon epitaxial layer
  • heat treatment such as an epitaxial growth step or a subsequent device step is performed.
  • Oxygen contained in the silicon single crystal substrate flows into the first layer containing the non-carrier dopant, and the distortion of the first layer containing the non-carrier dopant is relaxed. Almost no oxygen flows into the second layer containing the non-carrier dopant formed in (1).
  • the strain of the second layer containing the non-carrier dopant is maintained, and as a result, the gettering ability of the impurity metal by the second layer containing the non-carrier dopant is maintained in a high state.
  • an epitaxial silicon wafer having high gettering ability can be obtained even if the integrated circuit substrate is thinned.
  • 1A to 1E are sectional views of a wafer showing a method of manufacturing an epitaxial silicon wafer according to the first embodiment.
  • the silicon single crystal grown by the CZ method is first subjected to processing such as slicing, grinding, etching, mirror polishing, and the like to obtain the silicon single crystal substrate 1.
  • the diameter and thickness of the silicon single crystal substrate 1 are not particularly limited, but the initial interstitial oxygen concentration is limited to 2.7 ⁇ 10 18 atoms / cc (ASTM F-121, 1979) or less from the solid solubility.
  • the silicon single crystal substrate 1 is set in an ion implantation apparatus, and carbon ions are ion-implanted into one surface (upper surface in FIG. 1) of the silicon single crystal substrate 1 as shown in FIG. 1A, as shown in FIG. 1B.
  • a first layer 2 containing a non-carrier dopant is formed near the surface of the silicon single crystal substrate 1.
  • Carbon ions can be implanted under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2.0 ⁇ m.
  • ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used.
  • the first layer 2 including the non-carrier dopant of this example has a function of capturing oxygen existing in the silicon single crystal substrate 1, it is more preferable to use a dopant such as carbon that easily binds to the oxygen. preferable.
  • the depth of the first layer 2 containing the non-carrier dopant is not particularly limited, but in consideration of the function of capturing oxygen present in the silicon single crystal substrate 1, it is formed as close to the surface of the silicon single crystal substrate 1 as possible. More preferably.
  • the silicon single crystal substrate 1 on which the first layer 2 containing the non-carrier dopant is formed is set in a vapor phase growth apparatus, and the silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 as shown in FIG. 1C. Form.
  • a monosilane gas or a hydrogen-diluted chlorosilane-based gas added with a diborane (P-type) or phosphine or arsine (N-type) dopant source gas is used.
  • a silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 by a thermal CVD reaction. The thickness of the silicon epitaxial layer 3 is appropriately selected according to the target device.
  • the silicon single crystal substrate 1 on which the silicon epitaxial layer 3 is formed is set in an ion implantation apparatus, and as shown in FIG. 1D, carbon ions are ion-implanted into the surface of the silicon epitaxial layer 3 (upper surface in the figure).
  • a second layer 4 containing a non-carrier dopant is formed in the silicon epitaxial layer 3.
  • This carbon ion implantation can be performed under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2 ⁇ m.
  • ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe and the like can also be used.
  • the second layer 4 containing a non-carrier dopant in this example is responsible for the function of trapping metal impurities in the device process. It is more preferable to use a dopant that easily binds to impurities.
  • the depth of the second layer 4 containing the non-carrier dopant is not particularly limited, but in consideration of the metal impurity trapping function, the second layer 4 is formed at a position deeper than the device active region and in the vicinity of the device active region. Is more preferable.
  • the oxygen present in the silicon single crystal substrate 1 tends to diffuse outward by the heat treatment in the vapor phase growth process and the heat treatment in the subsequent device process, but as shown by arrows in FIG. 1E, Oxygen present on the back side of the first layer 2 containing the non-carrier dopant is attracted to the strain generated by the first layer 2 containing the non-carrier dopant and is bonded to carbon.
  • the second layer 4 containing the non-carrier dopant formed in the silicon epitaxial layer 3 is very small. Since only a small amount of oxygen is captured (oxygen present in the region on the surface side of the silicon single crystal substrate 1 from the first layer 2 containing the non-carrier dopant), the non-carrier dopant is It is possible to suppress a decrease in the metal impurity capturing function of the second layer 4 that is included.
  • the initial oxygen concentration of the silicon single crystal substrate 1 is high, oxygen can be captured by the first layer 2 containing the non-carrier dopant, and the second layer 4 containing the non-carrier dopant exhibits the gettering function. Therefore, a wafer having a high gettering ability can be obtained without using a silicon single crystal having a low initial oxygen concentration.
  • the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant can be formed even if the wafer itself is thinned, it is applied to a device wafer such as MCP. be able to.
  • Second Embodiment are cross-sectional views of a wafer showing a method of manufacturing an epitaxial silicon wafer according to the second embodiment.
  • a first layer 2 containing a non-carrier dopant and a second layer 4 containing a non-carrier dopant are formed on the silicon epitaxial layer 3.
  • the silicon single crystal grown by the CZ method is subjected to processing such as slicing, grinding, etching, mirror polishing, etc., and the silicon single crystal substrate 1 is obtained.
  • the diameter and thickness of the silicon single crystal substrate 1 are not particularly limited, but the initial interstitial oxygen concentration is limited to 2.7 ⁇ 10 18 atoms / cc (ASTM F-121, 1979) or less from the solid solubility. This is the same as in the first embodiment.
  • this silicon single crystal substrate 1 is set in a vapor phase growth apparatus, and a silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 as shown in FIG. 2B.
  • diborane (P-type) or phosphine or arsine (N-type) is added to a monosilane gas or a hydrogen-diluted chlorosilane-based gas, as in the first embodiment.
  • a material to which a dopant source gas is added can be used.
  • a silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 by a thermal CVD reaction. The thickness of the silicon epitaxial layer 3 is appropriately selected according to the target device.
  • the silicon single crystal substrate 1 on which the silicon epitaxial layer 3 is formed is set in an ion implantation apparatus, and as shown in FIG. 2C, carbon ions are ion-implanted into the surface of the silicon epitaxial layer 3 (upper surface in the figure).
  • a first layer 2 containing a non-carrier dopant is formed in the silicon epitaxial layer 3.
  • This carbon ion implantation can be performed under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2 ⁇ m.
  • ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used.
  • the first layer 2 including the non-carrier dopant of this example has a function of capturing oxygen existing in the silicon single crystal substrate 1, it is more preferable to use a dopant such as carbon that easily binds to the oxygen. preferable.
  • the depth of the first layer 2 containing the non-carrier dopant is not particularly limited, but in consideration of the function of capturing oxygen present in the silicon single crystal substrate 1, it is formed as close to the surface of the silicon single crystal substrate 1 as possible. More preferably.
  • carbon ions are ion-implanted into the surface (upper surface in FIG. 2) of the silicon epitaxial layer 3 on which the first layer 2 containing the non-carrier dopant is formed by an ion implantation apparatus.
  • the second layer 4 containing the non-carrier dopant is formed on the surface side of the first layer 2 containing the non-carrier dopant of the silicon epitaxial layer 3.
  • This carbon ion implantation can be performed under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2 ⁇ m.
  • ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used.
  • the second layer 4 containing a non-carrier dopant in this example is responsible for the function of trapping metal impurities in the device process. It is more preferable to use a dopant that easily binds to impurities.
  • the depth of the second layer 4 containing the non-carrier dopant is not particularly limited, but in consideration of the metal impurity trapping function, the second layer 4 is formed at a position deeper than the device active region and in the vicinity of the device active region. Is more preferable.
  • a wafer is obtained in which the first layer 2 containing a non-carrier dopant is formed at a deep position of the silicon epitaxial layer 3 and the second layer 4 containing a non-carrier dopant is formed at a shallow position. .
  • the oxygen present in the silicon single crystal substrate 1 tends to diffuse outward by the heat treatment in the subsequent device process, but as shown by the arrow in FIG. 2F, the oxygen present in the silicon single crystal substrate 1 Is attracted to the strain generated by the first layer 2 containing a non-carrier dopant and bonds to carbon.
  • the second layer 4 containing the non-carrier dopant formed in a shallow position of the silicon epitaxial layer 3. In this case, almost no oxygen is trapped (the silicon epitaxial layer does not contain oxygen), so that the metal impurity trapping function of the second layer 4 containing the non-carrier dopant can be maintained.
  • the initial oxygen concentration of the silicon single crystal substrate 1 is high, oxygen can be captured by the first layer 2 containing the non-carrier dopant, and the second layer 4 containing the non-carrier dopant exhibits the gettering function. Therefore, a wafer having a high gettering ability can be obtained without using a silicon single crystal having a low initial oxygen concentration.
  • the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant can be formed even if the wafer itself is thinned, it is applied to a device wafer such as MCP. be able to.
  • 3A to 3E are cross-sectional views of a wafer showing a method of manufacturing an epitaxial silicon wafer according to a third embodiment.
  • a first layer 2 containing a non-carrier dopant and a second layer 4 containing a non-carrier dopant are formed on a silicon single crystal substrate 1.
  • a silicon single crystal grown by the CZ method is subjected to processing such as slicing, grinding, etching, mirror polishing, and the like to obtain a silicon single crystal substrate 1.
  • the diameter and thickness of the silicon single crystal substrate 1 are not particularly limited, but the initial interstitial oxygen concentration is limited to 2.7 ⁇ 10 18 atoms / cc (ASTM F-121, 1979) or less from the solid solubility. This is the same as in the first embodiment.
  • the silicon single crystal substrate 1 is set in an ion implantation apparatus, and carbon ions are ion-implanted into one surface (upper surface in FIG. 3) of the silicon single crystal substrate 1 as shown in FIG. First, a first layer 2 containing a non-carrier dopant is formed near the surface of the silicon single crystal substrate 1.
  • Carbon ions can be implanted under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2000 ⁇ m.
  • ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used.
  • the first layer 2 including the non-carrier dopant of this example has a function of capturing oxygen existing in the silicon single crystal substrate 1, it is more preferable to use a dopant such as carbon that easily binds to the oxygen. preferable.
  • the depth of the first layer 2 containing the non-carrier dopant is not particularly limited, but in consideration of the function of capturing oxygen present in the silicon single crystal substrate 1, it is formed as close to the surface of the silicon single crystal substrate 1 as possible. More preferably.
  • carbon ions are ion-implanted into the surface of the silicon single crystal substrate 1 on which the first layer 2 containing the non-carrier dopant is formed by an ion implantation apparatus, as shown in FIG. 3D.
  • the second layer 4 containing the non-carrier dopant is formed on the surface side of the first layer 2 containing the non-carrier dopant.
  • This carbon ion implantation can be performed under the conditions of an acceleration energy of 1 to 2000 keV, a peak density of 10 15 to 10 22 atoms / cc, and a depth from the surface of 0.01 to 2 ⁇ m.
  • ions to be ion-implanted may be any non-carrier dopant, and Si, Ge, Sn, Pb, He, Ne, Ar, Kr, Xe, and the like can also be used.
  • the second layer 4 containing a non-carrier dopant in this example is responsible for the function of trapping metal impurities in the device process. It is more preferable to use a dopant that easily binds to impurities.
  • the depth of the second layer 4 containing the non-carrier dopant is not particularly limited, but considering the metal impurity trapping function, the depth is deeper than the device active region and in the vicinity of the device active region, that is, silicon single layer. More preferably, it is formed near the surface of the crystal substrate 1.
  • the silicon single crystal substrate 1 on which the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant are formed is set in a vapor phase growth apparatus, and silicon as shown in FIG. 3E. Silicon epitaxial layer 3 is formed on the surface of single crystal substrate 1.
  • diborane (P-type) or phosphine or arsine (N-type) is added to a monosilane gas or a hydrogen-diluted chlorosilane-based gas, as in the first embodiment.
  • a material to which a dopant source gas is added can be used.
  • a silicon epitaxial layer 3 is formed on the surface of the silicon single crystal substrate 1 by a thermal CVD reaction. The thickness of the silicon epitaxial layer 3 is appropriately selected according to the target device.
  • oxygen present in the silicon single crystal substrate 1 tends to diffuse outward by the heat treatment in the vapor phase growth process and the heat treatment in the subsequent device process, but as shown by arrows in FIG. Oxygen present on the back side of the first layer 2 containing the non-carrier dopant is attracted to the strain generated by the first layer 2 containing the non-carrier dopant and is bonded to carbon.
  • the distortion of the first layer 2 containing the non-carrier dopant is relaxed and the function of capturing the metal impurity is lowered, the first layer 2 containing the non-carrier dopant formed on the silicon epitaxial layer 3 side of the silicon single crystal substrate 1 is reduced. Only a small amount of oxygen is trapped in the second layer 4 (oxygen present in the region on the surface side of the silicon single crystal substrate 1 from the layer 2 containing the first non-carrier dopant is trapped). Therefore, it is possible to suppress a decrease in the function of trapping metal impurities in the second layer 4 containing the non-carrier dopant.
  • the initial oxygen concentration of the silicon single crystal substrate 1 is high, oxygen can be captured by the first layer 2 containing the non-carrier dopant, and the second layer 4 containing the non-carrier dopant exhibits the gettering function. Therefore, a wafer having a high gettering ability can be obtained without using a silicon single crystal having a low initial oxygen concentration.
  • the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant can be formed even if the wafer itself is thinned, it is applied to a device wafer such as MCP. be able to.
  • ⁇ 4th Embodiment are sectional views of a wafer showing a method for manufacturing an epitaxial silicon wafer according to the fourth embodiment.
  • a first layer 2 containing a non-carrier dopant and a second layer 4 containing a non-carrier dopant are formed on a silicon epitaxial layer 3, and the structure is the same as in the second embodiment.
  • the first and second layers 2 and 4 containing a non-carrier dopant are formed by vapor deposition instead of ion implantation.
  • the silicon single crystal grown by the CZ method is subjected to processing such as slicing, grinding, etching, mirror polishing, and the like to obtain the silicon single crystal substrate 1.
  • the diameter and thickness of the silicon single crystal substrate 1 are not particularly limited, but the initial interstitial oxygen concentration is limited to 2.7 ⁇ 10 18 atoms / cc (ASTM F-121, 1979) or less from the solid solubility. This is the same as in the second embodiment.
  • this silicon single crystal substrate 1 is set in a vapor phase growth apparatus, and a silicon epitaxial layer 3a is formed on the surface of the silicon single crystal substrate 1 as shown in FIG. 4B.
  • diborane (P-type) or phosphine or arsine (N-type) is added to monosilane gas or hydrogen-diluted chlorosilane-based gas, as in the second embodiment.
  • a material to which a dopant source gas is added can be used.
  • a silicon epitaxial layer 3a is formed on the surface of the silicon single crystal substrate 1 by a thermal CVD reaction.
  • reaction gas of the vapor phase growth apparatus is switched, carbon as a non-carrier dopant is contained in the reaction gas, and vapor phase growth is performed, whereby non-carriers are formed on the surface of the silicon epitaxial layer 3a as shown in FIG. 4C.
  • a first layer 2 containing a conductive dopant is formed.
  • the reaction gas of the vapor phase growth apparatus is switched to the reaction gas in which the silicon epitaxial layer 3a is grown, and the silicon epitaxial layer 3b is formed on the surface of the first layer 2 containing the non-carrier dopant as shown in FIG. 4D. It is formed by vapor phase growth.
  • reaction gas of the vapor phase growth apparatus is switched, carbon as a non-carrier dopant is contained in the reaction gas, and vapor phase growth is performed, whereby non-carrier is formed on the surface of the silicon epitaxial layer 3b as shown in FIG. 4E.
  • a second layer 4 containing a conductive dopant is formed.
  • the reaction gas of the vapor phase growth apparatus is switched to the reaction gas in which the silicon epitaxial layers 3a and 3b are grown, and a silicon epitaxial layer is formed on the surface of the second layer 4 containing a non-carrier dopant as shown in FIG. 4F. 3c is formed by vapor phase growth.
  • the total thickness of the silicon epitaxial layers 3a, 3b, 3c, the first layer 2 containing a non-carrier dopant, and the second layer 4 containing a non-carrier dopant is appropriately selected according to the target device. .
  • the first layer 2 containing the non-carrier dopant is formed in the deep position of the silicon epitaxial layer 3, and the second layer containing the non-carrier dopant in the shallow position.
  • a wafer having 4 formed thereon is obtained.
  • oxygen existing in the silicon single crystal substrate 1 tends to diffuse outward by the heat treatment in the subsequent device process.
  • oxygen present in the silicon single crystal substrate 1 Is attracted to the strain generated by the first layer 2 containing a non-carrier dopant and bonds to carbon.
  • the second layer 4 containing the non-carrier dopant formed at a shallow position of the silicon epitaxial layer 3. Almost no oxygen is trapped (the silicon epitaxial layers 3a, 3b, 3c do not contain oxygen), so that the function of trapping metal impurities of the second layer 4 containing the non-carrier dopant can be maintained. .
  • the initial oxygen concentration of the silicon single crystal substrate 1 is high, oxygen can be captured by the first layer 2 containing the non-carrier dopant, and the second layer 4 containing the non-carrier dopant exhibits the gettering function. Therefore, a wafer having a high gettering ability can be obtained without using a silicon single crystal having a low initial oxygen concentration.
  • the first layer 2 containing the non-carrier dopant and the second layer 4 containing the non-carrier dopant can be formed even if the wafer itself is thinned, it is applied to a device wafer such as MCP. be able to.

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Abstract

L'invention porte sur une tranche de silicium épitaxiale. L'invention porte également sur un procédé de fabrication de la tranche de silicium épitaxiale. La tranche de silicium épitaxiale est caractérisée par le fait qu'elle comprend une plaque de base monocristalline de silicium (1) et une couche épitaxiale de silicium (3) agencée sur la surface principale de la plaque de base (1), et est également caractérisée par le fait qu'au moins une première couche (2) contenant un dopant non porteur et une seconde couche (4) contenant un dopant non porteur sont formées sur la plaque de base monocristalline de silicium et la couche épitaxiale de silicium.
PCT/JP2009/063740 2008-08-06 2009-08-03 Tranche de silicium épitaxiale et son procédé de fabrication WO2010016457A1 (fr)

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JP2008-203402 2008-08-06
JP2008203402A JP2010040864A (ja) 2008-08-06 2008-08-06 エピタキシャルシリコンウェーハ及びその製造方法

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JP2014099457A (ja) * 2012-11-13 2014-05-29 Sumco Corp 半導体エピタキシャルウェーハの製造方法、半導体エピタキシャルウェーハ、および固体撮像素子の製造方法
JP2017175145A (ja) * 2017-05-01 2017-09-28 株式会社Sumco 半導体エピタキシャルウェーハの製造方法、半導体エピタキシャルウェーハ、および固体撮像素子の製造方法
JP2017183736A (ja) * 2017-05-11 2017-10-05 株式会社Sumco 半導体エピタキシャルウェーハの製造方法、半導体エピタキシャルウェーハ、および固体撮像素子の製造方法

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WO2012157162A1 (fr) * 2011-05-13 2012-11-22 株式会社Sumco Procédé de fabrication d'une plaquette épitaxiale de semi-conducteur, plaquette épitaxiale de semi-conducteur et procédé de fabrication d'un élément de prise de vue à semi-conducteur
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JP5799935B2 (ja) * 2012-11-13 2015-10-28 株式会社Sumco 半導体エピタキシャルウェーハの製造方法、半導体エピタキシャルウェーハ、および固体撮像素子の製造方法
JP5776669B2 (ja) * 2012-11-13 2015-09-09 株式会社Sumco エピタキシャルシリコンウェーハの製造方法、エピタキシャルシリコンウェーハ、および固体撮像素子の製造方法
JP6107068B2 (ja) * 2012-11-13 2017-04-05 株式会社Sumco エピタキシャルシリコンウェーハの製造方法、エピタキシャルシリコンウェーハ、および固体撮像素子の製造方法
JP5799936B2 (ja) * 2012-11-13 2015-10-28 株式会社Sumco 半導体エピタキシャルウェーハの製造方法、半導体エピタキシャルウェーハ、および固体撮像素子の製造方法
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JP6065848B2 (ja) * 2014-01-07 2017-01-25 株式会社Sumco 半導体エピタキシャルウェーハの製造方法、半導体エピタキシャルウェーハ、および固体撮像素子の製造方法
JP6427894B2 (ja) * 2014-02-21 2018-11-28 株式会社Sumco エピタキシャルウェーハの製造方法
JP2015220242A (ja) * 2014-05-14 2015-12-07 株式会社Sumco 半導体エピタキシャルウェーハの製造方法および固体撮像素子の製造方法
JP2018098266A (ja) * 2016-12-08 2018-06-21 キヤノン株式会社 光電変換装置、光電変換装置の製造方法およびカメラ

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JP2014099456A (ja) * 2012-11-13 2014-05-29 Sumco Corp 半導体エピタキシャルウェーハの製造方法、半導体エピタキシャルウェーハ、および固体撮像素子の製造方法
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