JPH10247731A - Semiconductor wafer, and manufacture thereof, and semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an epitaxial wafer for a MIS(metal insulator semiconductor) device at a low cost, wherein the wafer is improved in gettering capacity and possessed of a gate oxide film (GOI) excellent in properties. SOLUTION: An epitaxial layer is made to grow on the main surface of a single crystal silicon wafer which is so tilted as to cross at right angles a crystal axis within an angle of 35 deg. from one of axes in the [010] direction in the (100) plane as a main plane and within an angle of 2.5 deg. to 15 deg. from a 100 crystal axis. By this setup, OSF(oxidation induced stacking fault) is restrained (a reduction in OSF dislocation density) from being induced on the surface (MISFET formation region) of the epitaxial layer, so that the silicon wafer of this constitution can be possessed of a heavy metal gettering capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer and a method of manufacturing the same, and a semiconductor integrated circuit device and a method of manufacturing the same using the same, and more particularly, to a semiconductor wafer grown on a main surface of a single crystal silicon (Si) wafer. MISFET (Metal Insulator Semiconductor Field)
The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device that forms an integrated circuit configured by an effect transistor.

[0002]

2. Description of the Related Art In recent years, in the field of MIS devices in which an integrated circuit is composed of MISFETs, CZ is required to improve the breakdown voltage of a gate oxide film and to reduce the leakage current of a pn junction.
The introduction of a semiconductor wafer (epitaxial wafer) in which an epitaxial layer is grown on the main surface of a single crystal silicon wafer (CZ wafer) manufactured by the (Czochralski) method is in progress.

Since a silicon wafer (hereinafter referred to as a CZ wafer) is made by pulling up silicon melted in a quartz crucible (crucible), excess oxygen eluted from the crucible is taken in between crystal lattices (up to 20 ppma). (JEI
DA conversion)). When the interstitial oxygen concentration is increased, oxygen precipitation is promoted, and the breakdown voltage of the gate oxide film is deteriorated and the junction leak current is increased. Therefore, when forming a MISFET on the main surface of a CZ wafer, it is necessary to reduce oxygen precipitates near the wafer surface by lowering the oxygen concentration of the substrate.

[0004] On the other hand, the epitaxial layer formed on the CZ wafer does not take in oxygen during the growth process unlike the CZ wafer. In addition, many glow-in defects (up to 20 ppma (in terms of JEIDA)) present on the CZ wafer are extremely small in the epitaxial layer. Therefore, the MI obtained by thermally oxidizing the surface of the epitaxial layer
The gate oxide film of the SFET has higher quality and higher reliability than the gate oxide film obtained by thermally oxidizing the surface of the CZ wafer. That is, by using an epitaxial wafer, the gate oxide film characteristics (Gate Oxide in
tegrity (GOI) can be improved.

However, since the epitaxial layer itself formed on the CZ wafer has few glow-in defects and oxygen precipitates, and has few defects serving as nuclei for capturing contaminants such as heavy metals, the epitaxial layer has a gettering property as compared with the CZ wafer. A drop in ring capacity is expected. When an epitaxial layer is formed on a CZ wafer, a temperature of 950 ° C. to 1100 ° C. is set in advance to remove a natural oxide film on the surface of the CZ wafer.
It is necessary to perform hydrogen annealing at about ℃ and several tens of minutes. However, if this heat treatment is performed, the glow-in defect in the CZ wafer dissolves and disappears, and the oxygen precipitation is suppressed. Resulting in.

In the case of an epitaxial wafer for a bipolar transistor, an epitaxial layer is formed during the manufacturing process. Therefore, the CZ wafer is kept at a low temperature (for example, 650 to 750 ° C.) prior to the epitaxial growth step.
, A precipitation nucleus is formed at that time, so that even if a high temperature heat treatment is performed during epitaxial growth, oxygen precipitation occurs inside the wafer, and the gettering ability is not lost.
In contrast, an epitaxial wafer for a MIS device is exposed to a high temperature during epitaxial growth without being subjected to such a heat treatment, so that precipitation nuclei shrink and disappear, and the growth of oxygen precipitates is suppressed in the subsequent heat treatment. Is done.

[0007] Heavy metal contamination in a semiconductor manufacturing process causes deterioration of a gate oxide film and an increase in junction leak current, and an oxidation induced stacking fault (OSF).
d Stacking-fault). Therefore, MISFE
To improve the reliability of T and the production yield, MI
Areas related to SFET electrical characteristics (surface area of wafer)
Measures to remove heavy metals from water are indispensable.

For these reasons, an epitaxial wafer for a MIS device has a high concentration (for example, 1 × 10 ¹⁸ to 1 × 10 ²⁰ atoms / cm) for the purpose of improving the gettering ability.
cm ³ ) of low resistance (for example, specific resistance of 0.01)
A CZ wafer of about 0.001 Ωcm) is used. In particular, a CZ wafer to which boron (B) is added at a high concentration (p + CZ wafer) is considered to be effective in improving the gettering ability for heavy metals such as iron (Fe). In addition, low resistance C
The use of an epitaxial wafer in which an epitaxial layer is grown on a Z wafer is effective as a measure to improve the latch-up resistance and the α-ray resistance of the MIS device.

An epitaxial wafer (p) having a p-type epitaxial layer formed on a p-type low resistance CZ wafer
/ P epitaxial wafer), published by the Japan Society of Applied Physics, August 10, 1991, "Applied Physics Vol. 60, No. 8," p. 762-p.
No. 832.

[0010]

However, when an epitaxial layer is formed on a CZ wafer to which impurities are added at a high concentration, the impurities in the CZ wafer are moved outward from the back surface by heat treatment during epitaxial growth (or during the manufacturing process). The doping (auto-doping) of the surface of the epitaxial layer due to diffusion (Out Diffuse), or the impurity rising from the main surface of the CZ wafer to the epitaxial layer causes a change in the impurity concentration profile of the element formation region. MISF, such as variation in value voltage (Vth)
ET characteristics may be degraded.

On the other hand, in order to avoid the above problem, for example, the epitaxial layer is thickened (for example, about 8 to 10 μm).
The growth may be performed to reduce the influence of the rise of impurities from the CZ wafer, or the back surface (and the side surface) of the CZ wafer may be covered with an insulating film such as silicon oxide before the epitaxial layer is formed to prevent out-diffusion of impurities. Then, the manufacturing cost of the epitaxial wafer increases. Further, low resistance (for example, specific resistance of 0.01 to 0.0) in which impurities are added at a high concentration.
A CZ wafer of about 01 Ωcm) itself has a specific resistance of 1
The manufacturing cost is higher than a normal CZ wafer of about 0 Ωcm.

As described above, the production cost of the conventional epitaxial wafer for a MIS device increases when an attempt is made to obtain an epitaxial layer having high quality and improved gettering ability. As a result, the production cost of the MIS device is increased. There was a problem that would increase.

An object of the present invention is to provide, at low cost, an epitaxial wafer for a MIS device having improved gettering ability and gate oxide film characteristics (GOI).

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) The semiconductor wafer of the present invention is an epitaxial wafer in which an epitaxial layer is grown on a main surface of a CZ wafer manufactured by the Czochralski method, wherein the main surface of the CZ wafer is a (100) plane, 35 from any one axis in the [010] direction in that plane.
The angle is inclined so as to be perpendicular to the crystal axis within the range of 2.5 ° to 15 ° from the 100 crystal axis.

(2) The epitaxial wafer of the present invention comprises:
The thickness of the epitaxial layer is 0.3 to 5 μm.

(3) The epitaxial wafer of the present invention comprises:
The initial oxygen concentration of the CZ wafer is 17 ppma (JEIDA
Conversion).

(4) The epitaxial wafer of the present invention comprises:
An impurity of a predetermined conductivity type is added to the CZ wafer at 1 × 10 ¹⁵ at.
oms / cm ³ or more and less than 3 × 10 ¹⁶ atoms / cm ³ , and the epitaxial layer is doped with an impurity of the same conductivity type as the impurity at a concentration substantially equal to or less than the concentration range. I have.

(5) The epitaxial wafer of the present invention comprises:
The diameter of the CZ wafer is 8 inches or more.

(6) In the method of manufacturing an epitaxial wafer of the present invention, (a) the (100) plane is a principal plane, and within that plane, at an angle of 35 ° from any one axis in the [010] direction. A step of preparing a CZ wafer inclined so as to be perpendicular to a crystal axis within a range of 2.5 ° to 15 ° from the 100 crystal axis, and (b) preventing outward diffusion of impurities on at least the back surface of the CZ wafer. Growing an epitaxial layer on the main surface of the CZ wafer without forming an insulating film for performing the process.

(7) The method of manufacturing an epitaxial wafer according to the present invention is characterized in that the (100) plane is within a range of 35 ° from any one axis in the [010] direction and 2.5 ° from a 100 crystal axis. After raising the ingot using a seed crystal tilted so as to be perpendicular to the crystal axis within the range of 15 °, the CZ wafer is sliced on a plane orthogonal to the pulling direction. To form

(8) In the method of manufacturing an epitaxial wafer according to the present invention, after the ingot is pulled up using a seed crystal having the (100) plane as a main surface, the ingot is placed in one of the [010] directions. By slicing to expose a (100) plane that is inclined at 35 ° from one axis and perpendicular to a crystal axis within a range of 2.5 ° to 15 ° from the 100 crystal axis, The CZ wafer is formed.

(9) In the method of manufacturing an epitaxial wafer according to the present invention, after the step (a), prior to the step (b), the CZ wafer is annealed at least 600 ° C. for at least 30 minutes. Thus, a process for erasing the oxygen donor in the CZ wafer is performed.

(10) In the method of manufacturing an epitaxial wafer according to the present invention, the thickness of the epitaxial layer may be 0.3 to 5 μm.
m.

(11) In the method of manufacturing an epitaxial wafer according to the present invention, the CZ wafer may contain an impurity of a predetermined conductivity type at 1 × 10 ¹⁵ atoms / cm ³ or more and 3 × 10 ¹⁶ atoms / cm 3 when the ingot is pulled up. Doping in a concentration range of less than ³ ,
The epitaxial layer is doped with an impurity having the same conductivity type as that of the impurity at a concentration substantially equal to or less than the concentration range during the epitaxial growth.

(12) The semiconductor integrated circuit device of the present invention
MI formed by thermally oxidizing the surface of the epitaxial layer
It has an SFET gate oxide film.

(13) The semiconductor integrated circuit device of the present invention
The impurity concentration of the epitaxial layer is the MISFET
Is lower than the impurity concentration of the channel region.

(14) The semiconductor integrated circuit device of the present invention
A second conductivity type MISFET is formed in a first conductivity type well formed in a part of the epitaxial layer, and a first conductivity type MISFET is formed in a second conductivity type well formed in another part of the epitaxial layer. Have been.

(15) The semiconductor integrated circuit device of the present invention
The first conductivity type well and the second conductivity type well have a retrograde structure in which the impurity concentration inside is higher than the impurity concentration on the surface.

(16) The semiconductor integrated circuit device of the present invention
The first conductivity type well and the second conductivity type well are separated from each other by an element isolation groove formed in the epitaxial layer.

(17) The semiconductor integrated circuit device according to the present invention
A second conductivity type MISFET forming a memory cell of a DRAM is formed in a part of the first conductivity type well, and
A complementary MISFET forming a peripheral circuit of the DRAM is formed in another part of the conductive well and the second conductive well.

(18) The semiconductor integrated circuit device according to the present invention
A second conductivity type MISFET forming a part of a memory cell of the SRAM is formed in a part of the first conductivity type well, and the other part of the first conductivity type well and the second conductivity type well are connected to the second conductivity type MISFET. Complementary MISF Constituting Peripheral Circuit of SRAM
ET is formed.

(19) The semiconductor integrated circuit device of the present invention
A second conductivity type MISFET forming a memory cell of a nonvolatile memory is formed in a part of the first conductivity type well, and the non-volatile memory is formed in another part of the first conductivity type well and the second conductivity type well. M forming the peripheral circuit of the non-volatile memory
An ISFET is formed.

(20) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps (a) to (c).

(A) The (100) plane is defined as a main surface, and 35 ° from any one axis in the [010] direction within that plane.
Preparing a CZ wafer tilted so as to be perpendicular to the crystal axis within a range of 2.5 ° to 15 ° from the 100 crystal axis, and (b) at least the back surface of the CZ wafer Growing an epitaxial layer on the main surface of the CZ wafer without forming an insulating film for preventing out-diffusion; and (c) thermally oxidizing the surface of the epitaxial layer to form a gate oxide film of the MISFET. Forming step.

(21) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps (a) to (d).

(A) The (100) plane is defined as the principal plane, and 35 ° from any one axis in the [010] direction within the plane.
Preparing a CZ wafer tilted so as to be perpendicular to the crystal axis within a range of 2.5 ° to 15 ° from the 100 crystal axis, and (b) the CZ wafer is at least 60
A step of erasing oxygen donors in the CZ wafer by annealing at 0 ° C. or more for at least 30 minutes or more; (c) insulation for preventing outward diffusion of impurities on at least the back surface of the CZ wafer Growing an epitaxial layer on the main surface of the CZ wafer without forming a film, and (d) forming a gate oxide film of the MISFET by thermally oxidizing the surface of the epitaxial layer.

(22) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the epitaxial layer may have a thickness of 0.3 to 5 μm.
And

(23) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the CZ wafer may contain a predetermined conductivity type impurity of 1 × 10 ¹⁵ atoms / cm ³ or more and 3 × 10 ¹⁶ atoms when the ingot is pulled up. doped with a concentration range of less than / cm ^3,
The epitaxial layer is doped with an impurity having the same conductivity type as that of the impurity at a concentration substantially equal to or less than the concentration range during the epitaxial growth.

(24) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a first conductivity type well is formed by ion-implanting a first conductivity type impurity into a part of the epitaxial layer. Are ion-implanted with a second conductivity type impurity to form a second conductivity type well.

[0042]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) Referring to FIGS. 1 and 2, an epitaxial wafer (semiconductor wafer) of this embodiment will be described.
Will be described.

First, as shown in FIG. 1A, an ingot 100 of single crystal silicon is manufactured by using the Czochralski (CZ) method. This ingot 100 is pulled up within a range of 35 ° from any one axis in the [010] direction in the (100) plane and from the 100 crystal axis.
A seed crystal having an inclination angle that is perpendicular to the crystal axis in the range of 2.5 ° to 15 ° is used.

Further, for example, boron (B) is added as a dopant at the time of pulling, and the impurity (boron) concentration of the ingot 100 is set to about 1.5 × 10 ¹⁵ atoms / cm ³ (specific resistance = about 10 Ω · cm). I do. The impurity (boron) concentration of the ingot 100 may be higher than the above concentration as long as the impurity concentration profile of the element formation region of the epitaxial layer does not fluctuate due to impurities diffused outward from the wafer during the later formation of the epitaxial layer. However, in order to eliminate the need for a step of forming an insulating film for preventing out-diffusion of impurities on the back surface of the epitaxial wafer, 10 ¹⁵
It is appropriate to set the concentration not to greatly exceed the order of atoms / cm ³ .

That is, the impurity (boron) concentration is determined by the channel concentration (for example, 1 × 10 ¹⁷ at) of the MISFET described later.
oms / cm ³ ) which is lower than 3 × 10 ¹⁶ atoms / cm ³ (specific resistance = approximately 0.5 Ωcm) which is lower by about one digit than MISFET
Any range may be used as long as it does not affect the impurity concentration (for example, about 6 × 10 ¹⁷ atoms / cm ³ ) of the well which determines the device characteristics of the above.

When the ingot 100 is lifted, the amount of oxygen dissolved from the quartz crucible, the convection of the molten silicon and the amount of evaporation from the surface are controlled.
Usually, the concentration of oxygen taken into the ingot 100 is set, but in the present embodiment, such control is unnecessary. That is, the initial oxygen concentration of the ingot 100 may be, for example, a high concentration of 17 ppma (in JEIDA conversion) or higher, or may be lower than that.

Next, as shown in FIG. 3B, a part of the ingot 100 is cut, leaving only the ingot 100 in the region where the impurity concentration is within the above-mentioned range.

Next, as shown in FIG. 5C, after the outer periphery is ground and the orientation flat (or orientation notch) is formed on the ingot 100, the ingot 100 is lifted as shown in FIG. A silicon wafer (CZ wafer) 1 is prepared by slicing thinly on a surface perpendicular to the direction, and then, the outer peripheral portion of the CZ wafer 1 is chamfered to prevent chipping.

Next, as shown in FIG. 4E, after lapping both sides of the CZ wafer 1 to adjust the thickness and flatness, an acid or an acid is removed to remove mechanical strain caused by the lapping. Both surfaces of the CZ wafer 1 are wet-etched using an alkaline solution.

Next, as shown in FIG. 5F, the CZ wafer 1 is annealed at, for example, about 600 ° C. for about 30 minutes in a nitrogen atmosphere, so that an oxygen donor generated by oxygen mixed in during the lifting of the ingot 100 is formed. Is performed. This is due to the fact that during the cooling of the crystal pull, 450
This is because oxygen is converted into a donor at around 0 ° C., and the resistivity in the wafer surface greatly changes, so that a heat treatment for erasing the oxygen donor is required to obtain a desired resistivity.

Next, as shown in FIG. 3G, the surface on which the epitaxial layer is formed of the CZ wafer 1 is mirror-polished to make the (100) plane the main surface, and [010] in the (100) plane. 35 ° from any one axis in the direction
And a p-type CZ having an inclination angle perpendicular to the crystal axis within a range of 2.5 ° to 15 ° from the 100 crystal axis.
The wafer 1 is obtained. If an n-type impurity (for example, phosphorus (P)) is added as a dopant when the ingot 100 is pulled up, an n-type single crystal CZ wafer (CZ
Wafer) is obtained.

As another method of manufacturing the CZ wafer 1, an ingot 100 is manufactured using a seed crystal having no tilt angle (tilt angle = 0 °) as described above,
(100) having the above-mentioned inclination angle in the step (d)
The ingot 100 may be sliced so that the surface is exposed.

Next, as shown in FIG. 2, an epitaxial layer 2 of the same conductivity type (p-type) as that of the CZ wafer 1 is grown on the surface of the CZ wafer 1 so that the epitaxial wafer (p /
(p epitaxial wafer) 2EW is produced. Since the main surface of the CZ wafer 1 has the inclination angle as described above, the main surface of the epitaxial layer 2 grown on the main surface also has the same inclination angle. That is, the (100) plane is defined as a main surface, and within this (100) plane, within a range of 35 ° from any one axis in the [010] direction, and within a range of 2.5 ° to 15 ° from the 100 crystal axis. Thus, epitaxial wafer 2EW having p-type epitaxial layer 2 having an inclination angle perpendicular to the crystal axis inside is obtained.

To form the epitaxial layer 2,
For example, first, the CZ wafer 1 is put into an epitaxial growth furnace, and annealing is performed in a hydrogen atmosphere at about 950 to 1100 ° C. for about 10 minutes to remove a natural oxide film on the surface. Low temperature (about 900
１０００1000 ° C.) and then monosilane + B ₂ H ₆
For about 10 minutes to perform epitaxial growth.

In order to shorten the time for growing the epitaxial layer 2 and reduce the manufacturing cost of the epitaxial wafer 2EW, the upper limit of the thickness of the epitaxial layer 2 is set to 5 to 5.
It is appropriate that the thickness be 6 μm or less, preferably 3 μm or less. On the other hand, the lower limit of the thickness of the epitaxial layer 2 may be determined in consideration of the shaved amount due to thermal oxidation up to the formation of the gate oxide film, the heat treatment conditions, and the like. Appropriate.

The impurity (boron) concentration of the epitaxial layer 2 is almost the same as that of the CZ wafer 1 (about 1.5 × 10 5).
¹⁵ atoms / cm ³ ) or less, but MISFET
If it is lower by about one digit than the channel concentration (for example, 1 × 10 ¹⁷ atoms / cm ³ ), that is, 3 × 10 ¹⁶ atoms / cm ³ or less, there is no problem.

FIG. 3 shows the initial oxygen concentration [O
6 is a graph showing the relationship between i] and the gate oxide film defect density. The horizontal axis is the initial oxygen concentration (ppma (JEIDA conversion)),
The vertical axis indicates the gate oxide film defect density (relative value). Assuming that the gate oxide film defect density at an initial oxygen concentration of 18 ppma (in JEIDA) is 1, the gate oxide film defect density decreases as the oxygen concentration decreases. Therefore, in the case of the CZ wafer 1, the initial oxygen concentration is set to 17 ppma in order to reduce the defect density of the gate oxide film formed on the surface thereof.
(JEIDA conversion) It is necessary to set below.

FIG. 4 is a graph showing the relationship between the thickness of the epitaxial layer 2 and the defect density of the gate oxide film. The abscissa indicates the thickness (μm) of the epitaxial layer 2 and the ordinate indicates the gate oxide defect density (relative value with respect to the CZ wafer). The initial oxygen concentration of the epitaxial layer 2 is 15, 16.5, 1
It is 9, 20 ppma (in JEIDA conversion).

From this graph, it is found that the gate oxide film defect density does not depend on the initial oxygen concentration of the CZ wafer 1 and decreases as the thickness of the epitaxial layer 2 increases.
It can be seen that when the thickness is 3 μm or more, the thickness becomes about 1/30 of that of the CZ wafer 1. That is, the epitaxial wafer 2EW
In the case of, the initial oxygen concentration is 17 ppma (JEIDA conversion)
A higher density does not increase the gate oxide defect density. Therefore, the thickness of the epitaxial layer 2 is at least
It is appropriate that the thickness be 0.3 μm or more.

From the above, the epitaxial wafer 2
In EW, the initial oxygen concentration was 17 ppma (JEIDA
Even if it is higher than (converted), the breakdown voltage of the gate oxide film on the surface of the epitaxial layer 2 does not deteriorate due to the springing of oxygen from the CZ wafer 1 due to the heat treatment.

Next, the relationship between the thickness of the epitaxial layer remaining after the formation of the oxide film and the gate oxide film characteristics (GOI) was examined. FIG. 5 shows that the thickness of the epitaxial layer 2 is constant (1
μm), the epitaxial layer 2 is intentionally shaved from the surface by forming a predetermined oxide film, and the remaining film thickness of the epitaxial layer 2 is set to 0.1 μm (△ in the figure) and 0 μm (□ in the figure).
3 shows the relationship between the breakdown voltage and the cumulative failure rate in the case of ()). The data for the epitaxial layer 2 having a thickness of 1 μm is also shown (indicated by a circle in the figure).

From this graph, when the epitaxial layer 2 disappears due to oxidation (indicated by □ in the figure), the gate oxide film characteristic (GOI) is changed to the 1 μm-thick epitaxial layer 2 (indicated by ○ in the figure). It turned out that it deteriorated compared with. Further, even when the remaining film thickness of the epitaxial layer 2 is 0.1 μm (indicated by a mark in the figure), it is deteriorated as compared with the epitaxial layer 2 having a film thickness of 1 μm. This result indicates that the epitaxial layer 2
When the film thickness of the gate oxide film becomes 0.3 μm or more, the gate oxide film characteristics (G
OI) is improved (if the thickness of the epitaxial layer 2 is 0.3 μm or more, the epitaxial layer 2 remains until the gate oxide film forming step).

FIG. 6 shows the C of the epitaxial wafer 2EW.
Micro defect density (BMD; Bulk Mic) in Z wafer 1
7 is a graph showing the relationship between the initial oxygen concentration and the initial oxygen concentration. The horizontal axis is the initial oxygen concentration (ppma (JEIDA conversion)),
The vertical axis indicates the BMD concentration (pieces / cm ³ ). For comparison, a CZ wafer 1 (white circle in the figure) having the same oxygen concentration as that of the epitaxial wafer 2EW (black circle in the figure) is also shown.

Observation of the density of minute defects was carried out using JEIDA-24.
"Standard Specification for Visual Inspection of Silicon Mirror Wafer"
(Established in March 1974). In order to increase observation accuracy, annealing for oxygen precipitation (in a nitrogen atmosphere,
After 800 ° C., 4 hours + 1000 ° C., 16 hours, the wafer is cleaved and the cleaved surface is etched with an etching solution (K ₂ Cr).
₍ 11 g of ₂ O ₇ +500 ml of HF + 50 ml of H ₂ O ₂ ) for 1 minute and etched at 1 μm. Thereafter, the vicinity of about 250 μm in the depth direction of the wafer was observed with a microscope to measure the minute defect density.

Although depending on the contamination level of the production line,
Usually, the BMD density becomes less than 1 × 10 ⁶ cells / cm ^3, the gate breakdown voltage is deteriorated by lowering the gettering capability, while when it exceeds 1 × 10 ⁹ pieces / cm ^3, the heat treatment step by degradation of the crystal strength As a result, the wafer is easily warped.

In the CZ wafer 1, as the BMD concentration increases, the gate breakdown voltage deteriorates (that is, as shown in FIG. 3, the initial oxygen concentration in the CZ wafer 1 is 14 ppma
(The gate breakdown voltage is degraded by JEIDA conversion), but p /
In the case of the p epitaxial wafer 2EW, the BMD concentration of the epitaxial layer 2 does not increase, and the BMD concentration range focusing on the gettering ability of the CZ wafer 1 as a supporting substrate is 1 × 10 ⁶ to 1 × 10 ⁹ / cm. It can be said that ³ is desirable. That is, in the epitaxial wafer 2EW, even in this BMD concentration range, as shown in FIG. 4, the gate breakdown voltage does not deteriorate and the gate oxide film characteristics (GO
I) is improved.

FIG. 7 shows an OSDA apparatus (Optical Shallow Defect Analyz) which can observe the density of minute defects having a size of 20 nm or more as the integration density up to 5 μm in the depth direction of the wafer.
5 is a graph showing the relationship between the density of micro defects and the initial oxygen concentration observed using er). The horizontal axis is the initial oxygen concentration (ppma
(JEIDA conversion)), the vertical axis is the micro defect density (pieces / cm ³ )
It is. Hereinafter, a micro defect density observed using an OSDA apparatus is referred to as an OSDA defect, and the density is referred to as an OSDA defect density.

Although depending on the contamination level of the production line,
Usually, in the p / p epitaxial wafer 2EW,
If the OSDA defect density is 6 × 10 ⁶ / cm ³ or more, the gate breakdown voltage does not deteriorate due to contamination, but the upper limit is defined by the warpage of the wafer.

Thus, the OSDA defect density range of the p / p epitaxial wafer 2EW is from 6 × 10 ⁶ to 2 × 1
It can be said that 0 ⁸ pieces / cm ³ is desirable. That is, in the epitaxial wafer 2EW, even in this OSDA defect density range, as shown in FIG.
Gate oxide film properties (GOI) are improved.

The outline of the OSDA device is shown in FIG.
This will be briefly described with reference to FIG.

As shown in the figure, the OSDA apparatus sequentially irradiates each region with laser light of two wavelengths (532 nm and 810 nm) while rotating the wafer, and analyzes how light is scattered. The light is scattered only at the defective portion, and is attenuated and absorbed by the wafer in the other defect-free portions. The scattered light is detected by two types of detectors, one for 532 nm and the other for 810 nm, and by analyzing those data, the plane distribution, depth and size of the defect can be identified. As a result, minute defects (OSDA defects) having a size of 20 nm or more can be observed up to 5 μm in the depth direction of the wafer.

The inventor uses the OSDA device to perform CZ
OSDA of wafer 1 and epitaxial wafer 2EW
Inspection of the defects revealed that the epitaxial wafer 2EW had less OSDA defects than the CZ wafer 1, as shown in FIG.

As for the OSDA device, for example, “E
xtended Abstract of the 1996 International Confere
nce on Solid State Devices and Material, 1996, "p1
51.

FIG. 9 is a graph showing the relationship between the initial oxygen concentration and the amount of precipitated oxygen. The sample wafers are the CZ wafer 1 and the epitaxial wafer 2EW. In order to promote oxygen precipitation, annealing for oxygen precipitation (in a nitrogen atmosphere, 8
(00 ° C., 4 hours + 1000 ° C., 16 hours). The amount of oxygen precipitation was determined by a Fourier transform infrared spectrophotometer as the difference between the oxygen concentrations before and after the heat treatment. As shown, C
In the Z wafer 1, the amount of precipitated oxygen increases as the initial oxygen concentration increases, but slightly in the epitaxial wafer 2 EW.

This graph also shows the amount of precipitated oxygen on the CZ wafer 1 that has been subjected to the heat treatment up to the preheating (preheating for removing the natural oxide film) in the epitaxial growth step. It can be seen that oxygen precipitation is suppressed by heat treatment up to preheating. This is because the glow-in defect in the CZ wafer 1 dissolves and disappears due to the high-temperature heat treatment until the pre-heating,
It is considered that this is because oxygen precipitation is suppressed.

FIG. 10 shows that the oxygen concentration in the wafer is 1000
SIMS (Secondary Ion M
4 is a graph showing the results of analysis (ass Spectroscopy).
The thickness of the epitaxial wafer 2EW used here is 1 μm.
m. For comparison, this epitaxial wafer 2E
The CZ wafer 1 having the same oxygen concentration as W is also shown.

As shown in the figure, before the heat treatment, the oxygen concentration of the epitaxial wafer 2EW is lower than that of the CZ wafer 1, but the oxygen concentration distribution of the epitaxial wafer 2EW and the CZ wafer 1 can be obtained only by performing the heat treatment at 1000 ° C. for 30 minutes. There is no difference. Therefore, CZ during heat treatment during the manufacturing process
Although oxygen flows from the wafer 1 to the epitaxial wafer 2EW, it can be seen that the presence of oxygen in the epitaxial wafer 2EW itself does not deteriorate the gate oxide film breakdown voltage.

FIG. 11 shows an epitaxial wafer 2EW (marked with a circle: inclined wafer) of the present embodiment having the above-described inclination angle and an epitaxial wafer (△) having an inclination angle of 0.
4 is a graph showing the relationship between the impurity dose amount of a mark (just wafer) and the dislocation density due to oxidation-induced stacking fault (OSF). The horizontal axis is the surface of the epitaxial layer 2 (MISFET).
The dose amount of the impurity (boron) ion-implanted into the formation region), and the vertical axis indicates the OSF dislocation density in this region.

As shown in the figure, a significant difference was found in the dislocation density between the inclined wafer and the just wafer. In other words, it has been found that the inclined wafer suppresses OSF defects in the MISFET formation region as compared with the just wafer, and thus has a high gettering effect on heavy metal, which is a factor of OSF generation.

As described above, the (100) plane is set as the main surface, and any one of the [010] directions in the (100) plane is
2.35 ° from one axis and 2.
According to epitaxial wafer 2EW of the present embodiment having an inclination angle perpendicular to the crystal axis within the range of 5 ° to 15 °, the gate oxide film formed on the surface of epitaxial layer 2 in a later step is formed. The characteristic (GOI) improves,
The gettering effect on heavy metal contamination is improved.

The impurity (boron) concentration of the epitaxial layer 2 is substantially the same as that of the CZ wafer 1 (about 1.5 × 10 ^15).
atoms / cm ³ ) or less, and according to the epitaxial wafer 2EW of the present embodiment in which the thickness of the epitaxial layer 2 is about 0.3 μm to 5 μm, the manufacturing cost can be reduced.

That is, according to the present embodiment, the epitaxial wafer 2EW with improved gate oxide film characteristics (GOI) and improved gettering effect against heavy metal contamination can be realized at low cost.

Epitaxial wafer 2E of the present embodiment
In order to further improve the gettering effect of W, the heat treatment (see FIG. 1 (f)) for erasing oxygen donors generated by oxygen mixed during pulling of the ingot 100 is performed for a longer time (for example, 700 ° C., 3 ° C.). Time) is effective. In this case, oxygen precipitation is promoted by the subsequent high-temperature heat treatment, so that p with a low impurity concentration is used.
Even with the / p epitaxial wafer 2EW, the gettering effect is improved. Here, the heat treatment temperature for erasing the oxygen donor was set at 700 ° C.
0 ° C.), an improvement in the gettering effect can be expected.

FIG. 12 is a sectional view of a principal part of a semiconductor integrated circuit device in which a complementary MISFET (CMOSFET) is formed on the main surface of the epitaxial layer 2.

The epitaxial layer 2 has an n-type well 3n and a p-type well 3p. Although not particularly limited, each of the n-type well 3n and the p-type well 3p is
In order to improve the latch-up resistance of the CMOS, they are separated from each other via an element isolation groove 4 formed in the epitaxial layer 2.

In the n-type well 3n formed in the epitaxial layer 2, a p-channel MISFET Qp is formed.
An n-channel MISFET Qn is formed in the p-type well 3p. The p-channel type MISFET Qp mainly includes a pair of p-type semiconductor regions (source and drain regions) 6 and 6 formed in an n-type well 3n and an n-type well 3
A gate oxide film 7 formed on the surface of n and a gate electrode 8 formed on the gate oxide film 7 are formed. The n-channel MISFET Qn mainly includes a pair of n-type semiconductor regions (source and drain regions) 9 and 9 formed in the p-type well 3p, a gate oxide film 7 formed on the surface of the p-type well 3p, A gate electrode 8 formed on the gate oxide film 7. The gate electrode 8 is composed of, for example, a polycide film in which a W (tungsten) silicide film is laminated on an n-type polycrystalline silicon film. For example, a silicon oxide film 10 is formed on the gate electrode 8, and a sidewall spacer 11 made of a silicon oxide film is formed on a side wall. The silicon oxide film 10 and the sidewall spacer 11
The gate electrode 8 and the wirings (13a-1
3d).

First-layer wirings 13 a to 13 d are formed above the p-channel MISFET Qp and the n-channel MISFET Qn with a silicon oxide film 12 interposed therebetween. The wiring 13a is connected to a p-channel MISFE through a connection hole 14a formed in the silicon oxide film 12.
Electrically connected to one p-type semiconductor region 6 of TQp,
The wiring 13b is connected to the p-channel type MI through the connection hole 14b.
It is electrically connected to the other p-type semiconductor region 6 of the SFET Qp. The wiring 13c is electrically connected to one n-type semiconductor region 9 of the n-channel MISFET Qn through the connection hole 14c, and the wiring 13d is connected to the connection hole 14d.
And is electrically connected to the other n-type semiconductor region 9 of the n-channel type MISFET Qn. Wirings 13a-1
3d is made of, for example, an Al (aluminum) alloy to which Si (silicon) and Cu (copper) are added.

Second-layer wirings 16a and 16b are formed above the first-layer wirings 13a to 13d via an interlayer insulating film 15 made of a silicon oxide film or the like. The wiring 16a has a connection hole 17a formed in the interlayer insulating film 15.
The wiring 16b is electrically connected to the first layer wiring 13b through the connection hole 17b.
c and is electrically connected. The wirings 16a and 16b are
For example, it is composed of an Al alloy to which Si and Cu are added.

A passivation film 18 composed of a laminated film of a silicon oxide film and a silicon nitride film is formed on the wirings 16a and 16b.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

First, as shown in FIG. 13, an epitaxial wafer (see FIG. 2) in which a p-type epitaxial layer 2 is formed on a CZ wafer 1 made of p-type single crystal silicon is prepared. As described above, the CZ wafer 1 and the epitaxial layer 2 have the (100) plane as a main surface, and within the (100) plane, within 35 ° from any one axis in the [010] direction, and 2.5 from crystal axis
It has a tilt angle that is perpendicular to the crystal axis within the range of 15 ° to 15 °. The thickness of the epitaxial layer 2 is, for example, 1 μm.
m, and the impurity (boron) concentration is about 1.5 × 10 ¹⁵ atoms / cm ^3, which is almost the same as that of the CZ wafer 1.

Next, as shown in FIG. 14, a silicon oxide film 22 (film thickness = about 40 nm) and a silicon nitride film 23 (film thickness = about 50 nm) are formed on the epitaxial layer 2 by CVD (chemical vapor deposition). Then, after patterning the silicon nitride film 23 using a photoresist as a mask, the silicon oxide film 22 and the epitaxial layer 2 are sequentially etched using the silicon nitride film 23 as a mask to form a groove 4a. Subsequently, a thermal oxidation treatment at 900 to 1150 ° C. is performed to form a silicon oxide film (not shown) on the inner wall of the groove 4a.

Next, as shown in FIG. 15, a silicon oxide film 24 is deposited on the epitaxial layer 2 by a CVD method and subjected to a heat treatment at about 1000 ° C. to densify the film. The silicon oxide film 24 is flattened by polishing and is left inside the groove 4a to form the element isolation groove 4.

Next, as shown in FIG. 16, an n-type impurity (eg, P) is ion-implanted into a part of the surface of the epitaxial layer 2 and a p-type impurity (eg, B) is ion-implanted into another part. Thereafter, a heat treatment for elongating impurities is performed 12 times.
The n-type well 3n and the p-type well 3p are formed by thermally diffusing impurities into the inside of the epitaxial layer 2 at a temperature of 00 ° C. for several hours. The impurity concentration of the n-type well 3n and the p-type well 3p is, for example, 6 × 10 ¹⁶ atoms / cm ³ .

FIG. 17 shows an impurity concentration profile of a well region formed by ion-implanting impurities from the surface of epitaxial layer 2 (here, the impurity concentration profile of p-type well 3p is representatively shown). As shown, the impurity concentration in the well region monotonously decreases from the surface of the epitaxial layer 2 in the depth direction, and the bottom of the well extends to a part of the CZ wafer 1.

At this time, n-type impurities and p-type impurities are ion-implanted at a high accelerating voltage, so that the n-type well 3n and the p-type well 3p are retrograde so that the internal impurity concentration is higher than the surface impurity concentration. It may be constituted by a structure. By doing so, the latch-up resistance of the CMOS can be further improved.

Next, as shown in FIG. 18, after the epitaxial layer 2 is thermally oxidized to form a gate oxide film 7 on the surface of the active region, a gate electrode 8 is formed on the gate oxide film 7. Since the gate oxide film 7 is formed on the surface of the epitaxial layer 2 having a low OSF dislocation density, the reliability of the film is high. The gate electrode 8 is formed by sequentially depositing an n-type polycrystalline silicon film, a W (tungsten) silicide film and a silicon oxide film 10 on the epitaxial layer 2 on which the gate oxide film 7 is formed by a CVD method, using a photoresist as a mask. These films are patterned and formed by the dry etching. The gate electrode 8 is composed of a polycide film in which a W silicide film is laminated on an n-type polycrystalline silicon film. The gate electrode 8 may be formed of a single-layer film of n-type polycrystalline silicon or an n-type polycrystalline silicon film, a three-layer film in which a TiN (titanium nitride film), a W film is laminated, or the like.

Next, as shown in FIG.
N-type impurities are ion-implanted into the p-type wells 3p on both sides of the n-type well to form n-type semiconductor regions 9 and 9 (source and drain). , 6 (source, drain) to form an n-channel MISFET Qn and a p-channel MISFET Qp. The n-type semiconductor regions 9 are made of, for example, arsenic (As) of about 10 ¹⁵ atoms / cm ^2.
Is formed by ion implantation, and p-type semiconductor regions 6 and 6 are formed.
Is formed by ion-implanting, for example, BF ₂ of about 10 ¹⁵ atoms / cm ² . After that, the silicon oxide film deposited on the epitaxial layer 2 by the CVD method is processed by anisotropic etching to form the sidewall spacer 11 on the side wall of the gate electrode 8. Source and drain of n-channel MISFET Qn and p-channel MISFET Qp
The source and drain of the
usedDrain) Structure or LDD (Lightly Doped Drain)
It can also be constituted by a structure.

Next, as shown in FIG. 20, an n-channel MISFET Qn and a p-channel MISFET Qp
A silicon oxide film 12 is deposited on the epitaxial layer 2 on which the silicon oxide film 12 is formed by CVD, and a part of the silicon oxide film 12 is opened by dry etching using a photoresist as a mask, thereby forming a p-type MISFET Qp. Connection holes 14a and 14b are formed above the type semiconductor regions 6 and 6, and connection holes 14c and 14d are formed above the n-type semiconductor regions 9 and 9 of the n-channel MISFET Qn.

Next, as shown in FIG.
After depositing an Al alloy film on the silicon oxide film 12 on which the layers .about.14d have been formed by, for example, a sputtering method, the Al alloy film is patterned by dry etching using a photoresist as a mask, thereby forming a p-channel type MISFE.
Wirings 13a and 13b electrically connected to p-type semiconductor regions 6 and 6 of TQp, and n-channel MISFET Q
Wiring 1 electrically connected to n n-type semiconductor regions 9
3c and 13d are formed.

Next, as shown in FIG.
A silicon oxide film or the like is deposited on the upper part of 13d by a CVD method to form an interlayer insulating film 15, and a part of the interlayer insulating film 15 is opened by dry etching using a photoresist as a mask, thereby forming the wiring 13b. A connection hole 17a is formed in the upper part, and a connection hole 17b is formed in the upper part of the wiring 13c.
Subsequently, after an Al alloy film was deposited on the interlayer insulating film 15 by, for example, a sputtering method, the Al alloy film was patterned by dry etching using a photoresist as a mask, thereby being electrically connected to the wiring 13b. A wiring 16b electrically connected to the wiring 16a and the wiring 13c is formed.

Thereafter, the CV is applied to the upper portions of the wirings 16a and 16b.
By depositing a silicon oxide film and a silicon nitride film by the method D to form the passivation film 18, the semiconductor integrated circuit device having the complementary MISFET of the first embodiment is completed.

According to the present embodiment, the breakdown voltage and film quality of gate oxide film 7 can be improved, and the reliability of semiconductor integrated circuit device having complementary MISFET can be improved by using epitaxial wafer 2EW with improved gettering ability. Properties and manufacturing yield can be improved.

According to the present embodiment, since the epitaxial wafer 2EW can be manufactured at low cost, the manufacturing cost of a semiconductor integrated circuit device having a complementary MISFET can be reduced.

In the present embodiment, p / type epitaxial layer is grown on the surface of p-type CZ wafer 1 by p /
Although the p epitaxial wafer 2EW was used, the n-type C
An n-type epitaxial layer grown on the surface of a Z wafer
/ N epitaxial wafer.

(Second Embodiment) FIG. 23 is a cross-sectional view of a principal part showing a semiconductor integrated circuit device of a second embodiment.

The semiconductor integrated circuit device according to the second embodiment is
A DRAM (Dynamic Random Access Memory) is formed on the main surface of the epitaxial wafer 2EW of the first embodiment.

A part of the p-type well 3p formed in the epitaxial layer 2 includes n forming a memory cell of the DRAM.
A channel-type memory cell selecting MISFET Qs is formed, and an n-channel type
The SFET Qn is formed. A p-channel MISFET Qp of a peripheral circuit is formed in the n-type well 3n formed in the epitaxial layer 2. MISFET Qt for memory cell selection, n channel type MISFET Q
The n- and p-channel MISFETs Qp are provided on the surface of the epitaxial layer 2 with LOCOS (Local Oxidation of Silicon).
are separated from each other by a field oxide film 28 formed by the (con) method.

The memory cell selecting MISFET Qt and the n-channel MISFET Qn are mainly composed of a p-type well 3p
A gate oxide film 7 formed on the surface of the p-type well 3p; a gate electrode 8 formed on the gate oxide film 7; It is composed of p-channel type MISFE
TQp is mainly composed of a pair of p-type semiconductor regions (source and drain) 6 and 6 formed in the n-type well 3n, a gate oxide film 7 formed on the surface of the n-type well 3n, and And the gate electrode 8 formed on the substrate. The gate electrode 8 is formed by forming W on the n-type polycrystalline silicon film.
It is composed of a polycide film formed by stacking (tungsten) silicide films.

The bit lines BL ₁ and BL ₂ are formed above the memory cell selecting MISFET Qt, and the p-channel MISFET Qp and the n-channel MI
The first layer wiring 13 is provided on each of the SFETs Qn.
e, 13f are formed. Bit lines BL ₁ , BL ₂
The lower electrode 25, the capacitor insulating film 26 and the upper electrode 2
7 is formed, and further thereon, second layer wirings 16c to 16f are formed.

According to the present embodiment, the reliability and manufacturing yield of the DRAM can be improved by using epitaxial wafer 2EW having improved withstand voltage and film quality of gate oxide film 7 and improved gettering ability. Can be.

According to the present embodiment, the epitaxial wafer 2EW can be manufactured at low cost.
The manufacturing cost of the RAM can be reduced.

(Embodiment 3) FIG. 24 is a cross-sectional view of a principal part showing a semiconductor integrated circuit device of Embodiment 3 of the present invention.

The semiconductor integrated circuit device according to the third embodiment is
The flash memory is formed on the main surface of the epitaxial wafer 2EW of the first embodiment. A part of the p-type well 3p formed in the epitaxial layer 2 has an n-channel type MI that constitutes a memory cell of the flash memory.
An SFET Qm and an n-channel MISFET Qt constituting a transfer MISFET are formed, and an n-channel MISFET Qn of a peripheral circuit is formed in another part. The memory cell is of an AND type, and its drain region is provided with a transfer MISFET (n-channel MISF).
ETQtr) is electrically connected to the data line 13i via the source and drain paths.

Further, n formed in the epitaxial layer 2
In the well 3n, a p-channel MISFET of a peripheral circuit is provided.
Qp is formed. n-channel type MISFETQ
The m and n channel MISFET Qn and the p channel MISFET Qp
They are separated from each other by a field oxide film 28 formed by the COS method.

Memory cell n-channel MISFET Q
m denotes a pair of n-type semiconductor regions (source, drain) 9 and 9 formed mainly in the p-type well 3p, a gate oxide film 7 formed on the surface of the p-type well 3p, and A gate electrode (floating gate) 8 is formed, a second gate oxide film 29 is formed on the gate electrode 8, and a control gate 30 is formed on the second gate oxide film 29. The n-channel MISFET Qn of the peripheral circuit is mainly composed of a p-type well 3p
A gate oxide film 7 formed on the surface of the p-type well 3p; a gate electrode 8 formed on the gate oxide film 7; It is composed of p-channel type MISFE
TQp is mainly composed of a pair of p-type semiconductor regions (source and drain) 6 and 6 formed in the n-type well 3n, a gate oxide film 7 formed on the surface of the n-type well 3n, and And the gate electrode 8 formed on the substrate.

Memory cell n-channel MISFET Q
Above m, first-layer wirings 13g to 13i are formed, and further thereon, a second-layer wiring 16g is formed. Peripheral circuit p-channel MISFET
A first layer wiring 13j is formed above each of the Qp and the n-channel MISFET Qn, and a second layer wiring 16h is further formed thereon.

According to the present embodiment, the breakdown voltage and film quality of gate oxide film 7 can be improved, and the reliability and manufacturing yield of the flash memory can be improved by using epitaxial wafer 2EW with improved gettering ability. be able to.

According to the present embodiment, since the epitaxial wafer 2EW can be realized at low cost, the manufacturing cost of the flash memory can be reduced.

(Embodiment 4) FIG. 25 is a cross-sectional view showing a main part of a semiconductor integrated circuit device according to Embodiment 4 of the present invention.

The semiconductor integrated circuit device of the fourth embodiment is
An SRAM (Static Random Access Memory) is formed on the main surface of the epitaxial wafer 2EW of the first embodiment. The memory cell of this SRAM is formed in an active region surrounded by a field insulating film 28 on the main surface of the epitaxial layer 2. 6 that constitutes a memory cell
Among the MISFETs, a pair of n-channel type driving MISFETs and a pair of transfer MISFETs are formed in the active region of the p-type well 3p, and a pair of p-channel type loading MISFETs are driven. MISF for
It is formed above the ET.

A pair of transfer MISFETs are formed on the n ⁺ -type semiconductor region 38 and the n ⁻ -type semiconductor region 45 (source and drain) formed in the active region of the p-type well 3n, and formed on the surface of the active region. A gate oxide film 41 made of a silicon oxide film and a gate electrode 42 made of polycide formed on the gate oxide film 41 are formed. The gate electrode 42 of the transfer MISFET is formed integrally with the word line WL.

The pair of driving MISFETs are formed on the surface of the active region of the n ⁺ -type semiconductor region 38 and the n ⁻ -type semiconductor region 37 (source and drain) formed in the active region of the p-type well 3n. It is composed of a gate oxide film 35 and a gate electrode 36 made of polycrystalline silicon formed on the gate oxide film 35.

The pair of load MISFETs includes a driving MI
A gate electrode 47 made of polycrystalline silicon formed on the SFET; a gate oxide film 46 formed on the gate electrode 47; and a p-type made of polycrystalline silicon formed on the gate oxide film 46 Semiconductor region 48
(Source, drain).

Reference numeral 34 denotes a p-type channel stopper layer, Vcc denotes a power supply line, Vss denotes a GND line, DL denotes a data line,
49 to 51 are first-layer metal wirings.

According to the present embodiment, gate oxide film 3
By using the epitaxial wafer 2EW having improved breakdown voltage and film quality of 5, 41 and improved gettering ability, it is possible to reduce the data retention failure of the SRAM and to improve the reliability and the production yield.

According to the present embodiment, the epitaxial wafer 2EW can be realized at low cost.
The manufacturing cost of the RAM can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof. Needless to say,

[0130]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the (100) plane is defined as the principal plane, and within that plane, 35 ° from any one axis in the [010] direction, and 2.5 ° from the 100 crystal axis.
By growing the epitaxial layer on the main surface of the CZ wafer inclined so as to be perpendicular to the crystal axis within the range of 15 °, OSF defects on the surface of the epitaxial layer (MISFET formation region) are suppressed, and heavy metal Gettering effect is improved.

According to the present invention, the MISFET is formed on the main surface of the epitaxial wafer to form the MISFET.
Gate Oxide integrity (GOI) of T
Can be improved.

According to the present invention, the manufacturing cost of the epitaxial wafer can be reduced by lowering the impurity concentration of the CZ wafer and the epitaxial layer. In addition, a step of forming a silicon oxide film on the back surface of the CZ wafer is not required for the purpose of preventing impurities from diffusing out and auto-doping from the back surface of the CZ wafer when forming the epitaxial layer. Furthermore, since the amount of impurities from the CZ wafer is reduced, the thickness of the epitaxial layer can be reduced, and the fluctuation of the impurity concentration profile of wells and channel regions formed in the epitaxial layer can be prevented.

According to the present invention, the manufacturing cost of the epitaxial wafer can be reduced by forming the epitaxial layer thin. In addition, by forming the epitaxial layer thinly, it is possible to achieve low-temperature growth because the cost is commensurate even at a low growth rate. As a result, since slip-free can be realized, warping of the wafer due to heat during epitaxial growth can be prevented even when applied to a large-diameter wafer of 8 inches or more.

According to the present invention, there is no need to perform a process for controlling the amount of oxygen dissolved from the quartz crucible during the lifting of the ingot.

[Brief description of the drawings]

FIGS. 1A to 1G are explanatory diagrams showing a method for manufacturing a CZ wafer according to a first embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the epitaxial wafer according to the first embodiment of the present invention;

FIG. 3 is a graph showing a relationship between an initial oxygen concentration of a CZ wafer and a gate oxide film defect density.

FIG. 4 is a graph showing a relationship between a thickness of an epitaxial layer formed on a CZ wafer and a defect density of a gate oxide film.

FIG. 5 is a graph showing a relationship between a breakdown voltage of an oxide film formed on an epitaxial wafer and a cumulative failure rate.

FIG. 6 is a graph showing the relationship between the initial oxygen concentration of a wafer and the density of minute defects (BMD).

FIG. 7 is a graph showing the relationship between the initial oxygen concentration of a wafer and the density of minute defects observed using an OSDA apparatus.

FIG. 8 is a schematic explanatory view showing an optical system of the OSDA device.

FIG. 9 is a graph showing the relationship between the initial oxygen concentration of a wafer and the amount of precipitated oxygen.

FIG. 10 is a graph in which the relationship between the depth from the wafer surface and the oxygen concentration is analyzed by SIMS before and after the heat treatment.

FIG. 11 shows an impurity dose amount and O of an epitaxial wafer.
4 is a graph showing a relationship with SF dislocation density.

FIG. 12 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 17 is a graph showing an impurity concentration profile of a well region formed by ion-implanting impurities from the surface of an epitaxial layer.

FIG. 18 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 19 is an essential part cross sectional view showing the method for manufacturing the semiconductor integrated circuit device of the first embodiment of the present invention.

FIG. 20 is an essential part cross sectional view illustrating the method of manufacturing the semiconductor integrated circuit device of the first embodiment of the present invention;

FIG. 21 is an essential part cross sectional view showing the method of manufacturing the semiconductor integrated circuit device of the first embodiment of the present invention.

FIG. 22 is an essential part cross sectional view illustrating the method of manufacturing the semiconductor integrated circuit device of the first embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view showing a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 24 is a fragmentary cross-sectional view showing a semiconductor integrated circuit device according to a third embodiment of the present invention;

FIG. 25 is a fragmentary cross-sectional view showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon wafer (CZ wafer) 2 epitaxial layer 2 EW epitaxial wafer 3 n n-type well 3 pp p-type well 4 element isolation groove 4 a groove 6 p-type semiconductor region (source region, drain region) 7 gate oxide film 8 gate electrode 9 n-type semiconductor Region (source region, drain region) 10 silicon oxide film 11 side wall spacer 12 silicon oxide film 13a to 13j wiring 14a to 14d connection hole 15 interlayer insulating film 16a to 16h wiring 17a connection hole 17b connection hole 18 passivation film 20 silicon oxide film Reference Signs List 21 silicon oxide film 22 silicon oxide film 23 silicon nitride film 24 silicon oxide film 25 lower electrode 26 capacitance insulating film 27 upper electrode 28 field oxide film 29 second gate oxide film 30 control gate 34 channel stopper 35 a gate oxide film 36 gate electrode 37 n ^- -type semiconductor region 38 n ⁺ -type semiconductor region 41 a gate oxide film 42 gate electrode 45 n ^- -type semiconductor region 46 a gate oxide film 47 gate electrode 48 p-type semiconductor regions 49 to 51 metal wiring 100 Ingot BL ₁ , BL ₂ Bit line DL Data line C Information storage capacitor Qm n-channel MISFET Qn n-channel MISFET Qp p-channel MISFET Qs MISFET for memory cell selection Qt MISFET for transfer Vcc Power supply line Vss GND WL word line

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI C30B 29/06 504 C30B 29/06 504K 31/22 31/22 33/02 33/02 H01L 21/20 H01L 21/20 21 / 322 G 21/322 27/10 481 21/8244 21/205 27/11 27/10 381 27/10 481 681F 27/108 21/8242 // H01L 21/205 (72) Inventor Hirofumi Shimizu Kodaira, Tokyo 5-20-1, Kamizu Honcho Semiconductor Division, Hitachi, Ltd. (72) Inventor Norio Suzuki 5-20-1, Kamizu Honmachi, Kodaira City, Tokyo Semiconductor Division, Hitachi, Ltd. (72) Inventor Shigeaki Saito 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Inventor Yasushi Matsuda 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Semiconductors Within the business division (72) Inventor Yuji Sugino 5-2-1 Kamizuhoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Toshihide Tanaka 5-2-1 Kamimihoncho, Kodaira-shi, Tokyo Hitachi Semiconductor Co., Ltd.

Claims (24)

[Claims] 1. A semiconductor wafer in which an epitaxial layer is grown on a main surface of a single crystal silicon wafer manufactured by a Czochralski method, wherein the main surface of the single crystal silicon wafer is a (100) plane, and [01
A semiconductor wafer tilted within a range of 35 ° from any one of the 0] directions and perpendicular to a crystal axis within a range of 2.5 ° to 15 ° from the 100 crystal axis. . 2. The semiconductor wafer according to claim 1, wherein
A semiconductor wafer, wherein the thickness of the epitaxial layer is 0.3 to 5 μm. 3. The semiconductor wafer according to claim 1, wherein
The initial oxygen concentration of the single crystal silicon wafer is 17 ppma
(Equivalent to JEIDA) or more. 4. The semiconductor wafer according to claim 1, wherein
The single crystal silicon wafer is doped with impurities of a predetermined conductivity type in a concentration range of 1 × 10 ¹⁵ atoms / cm ³ or more and less than 3 × 10 ¹⁶ atoms / cm ³ , and the epitaxial layer includes A semiconductor wafer, wherein an impurity of the same conductivity type as the impurity is doped at a concentration substantially equal to or lower than the concentration range. 5. The semiconductor wafer according to claim 1, wherein
A semiconductor wafer, wherein the diameter of the single crystal silicon wafer is 8 inches or more. 6. A method for manufacturing a semiconductor wafer in which an epitaxial layer is grown on a main surface of a single crystal silicon wafer manufactured by a Czochralski method, wherein (a) (10)
0) A plane is a principal plane, and in that plane, is perpendicular to a crystal axis within a range of 35 ° from any one axis in the [010] direction and within a range of 2.5 ° to 15 ° from a 100 crystal axis. Preparing a single-crystal silicon wafer tilted so that
(B) growing an epitaxial layer on a main surface of the single crystal silicon wafer without forming an insulating film for preventing outward diffusion of impurities on at least the back surface of the single crystal silicon wafer. A method for manufacturing a semiconductor wafer, comprising: 7. The method for manufacturing a semiconductor wafer according to claim 6, wherein the single-crystal silicon wafer is 35 degrees away from any one axis in the [010] direction in the (100) plane.
The ingot is pulled up using a seed crystal that is tilted so as to be perpendicular to the crystal axis within a range of 2.5 ° to 15 ° from the 100 crystal axis within the range of 100 °, and then the ingot is pulled up. A method for manufacturing a semiconductor wafer, wherein the semiconductor wafer is formed by slicing on a plane orthogonal to a direction. 8. The method for manufacturing a semiconductor wafer according to claim 6, wherein the single crystal silicon wafer is pulled up using a seed crystal having a (100) plane as a main surface, and then the ingot is pulled up. The ingot is positioned within 35 ° from any one axis in the [010] direction and from 100 crystal axes.
2. A method for manufacturing a semiconductor wafer, comprising: slicing a wafer so that a (100) plane inclined so as to be perpendicular to a crystal axis within a range of 2.5 ° to 15 ° is exposed. 9. The method for manufacturing a semiconductor wafer according to claim 6, wherein the single crystal silicon wafer is heated to at least 600 ° C. after the step (a) and prior to the step (b). A method for erasing oxygen donors in the single crystal silicon wafer by annealing for at least 30 minutes or more. 10. The method of manufacturing a semiconductor wafer according to claim 6, wherein said epitaxial layer has a thickness of 0.3 to 5 μm. Method. 11. The method for manufacturing a semiconductor wafer according to claim 6, wherein said single-crystal silicon wafer contains 1 × 10 ¹⁵ impurities of a predetermined conductivity type when the ingot is pulled up. atoms / cm ³ or more, 3 × 10 ¹⁶ atom
doped in a concentration range of less than s / cm ^3, wherein the epitaxial layer, a semiconductor wafer, characterized by doping with substantially the same or less concentration with the concentration range of the impurity of the same conductivity type impurities during epitaxial growth Manufacturing method. 12. A semiconductor integrated circuit device comprising a gate oxide film of a MISFET formed by thermally oxidizing a surface of an epitaxial layer of the semiconductor wafer according to claim 1. Description: 13. The semiconductor integrated circuit device according to claim 12, wherein an impurity concentration of said epitaxial layer is lower than an impurity concentration of a channel region of said MISFET. 14. The semiconductor integrated circuit device according to claim 12, wherein a second conductivity type MISFET is formed in a first conductivity type well formed in a part of the epitaxial layer,
A semiconductor integrated circuit device, wherein a first conductivity type MISFET is formed in a second conductivity type well formed in another part of the epitaxial layer. 15. The semiconductor integrated circuit device according to claim 14, wherein said first conductivity type well and said second conductivity type well have a retrograde structure in which the impurity concentration inside is higher than the surface impurity concentration. A semiconductor integrated circuit device comprising: 16. The semiconductor integrated circuit device according to claim 14, wherein said first conductivity type well and said second conductivity type well are separated from each other by an element isolation groove formed in said epitaxial layer. A semiconductor integrated circuit device characterized by the above-mentioned. 17. The semiconductor integrated circuit device according to claim 14, 15 or 16, wherein a part of said first conductivity type well has a second conductivity type M constituting a memory cell of a DRAM.
A semiconductor integrated circuit, wherein an ISFET is formed, and a complementary MISFET forming a peripheral circuit of the DRAM is formed in another part of the first conductivity type well and the second conductivity type well. Circuit device. 18. The semiconductor integrated circuit device according to claim 14, 15 or 16, wherein a part of said first conductivity type well is provided with a second conductivity type MISFET constituting a part of a memory cell of an SRAM. The other part of the well of the first conductivity type and the well of the second conductivity type are formed with the SRAM.
A semiconductor integrated circuit device, wherein a complementary MISFET constituting a peripheral circuit of the above is formed. 19. The semiconductor integrated circuit device according to claim 14, 15 or 16, wherein a second conductivity type MISFET forming a memory cell of a nonvolatile memory is formed in a part of said first conductivity type well. And a complementary MISFET forming a peripheral circuit of the nonvolatile memory is formed in another part of the first conductivity type well and the second conductivity type well. apparatus. 20. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps (a) to (c): (a) a (100) plane as a main surface, and [0]
10] within 35 ° from any one axis in the direction
A step of preparing a single-crystal silicon wafer tilted so as to be perpendicular to a crystal axis within a range of 2.5 ° to 15 ° from the 100-crystal axis, and (b) at least the back surface of the single-crystal silicon wafer is free from impurities. Growing an epitaxial layer on the main surface of the single-crystal silicon wafer without forming an insulating film for preventing diffusion, (c) thermally oxidizing the surface of the epitaxial layer to form a gate oxide film of the MISFET Forming a. 21. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps (a) to (d): (a) a (100) plane as a main surface, and [0]
10] within 35 ° from any one axis in the direction
And preparing a single-crystal silicon wafer inclined so as to be perpendicular to a crystal axis within a range of 2.5 ° to 15 ° from the 100-crystal axis, (b) the single-crystal silicon wafer is at least 600 ° C. or higher, and A step of erasing oxygen donors in the single-crystal silicon wafer by annealing for at least 30 minutes or more; (c) an insulating film for preventing out-diffusion of impurities on at least the back surface of the single-crystal silicon wafer Growing an epitaxial layer on the main surface of the single-crystal silicon wafer without forming, and (d) forming a gate oxide film of a MISFET by thermally oxidizing the surface of the epitaxial layer. 22. The method for manufacturing a semiconductor integrated circuit device according to claim 20, wherein said epitaxial layer has a thickness of 0.3 to 5 μm. 23. The method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein said single-crystal silicon wafer contains impurities of a predetermined conductivity type at 1 × 10 ¹⁵ atoms / cm ³ at the time of lifting the ingot. 3 × 10 ¹⁶ atoms / cm
Doped with a concentration range of less than ^3, the epitaxial layer, the semiconductor integrated circuit device characterized by doping with substantially the same or less concentration with the concentration range of the impurity of the same conductivity type impurities during epitaxial growth Production method. 24. The method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein a first conductivity type impurity is ion-implanted into a part of said epitaxial layer. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a mold well; and ion-implanting a second conductivity type impurity into another part of the epitaxial layer to form a second conductivity type well.