CN103498196B - Method for fabricating silicon wafer - Google Patents

Method for fabricating silicon wafer Download PDF

Info

Publication number
CN103498196B
CN103498196B CN201310361966.3A CN201310361966A CN103498196B CN 103498196 B CN103498196 B CN 103498196B CN 201310361966 A CN201310361966 A CN 201310361966A CN 103498196 B CN103498196 B CN 103498196B
Authority
CN
China
Prior art keywords
temperature
silicon wafer
annealing
body regions
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310361966.3A
Other languages
Chinese (zh)
Other versions
CN103498196A (en
Inventor
朴正求
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aisi Kaifang Semiconductor Co ltd
Original Assignee
MagnaChip Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MagnaChip Semiconductor Ltd filed Critical MagnaChip Semiconductor Ltd
Publication of CN103498196A publication Critical patent/CN103498196A/en
Application granted granted Critical
Publication of CN103498196B publication Critical patent/CN103498196B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02469—Group 12/16 materials
    • H01L21/02472—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present invention provides a method for fabricating a silicon wafer, comprising: performing heat treatment to the silicon wafer to form a denuded zone and a bulk area in the silicon wafer; loading the heated silicon wafer to a heating device at a loading temperature; performing a first annealing process on the silicon wafer at a first temperature to supplementarily generate oxygen precipitate nuclei and oxygen precipitates in the bulk area; and performing a second annealing process on the silicon wafer at a second temperature higher than the first temperature to enlarge the oxygen precipitates in the bulk area, wherein the heat treatment to the silicon wafer is performed before the loading of the heated silicon wafer.

Description

The manufacture method of silicon wafer
The present invention is the denomination of invention submitted on September 28th, 2009 is the divisional application of the Chinese patent application 200910174525.6 of " silicon wafer and manufacture method thereof ".
Related application
The right of priority of No. 10-2008-0095462nd, the korean patent application that application claims on September 29th, 2008 and on January 16th, 2009 submit to Korean Intellectual Property Office and No. 10-2009-0003697, is incorporated to herein by reference.
Technical field
The present invention relates to semiconductor fabrication, more specifically relate to silicon wafer and manufacture method thereof.
Background technology
In most of high voltage devices of such as nmos pass transistor and PMOS transistor, usual trap is formed as the degree of depth from substrate surface about 5 microns to 10 microns.Ion implantation technology is only used to be difficult to realize the dopant profiles that the degree of depth is the trap of 5 microns to 10 microns.For this reason, high-temperature heat treatment should be used after ion implantation technology to implement dopant diffusion processes.
But, due to high-temperature heat treatment, oxygen precipitate can not be realized completely in silicon body (bulk).This causes at the lattice defect occurring such as ring-type dislocation for shallow trench isolation after the etch process of (STI) in a silicon substrate.
In addition, these lattice defects make good article rate reduce, and go back the electrical parameter characteristic of the leakage current homogeneity during the deterioration threshold voltage of such as high voltage device and the ready mode of static RAM (SRAM).In addition, during the foreign impurity matters test process that manufacture semiconducter device must be implemented, these lattice defects increase the time for checking and analyze a large amount of defect, thus cause the increase of the overall process time manufacturing semiconducter device.
Summary of the invention
One embodiment of the invention relate to a kind of silicon wafer, its generation of lattice defect by increasing gettering site fully to prevent the heat budget that causes due to subsequent high temperature thermal treatment process and causing.
Another embodiment of the invention relates to a kind of silicon wafer, and it has height and this bulky micro defect (BMD) density uniformly in body regions.
Another embodiment of the invention relates to a kind of method manufacturing silicon wafer, its generation of lattice defect by increasing gettering site fully to prevent the heat budget that causes due to subsequent high temperature thermal treatment process and causing.
Another embodiment of the invention relates to a kind of method manufacturing silicon wafer, and described silicon wafer has height and this bulky micro defect (BMD) density uniformly in body regions.
Another embodiment of the invention relates to a kind of semiconducter device by using manufactured by above-mentioned silicon wafer.
Another embodiment of the invention relates to a kind of by using the above-mentioned method for the manufacture of silicon wafer to manufacture the method for semiconducter device.
According to an aspect of the present invention, provide a kind of silicon wafer, it comprises: the first denuded zone (denuded zone), and it is formed as having the predetermined depth from silicon wafer end face; And body regions, it is formed between the first denuded zone and the back side of silicon wafer, wherein the first denuded zone is formed as having the degree of depth from end face about 20 microns to about 80 microns, and wherein in body regions the concentration of oxygen in whole body regions with 10% in change be uniformly distributed.
According to a further aspect in the invention, provide a kind of method manufacturing silicon wafer, it comprises: provide the silicon wafer with denuded zone and body regions; At a first temperature the first annealing process is implemented to this silicon wafer, produce oxygen precipitate core and oxygen precipitate to supplement in body regions; And at higher than the second temperature of the first temperature, the second annealing process is implemented to silicon wafer, to increase the oxygen precipitate in body regions.
According to another aspect of the invention, provide a kind of method manufacturing silicon wafer, it comprises: provide silicon wafer; Under loading temperature, silicon wafer is loaded into heating unit inside; Implement silicon wafer from the first heating process loading heating temperatures to the first temperature; The first annealing process implementing at a first temperature this silicon wafer is annealed is to produce oxygen precipitate; To implement silicon wafer from the first heating temperatures to higher than the second heating process of the second temperature of the first temperature; The second annealing process implementing at the second temperature silicon wafer is annealed is to increase oxygen precipitate for its density of increase; Implement process for cooling silicon wafer being cooled to unloading temperature from the second temperature; And silicon wafer self-heating apparatus is offloaded to outside.
Other object of the present invention and advantage are understood by following description, and become apparent with reference to embodiment of the present invention.And, it will be apparent to one skilled in the art that: objects and advantages of the present invention by claim means and combination realize.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the silicon wafer according to one embodiment of the invention;
Fig. 2 is the cross-sectional view that the method manufacturing silicon wafer according to first embodiment of the invention is described;
Fig. 3 is the cross-sectional view that the method manufacturing silicon wafer according to second embodiment of the invention is described;
Fig. 4 is the cross-sectional view that the method manufacturing silicon wafer according to third embodiment of the invention is described;
Fig. 5 is the cross-sectional view that the method manufacturing silicon wafer according to four embodiment of the invention is described;
Fig. 6 is the figure of the two step annealing process illustrated according to an embodiment of the invention;
Fig. 7 is the figure that bmd density is under various conditions described;
Fig. 8 is the figure of the degree of depth that denuded zone is under various conditions described;
Fig. 9 to Figure 12 illustrates the figure under various conditions according to the bmd density of oxygen concn and the degree of depth of denuded zone;
Figure 13 is the cross-sectional view of the silicon wafer according to comparative example manufacture;
Figure 14 is the cross-sectional view of the silicon wafer according to one embodiment of the invention manufacture;
Figure 15 illustrates the lattice defect figure of body regions in the silicon wafer manufactured according to comparative example;
Figure 16 illustrates the lattice defect figure of body regions in the silicon wafer that use two step annealing processs according to an embodiment of the invention manufacture;
Figure 17 A to Figure 17 D illustrates the method manufacturing semiconducter device according to an embodiment of the invention;
Figure 18 illustrates the assay of the lattice defect in the silicon wafer prepared according to comparative example;
Figure 19 is scanning electronic microscope (SEM) photo of the silicon wafer prepared by the oxidizing process of comparative example;
Figure 20 is the plane picture of the silicon wafer prepared by the oxidizing process of comparative example;
Figure 21 is that display carries out the micro image of bmd density analysis to silicon wafer prepared by the oxidizing process by comparative example;
Figure 22 illustrates the assay of the lattice defect of silicon wafer according to an embodiment of the invention;
Figure 23 is the plane picture of silicon wafer according to an embodiment of the invention;
Figure 24 is bmd density analysis is carried out in display Photomicrograph to silicon wafer according to an embodiment of the invention;
Figure 25 is for illustrating the comparative result figure of leakage current during static RAM (SRAM) ready mode; And
Figure 26 is the comparative result figure that good article rate is described.
Embodiment
By reference to the following description of the embodiment of described accompanying drawing afterwards, advantage of the present invention, feature and aspect can become apparent.
In the accompanying drawings, in order to clearly demonstrate, the size in layer and region is amplified.Also should be understood that it directly on another layer or substrate, also can exist middle layer when one deck (or film) is called as when another layer or substrate ' on '.In addition, should be understood that it directly under the other layer, also can exist one or more interposed layer when one deck is called as when another layer ' under '.In addition, also should be understood that when one deck is called as when two-layer ' between ', its can be two-layer between sole layer, also can there is one or more interposed layer.
The present invention is by using two step annealing processs to realize height in body regions and uniform bmd density to wafer silicon.As a result, the generation of lattice defect of the present invention by increasing gettering site (gettering site) fully and preventing the heat budget caused due to subsequent high temperature thermal treatment process from causing.
Fig. 1 is the cross-sectional view of the silicon wafer according to one embodiment of the invention.
As shown in Figure 1, silicon wafer 100 comprises: the first denuded zone DZ1, and the first denuded zone DZ1 is formed as having the predetermined depth from silicon wafer end face 101; And body regions BK, this body regions BK are formed between the first denuded zone DZ1 and the back side 102.Silicon wafer 100 also comprises the second denuded zone DZ2, and the second denuded zone DZ2 is formed as having the predetermined depth from this back side 102 towards the direction of this end face 101.
Forming that to have from end face 101 towards the first denuded zone DZ1 of the predetermined depth in the direction at the back side 102 be area free from defect (DFZ), there is not the lattice defect in such as room and dislocation in it.Preferably, the first denuded zone DZ1 is formed as having the degree of depth from end face 101 towards about 20 of the direction at the back side 102 microns to about 80 microns.
Second denuded zone DZ2 is also DFZ and is formed as having the degree of depth identical with the first denuded zone DZI degree of depth towards the direction of end face 101 from the back side 102, or according to the glossing to the back side 102, the second denuded zone DZ2 is formed as having the degree of depth of the degree of depth being less than the first denuded zone DZ1.That is when indistinguishably carrying out mirror polish to both the end face 101 of silicon wafer 100 and the back side 102, the first denuded zone DZI and the second denuded zone DZ2 is formed as having same depth.On the contrary, when not carrying out mirror polish to the back side 102 when carrying out mirror polish to end face 101, the second denuded zone DZ2 is formed as having the degree of depth being less than the first denuded zone DZI degree of depth, this is because form oxygen precipitate according to the roughness at the back side 102 near the back side 102.
The body regions BK formed between the first denuded zone DZI and the second denuded zone DZ2 comprises this bulky micro defect (BMD) 103.BMD103 keeps even in whole body regions.BMD103 comprises throw out and body stacking fault (bulk stacking fault).In addition, BMD103 in body regions BK can be controlled to have sufficient density, by this metal pollutant that spreads on the surface of silicon wafer via subsequent high temperature thermal treatment process or thermal process of gettering.BMD103 in body regions BK can keep density to be preferably about 1 × 10 5ea/cm 2to about 1 × 10 7ea/cm 2, be more preferably about 1 × 10 6ea/cm 2to 1 × 10 7ea/cm 2.In body regions BK, concentration (hereinafter referred to as ' oxygen concn ') and the oxygen precipitate of oxygen is closely related, preferred oxygen concn in whole body regions BK with 10% in change profile and remain about 10.5 ~ about 13PPMA (atom PPM).
Fig. 2 is the cross-sectional view that the method manufacturing silicon wafer according to first embodiment of the invention is described.
With reference to figure 2, prepare silicon wafer 200.Now, silicon wafer 200 can be naked wafer.Silicon wafer 200 can be formed according to following steps.First, after growing single-crystal silicon, silicon single crystal is cut into wafer shape.At enforcement etch process with etching through the surface of cut crystal or make after the side sphering of cut crystal, mirror polish is carried out to the end face 201 of silicon wafer 200 and the back side 202.Now, crystal growth vertical pulling method (Czochralski, CZ) is used to carry out growing single-crystal silicon.In addition, the mirror-polishing process to silicon wafer 200 can be implemented after subsequent thermal technique.
Implement the first thermal process to silicon wafer 200, the oxide elements 203 between the end face 201 of silicon wafer 200 and the back side 202 is internally spread.As a result, the first denuded zone DZ1 and the second denuded zone DZ2 and body regions BK is formed.First thermal process can be RTP (rapid hot technics) or uses the annealing process of furnace apparatus.Preferably, the first thermal process comprises RTP.
For the oxide elements 203 in the end face 201 of rapid diffusion silicon wafer 200 and the back side 202, use argon (Ar) gas, nitrogen (N 2) gas, ammonia (NH 3) gas or its combination at high temperature implement the first thermal process.When the first thermal process is RTP, be implement the first thermal process at the temperature of 1050 DEG C to about 1150 DEG C to last about 10 seconds to about 30 seconds in scope.When the first thermal process is annealing process, be implement the first thermal process at the temperature of 1050 DEG C to about 1150 DEG C to last about 100 minutes to about 300 minutes in scope.
Then, implement the second thermal process to silicon wafer 200, the oxide elements 203 in body regions BK is combined.As a result, oxygen precipitate core 204 is produced.Similar with the first thermal process, the second thermal process can be RTP or uses the annealing process of furnace apparatus.Second thermal process preferably includes RTP.
For being easy to form oxygen precipitate core 204, use argon (Ar) gas, nitrogen (N 2) gas, ammonia (NH 3) implement the second thermal process at gas or its temperature being combined in lower than the temperature of the first thermal process.When the second thermal process is RTP, be implement the second thermal process at the temperature of about 950 DEG C to about 1000 DEG C to last about 10 seconds to about 30 seconds in scope.When the second thermal process is annealing process, be implement the second thermal process at the temperature of about 950 DEG C to about 1000 DEG C to last about 100 minutes to about 200 minutes in scope.
Subsequently, after completing the second thermal process, the first annealing process is implemented to silicon wafer 200.Furnace apparatus is used to implement the first annealing process.By heating silicon wafer 200 under the preset temperature of the temperature lower than the second thermal process, supplementing the oxygen precipitate core 204 produced in body regions BK, meanwhile, producing oxygen precipitate 205A.Preferably, be implement the first annealing process at the temperature of about 750 DEG C to about 800 DEG C to last about 100 minutes to about 180 minutes in scope.In addition, at oxygen (O 2) atmosphere encloses lower enforcement first annealing process.
After completing the first annealing process, the second annealing process is implemented to silicon wafer 200.Also furnace apparatus is used to implement the second annealing process.By heating silicon wafer 200 under the preset temperature of the temperature higher than the first annealing process, increase oxygen precipitate 205A.As a result, the oxygen precipitate 205B through increasing is produced.Preferably, be implement the second annealing process at the temperature of about 1000 DEG C to about 1150 DEG C to last about 100 minutes to about 180 minutes in scope.In addition, at oxygen (O 2) atmosphere encloses lower enforcement second annealing process.
Hereinafter, the first annealing process and the second annealing process is described in detail.Hereinafter, the first annealing process and the second annealing process are called two step annealing processs.
Fig. 6 illustrates the graphic representation according to two step annealing processs of an embodiment of the present invention.
Referring to Fig. 6, use the annealing process of furnace apparatus to comprise and use oxygen (O 2) gas the first annealing process (II) of making silicon wafer 200 anneal at a first temperature and implement the second annealing process (IV) that silicon wafer 200 is annealed at higher than the second temperature of the first temperature.Implement the first annealing process (II) and the second annealing process (IV) all lasts about 100 minutes to about 180 minutes.The scope of the first temperature of the first annealing process (II) is about 750 DEG C to about 800 DEG C, and the scope of the second temperature of the second annealing process (IV) is about 1000 DEG C to about 1150 DEG C.
For improveing the effect of oxidizing process and thermal treatment process, front at the first annealing process (II), can comprise according to the two step annealing processs of embodiment of the present invention that silicon wafer 200 to be loaded into furnace apparatus inner and then silicon wafer 200 is retained to the loading process (L) that loading temperature lasts a predetermined lasting time further.And, after the second annealing process (IV), according to the two step annealing processs of embodiment of the present invention can be included in further silicon wafer 200 is offloaded to furnace apparatus outside before silicon wafer 200 is retained to the uninstall process (UL) that unloading temperature lasts a predetermined lasting time.
The loading temperature of loading process (L) is lower than the first temperature.Preferably, the scope of loading temperature is about 600 DEG C to about 700 DEG C.Loading process (L) period not by oxygen supply in furnace apparatus.As a result, be oxidized at loading process (L) period silicon wafer 200.The unloading temperature of uninstall process (UL) equals the first temperature substantially.Preferably, the scope of unloading temperature is about 750 DEG C to about 800 DEG C.In uninstall process (UL) period, not supply oxygen and only the supply of nitrogen.The scope of the flow rate of nitrogen is about 9slm to about 11slm.
In addition, according to the two step annealing processs of embodiment of the present invention can be included in further between loading process (L) and the first annealing process (II) for loading temperature is heated to the first temperature the first heating process (I) and between the first annealing process (II) and the second annealing process (IV) for the second heating process (III) by the first heating temperatures to the second temperature.When during the first heating process (I) and the second heating process (III), per minute temperature rise rate is too high, chip architecture may be out of shape.Therefore, the temperature rise rate in the first heating process (I) and the second heating process (III) can be set as the scope of about 5 DEG C/min to about 8 DEG C/min.
And, the process for cooling (V) for the second temperature being cooled to unloading temperature between the second annealing process (IV) and uninstall process (UL) can be included in further according to the two step annealing processs of embodiment of the present invention.The scope of the rate of temperature fall of process for cooling (V) can be about 2 DEG C/min to about 4 DEG C/min.
According in the two step annealing processs of embodiment of the present invention, the annealing of silicon wafer 200 is main substantially to be realized at the first annealing process and the second annealing process (II, IV) period, because only supply oxygen during these techniques.The scope of the flow rate of the oxygen that the first annealing process and the second annealing process (II, IV) period supply can be about 50sccm to about 120sccm.The first annealing process can be implemented and the second annealing process (II, IV) all lasts about 100 minutes to about 180 minutes.
The two step annealing processs as described in Fig. 6 can be applicable to show in Fig. 3 to Fig. 5 according to the following embodiment of the present invention for the manufacture of the first annealing process of the method for silicon wafer and the second annealing process.
Fig. 3 is the cross-sectional view of the method for the manufacture of silicon wafer illustrated according to the second embodiment of the invention.
Referring to Fig. 3, implement the thermal process to silicon wafer 300, the oxide elements 303 between the end face 301 of silicon wafer 300 and the back side 302 is internally spread.As a result, the first denuded zone DZ1 and the second denuded zone DZ2 and body regions BK is formed.Thermal process can be RTP or uses the annealing process of furnace apparatus.Preferably, the first thermal process comprises RTP.
For the end face 301 of rapid diffusion silicon wafer 300 and the oxide elements 303 at the back side 302, at high temperature implement thermal process.When thermal process is RTP, be implement thermal process at the temperature of 1050 DEG C to about 1150 DEG C to last about 10 seconds to about 30 seconds in scope.When thermal process is annealing process, be implement thermal process at the temperature of 1050 DEG C to about 1150 DEG C to last about 100 minutes to about 200 minutes in scope.
Subsequently, the first annealing process is implemented to silicon wafer 300, the oxide elements 203 in body regions BK is combined.As a result, oxygen precipitate core 304 is formed.Under the preset temperature of the temperature lower than thermal process, use furnace apparatus to implement the first annealing process.Preferably, be implement the first annealing process at the temperature of about 750 DEG C to about 800 DEG C to last about 100 minutes to about 180 minutes in scope.In addition, at oxygen (O 2) atmosphere encloses lower enforcement first annealing process.
Second annealing process is implemented to silicon wafer 300.Also furnace apparatus is used to implement the second annealing process.By heating silicon wafer 300 under the preset temperature of the temperature higher than the first annealing process, produce oxygen precipitate 305.Preferably, be implement the second annealing process at the temperature of about 1000 DEG C to about 1150 DEG C to last about 100 minutes to about 180 minutes in scope.In addition, at oxygen (O 2) atmosphere encloses lower enforcement second annealing process.
Fig. 4 is the cross-sectional view of the method for the manufacture of silicon wafer illustrated according to the third embodiment of the invention.
In the diagram, at the temperature of the thermal process temperature lower than Fig. 3, implement the thermal process before the first annealing process.
With reference to figure 4, at the temperature of the thermal process temperature lower than Fig. 3, thermal process is implemented to silicon wafer 400.Therefore, oxygen precipitate core 404 is produced.Because thermal process is implemented at low temperatures, so form oxygen precipitate core 404 in the first denuded zone DZ1 and the second denuded zone DZ2 and body regions BK.Thermal process can be RTP or annealing process.Preferably, the first thermal process comprises RTP.When thermal process is RTP, at the temperature of about 950 DEG C to about 1000 DEG C, implement thermal process about 10 seconds to about 30 seconds.When thermal process is annealing process, at the temperature of about 950 DEG C to about 1000 DEG C, implement thermal process about 100 minutes to about 200 minutes.
Subsequently, the first annealing process and the second annealing process are implemented successively to silicon wafer 400, make to produce oxygen precipitate core 404 and oxygen precipitate 405A.The first annealing process and the second annealing process is implemented under the condition identical with first annealing process of Fig. 3 and those conditions of the second annealing process.
Fig. 5 is the cross-sectional view that the method manufacturing silicon wafer according to four embodiment of the invention is described.
With reference to figure 5, different from the annealing process shown in Fig. 2 to Fig. 4, according to the annealing process of four embodiment of the invention without the need to the extra heat technique before the first annealing process and the second annealing process.That is, be provided as the silicon wafer 500 of naked wafer, and the first annealing process and the second annealing process are implemented successively to silicon wafer 500, make formation first denuded zone DZI and the second denuded zone DZ2 and body regions BK.The first annealing process and the second annealing process is implemented under the condition identical with those conditions of the first annealing process shown in Fig. 2 to Fig. 4 and the second annealing process.
In Figure 5, Reference numeral ' 501 ' represents end face, and ' 502 ' represents the back side, and ' 503 ' represents oxide elements, and ' 504 ' represents oxygen precipitate core, and ' 505A ' represents oxygen precipitate, and ' 505B ' represents the oxygen precipitate increased.
As mentioned above, the method for silicon wafer constructed in accordance is described referring to figs. 2 to Fig. 5.As previously mentioned, in the shown in Fig. 2 to Fig. 4 first to the 3rd embodiment, RTP preferably before the first annealing process and the second annealing process for thermal process.
The subsurface defect of the oxygen precipitate in silicon wafer or void defects can be controlled during monocrystalline silicon growing, or are controlled by thermal process after monocrystalline silicon growing.As described above, thermal process can comprise the RTP using halogen lamp and the annealing process using furnace apparatus.
At argon (Ar) gas or hydrogen (H 2) atmosphere implements under higher than the high temperature of about 1000 DEG C to use the annealing process of furnace apparatus to be greater than about 100 minutes long-time under enclosing.In the silicon wafer caused by annealing process thus, the diffusion of oxide elements and silicon are reset, and form device ideal area (that is, nondefective zone (DFZ)) in a part for the end face of silicon wafer.But along with silicon wafer sizes increases, this annealing process is difficult to the pollution or the slip dislocation that control silicon wafer due to high-temperature heat treatment.
Therefore, RTP obtains the silicon wafer characteristic being better than annealing process.But, when using various defect detecting method to assess the silicon wafer manufactured by RTP, control oxygen precipitate only in the degree of depth from end face about 3 microns to about 10 microns.In addition, when by only implementing RTP and manufacturing silicon wafer once or twice, there is the restriction to realizing high bmd density in body regions.More specifically, when once manufacturing silicon wafer by enforcement RTP, bmd density is through being defined as 1 × 10 6ea/cm 2to 3 × 10 6ea/cm 2, and be difficult to make bmd density exceed this scope.
In embodiments of the invention, as shown in Figures 2 to 4, after thermal process, implement two step annealing processs, remove the void defects near silicon wafer end face and oxygen precipitate thus.As a result, the present invention can guarantee nondefective zone (DFz) and increase the bmd density of the stacking defect of body and the oxygen precipitate comprised in body regions, improves gettering effect thus by the gettering site increased in body regions.
Hereinafter, the characteristic of the silicon wafer manufactured by embodiment of the present invention described in detail by reference table 1 and table 2.
[table 1]
[table 2]
In Table 1, argon (Ar) gas, nitrogen (N is used 2) gas, ammonia (NH 3) gas or its combination, under rapid thermal process implement ' high temperature RTP ' and ' low temperature RTP ' about 10 seconds to about 30 seconds.Use oxygen (O 2) gas implements ' low temperature annealing process ' and ' high-temperature annealing process ' about 100 minutes to about 180 minutes.
In table 1 and table 2, ' condition 1 ' represents the first embodiment shown in Fig. 2, ' condition 2 ' represents the second embodiment shown in Fig. 3, and ' condition 3 ' represents the 3rd embodiment shown in Fig. 4, and ' condition 4 ' represents the 4th embodiment shown in Fig. 5.Table 2 shows bmd density according to the oxygen concn (oi) in each condition and denuded zone (DZ) degree of depth.
Fig. 7 to Figure 12 is the figure of the parameter of indicator gauge 1 and table 2.Specifically, Fig. 7 illustrates the figure for the bmd density of each condition.Fig. 8 illustrates the figure for the DZ degree of depth of each condition.Fig. 9 to Figure 12 illustrates the figure for oxygen concn in the body regions of each condition.
Reference table 2 and Fig. 7, all obtain under all conditions and be greater than 1 × 10 5ea/cm 2bmd density.Specifically, regardless of oxygen concn, all obtain for 1 time in condition and be greater than 1 × 10 6ea/cm 2bmd density.Although do not show for by only implementing the RTP data of bmd density of the silicon wafer manufactured once or twice, this bmd density measurable compared with the bmd density under above condition by significantly lower.
As previously mentioned, metal pollutant is controlled by gettering BMD.But, because bmd density tends to reduce during high-temperature technology, so need to guarantee high bmd density during manufacture silicon wafer.Generally speaking, semiconducter device needs the high voltage device that operates under high voltage environment.For manufacturing this high voltage device, heavy ion injection technology and high-temperature annealing process must be implemented, this is because need the tie region (that is, doped region) with dark distribution.When bmd density reduces during high-temperature annealing process, not only due to defect estimation but also due to low gettering ability, so there is ring-type dislocation at follow-up shallow trench isolation after (STI).
As the result measuring bmd density, when bmd density is about 2.5 × 10 5ea/cm 2time local there is ring-type dislocation, but when bmd density be about 4.4 × 10 5ea/cm 2time there is not ring-type dislocation.Therefore, need to control bmd density and be greater than at least 1 × 10 5ea/cm 2.In the present embodiment, regardless of conventional thermal process during manufacture silicon wafer, all two step annealing processs to be implemented in addition for the initial process manufacturing semiconducter device.Initial process is included in the ion implantation oxidizing process implemented before forming trap.Oxidizing process corresponds to and is forming the technique of ion implantation (ion implantation hereinafter referred to as trap) period for the formation of screen oxide layer of trap.
Reference table 2 and Fig. 8, show the DZ degree of depth according to each condition.The DZ degree of depth is closely related with bmd density and oxygen concn.Along with bmd density and oxygen concn increase, the DZ degree of depth reduces.When oxygen concn under each condition all identical (such as, for 11.6 in table 2) time, bmd density under condition 1 and condition 2 is higher than the bmd density under condition 3 and condition 4, but the DZ degree of depth under condition 1 and condition 2 is lower than the DZ degree of depth under condition 3 and condition 4.Therefore, the DZ degree of depth can be the tolerance of bmd density.
Reference table 2 and Fig. 9 to Figure 12, show under each condition according to the bmd density of oxygen concn and the DZ degree of depth.Along with oxygen concn (Oi) increases, bmd density increases and the DZ degree of depth reduces.Therefore, oxygen concn (Oi) is also the tolerance of bmd density.That is, the bmd density in body regions is calculated by the measurement DZ degree of depth and oxygen concn (Oi).
Figure 13 and Figure 14 is the cross-sectional view of silicon wafer.
Specifically, Figure 13 display by implementing only RTP without two step annealing processs with the cross-sectional view of the silicon wafer manufactured, the cross-sectional view of the silicon wafer that Figure 14 display is manufactured by enforcement two step annealing process according to one embodiment of the invention.
As shown in the figure, in the silicon wafer of Figure 13, there is multiple silicon dislocation, but there is not silicon dislocation in the silicon wafer of Figure 14.In addition, when by using epitaxy to form epitaxial film, the lattice defect in the body regions (wherein forming epitaxial film) of silicon wafer is significantly reduced.
Figure 15 and Figure 16 illustrates the lattice defect figure of body regions in silicon wafer (wherein forming epitaxial film).The verifying attachment manufactured by KLA company is used to implement this inspection.
As illustrated in fig. 15, when implementing do not have the oxidizing process of two step annealing processs, a large amount of lattice defect is distributed in figure.At this, oxidizing process forms screen oxide layer in trap ion implantation period.On the contrary, as shown in figure 16, when implementing to have the oxidizing process of two step annealing processs of the present invention, lattice defect significantly reduces.
Hereinafter, describe the method with the semiconducter device of trap manufacturing and be used for high voltage device in detail with reference to Figure 17 A to Figure 17 D, the method comprises two step annealing processs according to an embodiment of the invention.
Figure 17 A to Figure 17 D illustrates the method manufacturing semiconducter device according to an embodiment of the invention.
With reference to figure 17A, the two step annealing processs shown in Fig. 6 are used to form screen oxide layer 601 on silicon wafer 600.Silicon wafer 600 can be the enforcement RTP wafer once or twice as described in Fig. 2 to Fig. 4, or is the as shown in Figure 5 naked wafer not implementing RTP.Screen oxide layer 601 can be silicon oxide layer, and is formed as about extremely about thickness.
With reference to figure 17B, in silicon wafer 600, form trap 602 to predetermined depth.Trap 602 can be p-type or N-shaped conduction type according to the conduction type of high voltage device.
Trap 602 is formed by ion implantation technology and diffusion technique.Only ion implantation technology is used to be difficult to form the trap for high voltage device.Therefore, after completing ion implantation technology, diffusion technique and ion implantation technology should be implemented in addition, to form the trap 602 of the dopant profiles with Figure 17 B.By using the annealing process implemented for long periods diffusion technique of the high-temperature heating equipment of such as stove.Preferably, only nitrogen (N is used 2) at the temperature of about 1100 DEG C to about 1250 DEG C, implement diffusion technique about 6 little of about 10 hours for gas.
Referring to Figure 17 C, pad nitride layer (not shown) as hard mask is formed in screen oxide layer 601, or pad nitride layer is formed on buffer layer (not shown), this buffer layer is formed by implementing additional oxidation technique after removing screen oxide layer 601.The reason removing screen oxide layer 601 is that screen oxide layer 601 is not suitable for buffer layer, this is because screen oxide layer 601 is damaged during ion implantation technology.Then in pad nitride layer, form the photoetching agent pattern 604 for the formation of sti trench groove.
Pad nitride layer is formed by low-pressure chemical vapor deposition (LPCVD) technique, to prevent silicon wafer 600 impaired by being applied to the stress of silicon wafer 600 during being minimized in depositing operation.Pad nitride layer can be formed by silicon nitride.Pad nitride layer can be formed as about extremely about thickness.
Use photoetching agent pattern 604 as etching mask, partly etch pad nitride layer, screen oxide layer 601 and silicon wafer 600 successively, form pad nitride article pattern 603, screen oxide pattern 601A, silicon wafer 600A and trap 602A thus.As a result, in silicon wafer 600A, form the groove 605 with predetermined depth and slope.
Referring to Figure 17 D, form the device isolation structure 606 of filling groove 605, remove pad nitride article pattern 603 and screen oxide pattern 601A subsequently.Device isolation structure 606 can be formed by high density plasma (HDP) layer with excellent gap-filling properties.
While method more of the present invention and comparative example, hereafter the beneficial effect of above embodiment of the present invention will be described.Method of the present invention comprises by using the oxidizing process of two step annealing processs to form screen oxide layer, and comparative example comprises by using the oxidizing process of a step annealing technique to form screen oxide layer.In the oxidizing process of this comparative example, use wet oxidation process silicon wafer at the single temperature of 800 DEG C to 850 DEG C.
Figure 18 to Figure 21 illustrates the defect in the silicon wafer prepared by the oxidizing process of comparative example.
Specifically, after Figure 18 illustrates and forms groove via STI technique in the silicon wafer prepared in the oxidizing process by comparative example, the diagram data of the lattice defect that the verifying attachment manufactured by KLA company is checked.As shown in figure 18, can be observed the lattice defect that there is such as ring-type silicon dislocation in most of defect chip.
Silicon wafer scanning electronic microscope (SEM) photo that Figure 19 and Figure 20 obtains for the verifying attachment manufactured by KLA company.
Specifically, Figure 19 is the SEM image in display silicon wafer cross section, and Figure 20 is planar tilt STM image.As shown in FIG. 19 and 20, can be observed to there is lattice defect and dislocation.
Figure 21 is this bulky micro defect (BMD) density analysis is carried out in display Photomicrograph to the silicon wafer with ring-type defect.
As further shown in figure 21, can be observed most of BMD and formed near the end face of silicon wafer, and only have minority BMD to be formed in the middle body of silicon wafer, that is, be formed in body regions.That is, the bmd density of body regions is significantly lower than the bmd density of the end face of silicon wafer.
Figure 22 to Figure 24 is the assay of lattice defect in the silicon wafer by using the oxidizing process of two step annealing processs according to embodiments of the present invention to prepare.This inspection uses the verifying attachment manufactured by KLA company to implement.
Specifically, Figure 22 illustrates the assay via the lattice defect of silicon wafer after STI technique formation groove in the silicon wafer prepared in the oxidizing process of the two step annealing processs of the application of the invention.As shown in figure 22, can be observed lattice defect removed and some particulates or dust only detected.
The planar tilt STM image of the silicon wafer that Figure 23 obtains for the verifying attachment manufactured by KLA company.Similar with the result of Figure 22, can be observed some particles only to be detected.
Figure 24 is that display carries out the Photomicrograph of bmd density analysis to silicon wafer prepared by the oxidizing process of the application of the invention two step annealing process.As shown in figure 24, can be observed evenly to form BMD in whole silicon wafer.
Figure 25 is for illustrating the comparative result figure of leakage current during static RAM (SRAM) ready mode.In fig. 25, the sample of high voltage device prepared by the oxidizing process that the figure on the left side shows the application of the invention two step annealing process, the sample of the high voltage device of the figure display comparison example on the right.As shown in figure 25, compared with the sample prepared with the oxidizing process by comparative example, the sample that can be observed to be prepared by oxidizing process of the present invention shows even leakage current characteristic.
Figure 26 is the comparative result figure that good article rate is described.In fig. 26, the sample of high voltage device prepared by the oxidizing process that the figure on the left side shows the application of the invention two step annealing process, the sample of the high voltage device of the figure display comparison example on the right.As shown in figure 26, compared with the sample of comparative example, the good article rate height about 5%-9% of the sample prepared by oxidizing process of the present invention.
According to the present invention, first, in silicon wafer, gettering site is produced by implementing two step annealing processs at different temperatures fully.This makes the generation of the lattice defect that can prevent the heat budget caused due to subsequent high temperature thermal treatment process from causing.
Secondly, the present invention has height and the silicon wafer of Uniform B MD density by implementing two step annealing processs at different temperatures to be provided in body regions.
3rd, according to the present invention, after implementing two step annealing processs to silicon wafer at different temperatures, use epitaxy to form epitaxial film on silicon.As a result, the present invention can provide the semiconducter device being formed and have the epitaxial film of excellent specific property.
4th, according to the present invention, by implementing two step annealing processs with after forming screen oxide layer on silicon to silicon wafer at different temperatures, implement ion implantation technology to form trap in silicon wafer by using screen oxide layer as ion mask.As a result, the present invention can produce gettering site fully in silicon wafer, the generation of the lattice defect caused to prevent the heat budget caused due to subsequent high temperature thermal treatment process thus.
Although describe the present invention for particular, those skilled in the art obviously can make various change and amendment when not departing from the spirit of the present invention and category that are limited by following claim.
Remarks
Remarks 1. 1 kinds of silicon wafers, it comprises: the first denuded zone, and it is formed as the predetermined depth of the end face had from described silicon wafer; And body regions, it is formed between described first denuded zone and the back side of described silicon wafer, wherein said first denuded zone is formed as having the degree of depth from described end face about 20 microns to about 80 microns, and the oxygen concn in wherein said body regions in whole described body regions with 10% in change be uniformly distributed.
Remarks 2. is as the silicon wafer of remarks 1, and in wherein said body regions, the density of this bulky micro defect (BMD) is about 1 × 10 5ea/cm 2to about 1 × 10 7ea/cm 2.
Remarks 3. is as the silicon wafer of remarks 1, and the oxygen concn in wherein said body regions is about 10.5 to about 13PPMA (atom PPMs).
Remarks 4. is as the silicon wafer of remarks 1, and it also comprises epitaxial film, and described epitaxial film is formed in by epitaxy on the end face of described silicon wafer.
Remarks 5. is as the silicon wafer of remarks 1, and it also comprises the second denuded zone, and described second denuded zone to be formed at below described body regions and the predetermined depth had from the described back side towards the direction of described end face.
Remarks 6. is as the silicon wafer of remarks 5, and wherein said second denuded zone is formed as the degree of depth with about 20 microns to about 80 microns from the described back side.
Remarks 7. 1 kinds of methods for the manufacture of silicon wafer, it comprises: provide the silicon wafer with denuded zone and body regions; At a first temperature the first annealing process is implemented to described silicon wafer and produce oxygen precipitate core and oxygen precipitate to supplement in described body regions; With at the second temperature higher than described first temperature, the second annealing process is implemented to increase the described oxygen precipitate in described body regions to described silicon wafer.
Remarks 8. is as the method for remarks 7, and wherein said first annealing process is implemented at the temperature of about 750 DEG C to about 800 DEG C.
Remarks 9. is as the method for remarks 7, and wherein said second annealing process is implemented at the temperature of about 1000 DEG C to about 1150 DEG C.
Remarks 10. is as the method for remarks 7, and providing of wherein said silicon wafer comprises: at the 3rd temperature being equal to or less than described second temperature, implement the first thermal process to form described denuded zone and described body regions to described silicon wafer; With higher than described first temperature lower than the 4th temperature of described 3rd temperature under the second thermal process is implemented to form described oxygen precipitate core in described body regions to described silicon wafer.
Remarks 11. is as the method for remarks 10, and wherein said first thermal process and described second thermal process are implemented by rapid hot technics (RTP) or annealing process.
Remarks 12. is as the method for remarks 10, and wherein said first thermal process is implemented at the temperature of about 1050 DEG C to about 1150 DEG C, and described second thermal process is implemented at the temperature of about 950 DEG C to about 1000 DEG C.
Remarks 13. is as the method for remarks 10, and wherein said first thermal process and described second thermal process use argon (Ar) gas, nitrogen (N 2) gas, ammonia (NH 3) gas or its combination.
Remarks 14. is as the method for remarks 7, and providing of wherein said silicon wafer comprises: at the 3rd temperature being equal to or less than described second temperature, implement thermal process to form described denuded zone and described body regions to described silicon wafer.
Remarks 15. is as the method for remarks 14, and wherein said thermal process is implemented at the temperature of about 1050 DEG C to about 1150 DEG C.
Remarks 16. is as the method for remarks 7, and providing of wherein said silicon wafer comprises: higher than described first temperature lower than the 3rd temperature of described second temperature under thermal process is implemented to form described denuded zone and described body regions to described silicon wafer.
Remarks 17. is as the method for remarks 16, and wherein said thermal process is implemented at the temperature of about 950 DEG C to about 1000 DEG C.
Remarks 18. is as the method for remarks 7, and wherein said first annealing process and described second annealing process are at oxygen (O 2) atmosphere encloses lower enforcement.
Remarks 19. is as the method for remarks 7, and wherein said first annealing process and described both second annealing processs all implement about 100 minutes to about 180 minutes.
Remarks 20. is as the method for remarks 7, and wherein said denuded zone is formed as the degree of depth of the end face about 20 microns to about 80 microns had from described silicon wafer.
Remarks 21. is as the method for remarks 7, and wherein after described second annealing process of enforcement, the density domination that described body regions comprises this bulky micro defect (BMD) of described oxygen precipitate is about 1 × 10 5ea/cm 2to about 1 × 10 7ea/cm 2.
Remarks 22. as the method for remarks 7, wherein after described second annealing process of enforcement, oxygen concn in described body regions control in whole described body regions with 10% in change be uniformly distributed.
Remarks 23. is as the method for remarks 7, and wherein after described second annealing process of enforcement, the oxygen concn in described body regions controls as about 10.5 to about 13PPMA.
Remarks 24. is as the method for remarks 7, and it also comprises: remove the oxide skin formed on the end face of described silicon wafer during described second annealing process; Form epitaxial film with by epitaxy, described epitaxial film is formed on the end face of described silicon wafer.
Remarks 25. is as the method for remarks 7, and it also comprises: by using oxide skin to form trap as buffer layer in described silicon wafer, wherein said oxide skin is formed on the end face of described silicon wafer during described second annealing process.
Remarks 26. is as the method for remarks 7, and providing of wherein said silicon wafer comprises: growing single-crystal silicon; The silicon single crystal of described growth is cut into wafer shape; With implement etch process to etch the surface of the silicon wafer of described cutting or to make the side sphering of silicon wafer of described cutting.
Remarks 27. 1 kinds manufactures the method for silicon wafer, and it comprises: provide silicon wafer; Under loading temperature, described silicon wafer is loaded into heating unit inside; Implement the first heating process described silicon wafer being heated to the first temperature from described loading temperature; The first annealing process implementing described silicon wafer is annealed at described first temperature is to produce oxygen precipitate; To implement described silicon wafer from described first heating temperatures to higher than the second heating process of the second temperature of described first temperature; The second annealing process implementing described silicon wafer is annealed at described second temperature to increase described oxygen precipitate, thus increases its density; Implement the process for cooling described silicon wafer being cooled to unloading temperature from described second temperature; Outside is offloaded to from described heating unit with by described silicon wafer.
Remarks 28. is as the method for remarks 27, and providing of wherein said silicon wafer comprises: by implementing thermal process to form denuded zone and body regions in described silicon wafer to described silicon wafer.
Remarks 29. is as the method for remarks 27, and wherein said loading temperature is about 600 DEG C to about 700 DEG C.
Remarks 30. is as the method for remarks 27, and the temperature rise rate of wherein said first heating process is about 5 DEG C/min to about 8 DEG C/min.
Remarks 31. is as the method for remarks 27, and wherein said first temperature is about 750 DEG C to about 800 DEG C.
Remarks 32. is as the method for remarks 27, and the temperature rise rate of wherein said second heating process is about 5 DEG C/min to about 8 DEG C/min.
Remarks 33. is as the method for remarks 27, and wherein said second temperature is about 1000 DEG C of extremely about 11S0 DEG C.
Remarks 34. is as the method for remarks 27, and the rate of temperature fall of wherein said process for cooling is about 2 DEG C/min to about 4 DEG C/min.
Remarks 35. is as the method for remarks 27, and wherein said unloading temperature is about 750 DEG C to about 800 DEG C.
Remarks 36. is as the method for remarks 27, and wherein said silicon wafer unloading uses nitrogen (N 2) gas enforcement.
Remarks 37. is as the method for remarks 27, and wherein said first annealing process and described second annealing process use oxygen (O 2) gas enforcement.

Claims (32)

1., for the manufacture of a method for silicon wafer, it comprises:
Described silicon wafer is heat-treated to form denuded zone and body regions in described silicon wafer;
To be loaded in heating unit through heat treated described silicon wafer under loading temperature and at a first temperature the first annealing process be implemented to described silicon wafer and produce oxygen precipitate core and oxygen precipitate to supplement in described body regions; With
At the second temperature higher than described first temperature, the second annealing process is implemented to increase the described oxygen precipitate in described body regions to described silicon wafer;
The described thermal treatment of wherein said silicon wafer was carried out before the described loading through heat treated described silicon wafer; With
The thermal treatment of described silicon wafer comprises implements the first thermal process and the second thermal process to described silicon wafer, and described second thermal process is implemented and in described body regions, formed described oxygen precipitate core at the temperature lower than described first thermal process.
2. method as claimed in claim 1, wherein said first annealing process is implemented at the temperature of 750 DEG C to 800 DEG C.
3. method as claimed in claim 1, wherein said second annealing process is implemented at the temperature of 1000 DEG C to 1150 DEG C.
4. method as claimed in claim 1, wherein
At the 3rd temperature being equal to or less than described second temperature, the first thermal process is implemented to form described denuded zone and described body regions to described silicon wafer; With
Higher than described first temperature lower than the 4th temperature of described 3rd temperature under the second thermal process is implemented to form described oxygen precipitate core in described body regions to described silicon wafer.
5. method as claimed in claim 4, wherein said first thermal process and described second thermal process are implemented by rapid hot technics (RTP) or annealing process.
6. method as claimed in claim 4, wherein said first thermal process is implemented at the temperature of 1050 DEG C to 1150 DEG C, and described second thermal process is implemented at the temperature of 950 DEG C to 1000 DEG C.
7. method as claimed in claim 4, wherein said first thermal process and described second thermal process use argon (Ar) gas, nitrogen (N 2) gas, ammonia (NH 3) gas or its combination.
8. method as claimed in claim 1, wherein
At the 3rd temperature being equal to or less than described second temperature, described first thermal process is implemented to form described denuded zone and described body regions to described silicon wafer.
9. method as claimed in claim 8, wherein said first thermal process is implemented at the temperature of 1050 DEG C to 1150 DEG C.
10. method as claimed in claim 1, wherein
Higher than described first temperature lower than the 3rd temperature of described second temperature under the second thermal process is implemented to form described denuded zone and described body regions to described silicon wafer.
11. as the method for claim 10, and wherein said second thermal process is implemented at the temperature of 950 DEG C to 1000 DEG C.
12. methods as claimed in claim 1, wherein said first annealing process and described second annealing process are at oxygen (O 2) atmosphere encloses lower enforcement.
13. methods as claimed in claim 1, wherein said first annealing process and described both second annealing processs are implemented 100 minutes to 180 minutes separately.
14. methods as claimed in claim 1, wherein said denuded zone is formed as the degree of depth of the end face 20 microns to 80 microns had from described silicon wafer.
15. methods as claimed in claim 1, wherein after described second annealing process of enforcement, the density domination that described body regions comprises this bulky micro defect (BMD) of described oxygen precipitate is 1 × 10 5ea/cm 2to 1 × 10 7ea/cm 2.
16. methods as claimed in claim 1, wherein after described second annealing process of enforcement, oxygen concn in described body regions control in whole described body regions with 10% in change be uniformly distributed.
17. methods as claimed in claim 1, wherein after described second annealing process of enforcement, it is 10.5 to 13PPMA that the oxygen concn in described body regions controls.
18. methods as claimed in claim 1, it also comprises:
Remove the oxide skin formed on the end face of described silicon wafer during described second annealing process; With
Form epitaxial film by epitaxy, described epitaxial film is formed on the end face of described silicon wafer.
19. methods as claimed in claim 1, it also comprises:
By using oxide skin to form trap as buffer layer in described silicon wafer, wherein said oxide skin is formed on the end face of described silicon wafer during described second annealing process.
20. methods as claimed in claim 1, also comprise and provide silicon wafer for thermal treatment to form described denuded zone and described body regions, the wherein said silicon wafer that provides comprises:
Growing single-crystal silicon;
The silicon single crystal of described growth is cut into wafer shape; With
Implement etch process to etch the surface of the silicon wafer of described cutting or to make the side sphering of silicon wafer of described cutting.
The method of 21. 1 kinds of semiconductor machining, it comprises:
Silicon wafer is heat-treated to form denuded zone and body regions in described silicon wafer;
To be loaded in heating unit through heat treated described silicon wafer under loading temperature;
Loaded silicon wafer is carried out first from described loading temperature and is heated to the first temperature;
At described first temperature, the first annealing is carried out to produce oxygen precipitate described in the described silicon wafer of the first heating to the described silicon wafer through the first heating;
Described silicon wafer through the first annealing is directly carried out second from described first temperature and is heated to the second temperature, described second temperature is higher than described first temperature;
At described second temperature, the second annealing is carried out to increase and to increase the density of described described oxygen deposition thing in the described silicon wafer of the second heating to the described silicon wafer through the second heating;
Described silicon wafer through the second annealing is cooled to unloading temperature from described second temperature; With
From the described silicon wafer of described heating unit unloading through cooling under described unloading temperature,
The described thermal treatment of wherein said silicon wafer was carried out before the described loading through heat treated described silicon wafer.
22. as the method for claim 21, and wherein said loading temperature is 600 DEG C to 700 DEG C.
23. as the method for claim 21, and the temperature rise rate of the first heating of the silicon wafer of wherein said loading is 5 DEG C/min to 8 DEG C/min.
24. as the method for claim 21, and wherein said first temperature is 750 DEG C to 800 DEG C.
25. as the method for claim 21, and the temperature rise rate wherein through described second heating of the described silicon wafer of the first annealing is 5 DEG C/min to 8 DEG C/min.
26. as the method for claim 21, and wherein said second temperature is 1000 DEG C to 1150 DEG C.
27. as the method for claim 21, and the rate of temperature fall wherein through the described cooling of the described silicon wafer of the second annealing is 2 DEG C/min to 4 DEG C/min.
28. as the method for claim 21, and wherein said unloading temperature is 750 DEG C to 800 DEG C.
29. as the method for claim 21, and wherein said silicon wafer unloading uses nitrogen (N 2) gas enforcement.
30. as the method for claim 21, wherein said first annealing and described second annealing use oxygen (O 2) gas enforcement.
31. as the method for claim 21, and wherein said silicon wafer comprises naked wafer.
The method of 32. 1 kinds of semiconductor machining, comprising:
Naked wafer is heat-treated to form denuded zone and body regions in described naked wafer;
To enter in heating unit through heat treated naked wafer-load under loading temperature;
Loaded described naked wafer is carried out first from described loading temperature and is heated to the first temperature;
At described first temperature, the first annealing is carried out to produce oxygen precipitate in the described naked wafer through the first heating to the described naked wafer through the first heating;
Described naked wafer through the first annealing is directly carried out second from described first temperature and is heated to the second temperature, described second temperature is higher than described first temperature;
At described second temperature, the second annealing is carried out to increase and to increase the density of described described oxygen precipitate in the described naked wafer of the second heating to the described naked wafer through the second heating;
Described naked wafer through the second annealing is cooled to unloading temperature from described second temperature; With
From the described naked wafer of described heating unit unloading through cooling under unloading temperature.
CN201310361966.3A 2008-09-29 2009-09-28 Method for fabricating silicon wafer Active CN103498196B (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
KR10-2008-0095462 2008-09-29
KR20080095462 2008-09-29
KR10-2009-0003697 2009-01-16
KR1020090003697A KR20100036155A (en) 2008-09-29 2009-01-16 Silicon wafer and fabrication method thereof
CN2009101745256A CN101713098B (en) 2008-09-29 2009-09-28 Silicon wafer and fabrication method thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN2009101745256A Division CN101713098B (en) 2008-09-29 2009-09-28 Silicon wafer and fabrication method thereof

Publications (2)

Publication Number Publication Date
CN103498196A CN103498196A (en) 2014-01-08
CN103498196B true CN103498196B (en) 2015-07-01

Family

ID=42213859

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201310361966.3A Active CN103498196B (en) 2008-09-29 2009-09-28 Method for fabricating silicon wafer
CN2009101745256A Active CN101713098B (en) 2008-09-29 2009-09-28 Silicon wafer and fabrication method thereof

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN2009101745256A Active CN101713098B (en) 2008-09-29 2009-09-28 Silicon wafer and fabrication method thereof

Country Status (4)

Country Link
JP (1) JP5940238B2 (en)
KR (2) KR20100036155A (en)
CN (2) CN103498196B (en)
TW (1) TWI395844B (en)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2966980B1 (en) * 2010-11-02 2013-07-12 Commissariat Energie Atomique METHOD OF MANUFACTURING SOLAR CELLS, ATTENUATING THE PHENOMENA OF LID
KR101971597B1 (en) * 2011-10-26 2019-04-24 엘지이노텍 주식회사 Wafer and method of fabrication thin film
JP5737202B2 (en) * 2012-01-30 2015-06-17 信越半導体株式会社 Semiconductor device and method for forming the same
KR101340237B1 (en) * 2012-02-27 2013-12-10 주식회사 엘지실트론 Single crystal silicon ingot growing method, single crystal silicon ingot, and epitaxial silicon wafer
CN104779135A (en) * 2014-01-10 2015-07-15 上海华虹宏力半导体制造有限公司 Method of eliminating influences of control wafer during batch polysilicon deposition process
DE102014208815B4 (en) * 2014-05-09 2018-06-21 Siltronic Ag Process for producing a semiconductor wafer made of silicon
JP6241381B2 (en) * 2014-07-09 2017-12-06 株式会社Sumco Epitaxial silicon wafer manufacturing method
CN106158583B (en) * 2015-04-01 2019-10-15 北大方正集团有限公司 A kind of method that silicon wafer forms sacrificial oxide layer
WO2018008561A1 (en) * 2016-07-06 2018-01-11 株式会社トクヤマ Single crystal silicon plate-shaped body and production method therefor
JP6254748B1 (en) * 2016-11-14 2017-12-27 信越化学工業株式会社 High photoelectric conversion efficiency solar cell manufacturing method and high photoelectric conversion efficiency solar cell
DE102016225138A1 (en) * 2016-12-15 2018-06-21 Siltronic Ag Single-crystal silicon wafer and method for producing a single-crystal silicon wafer
CN108987250B (en) * 2017-06-02 2021-08-17 上海新昇半导体科技有限公司 Substrate and manufacturing method thereof
US11060981B2 (en) * 2018-03-20 2021-07-13 Applied Materials Israel Ltd. Guided inspection of a semiconductor wafer based on spatial density analysis
WO2020102990A1 (en) * 2018-11-20 2020-05-28 长江存储科技有限责任公司 Formation method and annealing device for epitaxial layer and 3d nand memory
CN109830437B (en) * 2019-01-25 2021-05-28 西安奕斯伟硅片技术有限公司 Wafer heat treatment method and wafer
US11710656B2 (en) * 2019-09-30 2023-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor-on-insulator (SOI) substrate
DE102020107236B4 (en) * 2019-09-30 2023-05-04 Taiwan Semiconductor Manufacturing Co. Ltd. METHOD OF MAKING A SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE
CN111430236B (en) * 2020-05-06 2021-05-14 合肥晶合集成电路股份有限公司 Wafer annealing method
JP6978641B1 (en) 2020-09-17 2021-12-08 日本碍子株式会社 Group III element nitride semiconductor substrate
WO2022059244A1 (en) * 2020-09-17 2022-03-24 日本碍子株式会社 Group iii nitride semiconductor substrate
CN113257953A (en) * 2021-04-18 2021-08-13 安徽华晟新能源科技有限公司 Gettering method and phosphorus gettering device for N-type silicon wafer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1591781A (en) * 2003-09-05 2005-03-09 海力士半导体有限公司 Silicon wafers and method of fabricating the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0789555B2 (en) * 1983-09-22 1995-09-27 松下電子工業株式会社 Method of manufacturing solid-state image sensor
US5994761A (en) * 1997-02-26 1999-11-30 Memc Electronic Materials Spa Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
JP4605876B2 (en) * 2000-09-20 2011-01-05 信越半導体株式会社 Silicon wafer and silicon epitaxial wafer manufacturing method
JP4463957B2 (en) * 2000-09-20 2010-05-19 信越半導体株式会社 Silicon wafer manufacturing method and silicon wafer
JP2007235153A (en) * 2002-04-26 2007-09-13 Sumco Corp High-resistance silicon wafer, and manufacturing method thereof
JP3985768B2 (en) * 2003-10-16 2007-10-03 株式会社Ｓｕｍｃｏ Manufacturing method of high resistance silicon wafer
JP2005286282A (en) * 2004-03-01 2005-10-13 Sumco Corp Method of manufacturing simox substrate and simox substrate resulting from same
US7901132B2 (en) * 2006-09-25 2011-03-08 Siltron Inc. Method of identifying crystal defect region in monocrystalline silicon using metal contamination and heat treatment
KR101104492B1 (en) 2009-04-28 2012-01-12 삼성전자주식회사 Method of fabricating single crystal substrate, and method of heat treatment for evaluating the single crystal substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1591781A (en) * 2003-09-05 2005-03-09 海力士半导体有限公司 Silicon wafers and method of fabricating the same

Also Published As

Publication number Publication date
KR101423367B1 (en) 2014-08-04
JP5940238B2 (en) 2016-06-29
CN103498196A (en) 2014-01-08
CN101713098A (en) 2010-05-26
JP2010087512A (en) 2010-04-15
CN101713098B (en) 2013-09-18
KR20100036155A (en) 2010-04-07
KR20110049764A (en) 2011-05-12
TW201026914A (en) 2010-07-16
TWI395844B (en) 2013-05-11

Similar Documents

Publication Publication Date Title
CN103498196B (en) Method for fabricating silicon wafer
US9018735B2 (en) Silicon wafer and fabrication method thereof
US4376657A (en) Method of making fault-free surface zone in semiconductor devices by step-wise heat treating
KR100573473B1 (en) Silicon wafer and method of fabricating the same
KR102453743B1 (en) Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield
US6372611B1 (en) Semiconductor manufacturing method including gettering of metal impurities
KR19990024037A (en) Semiconductor device and manufacturing method thereof
EP2199435A1 (en) Annealed wafer and method for producing annealed wafer
JP2005522879A (en) A method to control the denuded zone depth in ideal oxygen-deposited silicon wafers
KR100319413B1 (en) Method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device
JP2004533125A (en) Method of fabricating a silicon-on-insulator structure having intrinsic gettering by ion implantation
JPS6031231A (en) Manufacture of semiconductor substrate
JP5251137B2 (en) Single crystal silicon wafer and manufacturing method thereof
KR20090006878A (en) Process for producing simox substrate and simox substrate produced by the process
US7807545B2 (en) Method for manufacturing SIMOX wafer
EP1313137A1 (en) Method for manufacturing single-crystal silicon wafers
US5951755A (en) Manufacturing method of semiconductor substrate and inspection method therefor
JP3381816B2 (en) Semiconductor substrate manufacturing method
JPH1074771A (en) Method and apparatus for heat treating silicon single crystal wafer, silicon monocrystalline wafer and its manufacture
JPH11168106A (en) Treatment method of semiconductor substrate
JPH09283529A (en) Manufacture and inspection of semiconductor substrate
JP4035886B2 (en) Silicon epitaxial wafer and manufacturing method thereof
US7740702B2 (en) Silicon wafer and method for manufacturing the same
JP3944958B2 (en) Silicon epitaxial wafer and manufacturing method thereof
JPH08340006A (en) Manufacture of semiconductor element, and mirror surface wafer to be used in said manufacture

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20201020

Address after: Han Guozhongqingbeidao

Patentee after: Key Foundry Co.,Ltd.

Address before: Cheongju Chungbuk Korea

Patentee before: MagnaChip Semiconductor, Ltd.

CP03 Change of name, title or address
CP03 Change of name, title or address

Address after: Republic of Korea

Patentee after: Aisi Kaifang Semiconductor Co.,Ltd.

Country or region after: Republic of Korea

Address before: Han Guozhongqingbeidao

Patentee before: Key Foundry Co.,Ltd.

Country or region before: Republic of Korea