CN104779135A - Method of eliminating influences of control wafer during batch polysilicon deposition process - Google Patents
Method of eliminating influences of control wafer during batch polysilicon deposition process Download PDFInfo
- Publication number
- CN104779135A CN104779135A CN201410011618.8A CN201410011618A CN104779135A CN 104779135 A CN104779135 A CN 104779135A CN 201410011618 A CN201410011618 A CN 201410011618A CN 104779135 A CN104779135 A CN 104779135A
- Authority
- CN
- China
- Prior art keywords
- control wafer
- wafer
- polysilicon deposition
- polysilicon
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 35
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 34
- 238000005137 deposition process Methods 0.000 title abstract 2
- 238000005498 polishing Methods 0.000 claims abstract description 12
- 239000000126 substance Substances 0.000 claims abstract description 11
- 238000004140 cleaning Methods 0.000 claims abstract description 10
- 230000008021 deposition Effects 0.000 claims description 14
- 239000002253 acid Substances 0.000 claims description 3
- 239000003513 alkali Substances 0.000 claims description 3
- 238000005554 pickling Methods 0.000 claims description 3
- 239000010409 thin film Substances 0.000 abstract description 3
- 239000012528 membrane Substances 0.000 description 16
- 239000013078 crystal Substances 0.000 description 12
- 238000000151 deposition Methods 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02096—Cleaning only mechanical cleaning
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The method discloses a method of eliminating influences of a control wafer during a batch polysilicon deposition process. A wafer after special treatment is adopted to serve as a control wafer, polishing treatment is carried out on the front face and the back face of the control wafer, or, after chemical cleaning treatment of a chemical groove is carried out on the back face of the control wafer, brightness of the back face is larger than 80 gloss unit. Influences of the control wafer on a wafer below the control wafer can be eliminated, the thickness and features of a polysilicon thin film on the surface of the wafer below the control wafer are consistent with those of a polysilicon thin film on the surface of a wafer at other place, and the product yield is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of method eliminating control wafer impact in batch type procedure for polysilicon deposition.
Background technology
In the batch type deposited polycrystalline silicon thin film processing procedure of depositing temperature >600 ° C, control wafer is set and come testing product quality and equipment operation situation, the vertical stacked arrangement of wafer, between a collection of wafer, a slice control wafer is set.
After carrying out polysilicon membrane batch deposition, find to be positioned at the polysilicon membrane that the thickness of polysilicon membrane of product crystal column surface below control wafer and the characteristic of polysilicon film are obviously different from the product crystal column surface of other positions.
As shown in Figure 1, the thickness being positioned at the polysilicon membrane of the product crystal column surface below control wafer is obviously much thin than the polysilicon membrane of the product crystal column surface of other positions.
The dry etching speed being positioned at the polysilicon membrane of the product crystal column surface below control wafer also will faster than the dry etching speed of the polysilicon membrane of the crystal column surface of other positions.
This just greatly reduces the yield of product.
Summary of the invention
A kind of method eliminating control wafer impact in batch type procedure for polysilicon deposition provided by the invention, control wafer can be eliminated on the impact being positioned at wafer below control wafer, make the thickness of the polysilicon membrane of the crystal column surface be positioned at below control wafer and characteristic all consistent with the polysilicon membrane of the crystal column surface of other positions, improve product yield.
In order to achieve the above object, the invention provides a kind of method eliminating control wafer impact in batch type procedure for polysilicon deposition, the method adopts through the wafer of special processing as control wafer;
The front and back of described control wafer is all through polishing.
The obverse and reverse polishing of the control wafer of twin polishing all requires to arrive mirror status.
The present invention also provides a kind of method eliminating control wafer impact in batch type procedure for polysilicon deposition, and the method adopts through the wafer of special processing as control wafer;
The back side of described control wafer, after the chemical cleaning process of chemical tank, makes the brightness at its back side be greater than 80 gloss unit.
Described chemical cleaning is divided into pickling, and acid+alkali cleaning.
The present invention can eliminate control wafer to the impact being positioned at wafer below control wafer, makes the thickness of the polysilicon membrane of the crystal column surface be positioned at below control wafer and characteristic all consistent with the polysilicon membrane of the crystal column surface of other positions, improves product yield.
Accompanying drawing explanation
Fig. 1 is the polysilicon membrane thickness table of the wafer obtained in batch type procedure for polysilicon deposition in background technology.
Fig. 2 is the polysilicon membrane thickness table of the wafer obtained have employed method of the present invention in batch type procedure for polysilicon deposition after.
Embodiment
Following according to Fig. 2, illustrate preferred embodiment of the present invention.
The invention provides a kind of method eliminating control wafer impact in batch type procedure for polysilicon deposition, the method adopts through the wafer of special processing as control wafer.
The front and back of described control wafer is all through polishing.
The two-sided brilliant garden polishing machine that all uses of the control wafer of twin polishing carries out polishing, and obverse and reverse polishing all requires to arrive mirror status;
Or the back side of described control wafer, after the chemical cleaning process of chemical tank, makes the brightness at its back side be greater than 80 gloss unit;
Described chemical cleaning is divided into pickling, and acid+alkali cleaning.
As shown in Figure 2, it is the polysilicon membrane thickness table of the wafer obtained have employed method of the present invention in batch type procedure for polysilicon deposition after, it can be seen from the table, employ wafer through special processing as control wafer after, the thickness being positioned at the polysilicon membrane of the crystal column surface below control wafer is all consistent with the polysilicon membrane of the crystal column surface of other positions, improves product yield.
Although content of the present invention has done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (4)
1. in batch type procedure for polysilicon deposition, eliminate a method for control wafer impact, it is characterized in that, the method adopts through the wafer of special processing as control wafer;
The front and back of described control wafer is all through polishing.
2. in batch type procedure for polysilicon deposition, eliminate the method for control wafer impact as claimed in claim 1, it is characterized in that, the obverse and reverse polishing of the control wafer of twin polishing all requires to arrive mirror status.
3. in batch type procedure for polysilicon deposition, eliminate a method for control wafer impact, it is characterized in that, the method adopts through the wafer of special processing as control wafer;
The back side of described control wafer, after the chemical cleaning process of chemical tank, makes the brightness at its back side be greater than 80 gloss unit.
4. in batch type procedure for polysilicon deposition, eliminate the method for control wafer impact as claimed in claim 3, it is characterized in that, described chemical cleaning is divided into pickling, and acid+alkali cleaning.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410011618.8A CN104779135A (en) | 2014-01-10 | 2014-01-10 | Method of eliminating influences of control wafer during batch polysilicon deposition process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410011618.8A CN104779135A (en) | 2014-01-10 | 2014-01-10 | Method of eliminating influences of control wafer during batch polysilicon deposition process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104779135A true CN104779135A (en) | 2015-07-15 |
Family
ID=53620546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410011618.8A Pending CN104779135A (en) | 2014-01-10 | 2014-01-10 | Method of eliminating influences of control wafer during batch polysilicon deposition process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104779135A (en) |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1154591A (en) * | 1997-08-06 | 1999-02-26 | Texas Instr Japan Ltd | Dummy wafer and method of using the same |
| CN1378235A (en) * | 2001-03-30 | 2002-11-06 | 华邦电子股份有限公司 | Cleaning method for reclaimed chip |
| CN1434883A (en) * | 2000-05-08 | 2003-08-06 | Memc电子材料有限公司 | Epitaxial silicon wafer free from autodoping and backside halo |
| US20050042800A1 (en) * | 2002-02-22 | 2005-02-24 | Mitsui Engineering & Shipping Co Ltd | Production method of sic monitor wafer |
| CN1632910A (en) * | 2003-12-25 | 2005-06-29 | 中芯国际集成电路制造(上海)有限公司 | Control wafer recovery and regenerating method and control wafer structure thereof |
| US20050248004A1 (en) * | 2004-05-10 | 2005-11-10 | Mosel Vitelic, Inc. | Wafer and the manufacturing and reclaiming methods thereof |
| KR20060066390A (en) * | 2004-12-13 | 2006-06-16 | 주식회사 하이닉스반도체 | Method of forming a isolation layer in a semiconductor device |
| US20090042390A1 (en) * | 2007-08-09 | 2009-02-12 | Sakae Koyata | Etchant for silicon wafer surface shape control and method for manufacturing silicon wafers using the same |
| CN201238043Y (en) * | 2008-05-29 | 2009-05-13 | 北大方正集团有限公司 | Control wafer and retaining wafer |
| CN101661869A (en) * | 2008-08-25 | 2010-03-03 | 北京有色金属研究总院 | Method for cleaning polished gallium arsenide chip and laundry drier |
| CN102085517A (en) * | 2009-12-03 | 2011-06-08 | 无锡华润上华半导体有限公司 | Method and device for cleaning grid oxygen control wafer |
| CN102456543A (en) * | 2010-10-21 | 2012-05-16 | 上海华虹Nec电子有限公司 | Negative film recycling method applied to batch treatment ion implanter |
| CN102646620A (en) * | 2012-05-08 | 2012-08-22 | 中国科学院半导体研究所 | Uniform axial force applying device for graphical heterogeneous bonding of silicon-based III-V epitaxial material |
| CN103498196A (en) * | 2008-09-29 | 2014-01-08 | 美格纳半导体有限会社 | Method for fabricating silicon wafer |
-
2014
- 2014-01-10 CN CN201410011618.8A patent/CN104779135A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1154591A (en) * | 1997-08-06 | 1999-02-26 | Texas Instr Japan Ltd | Dummy wafer and method of using the same |
| CN1434883A (en) * | 2000-05-08 | 2003-08-06 | Memc电子材料有限公司 | Epitaxial silicon wafer free from autodoping and backside halo |
| CN1378235A (en) * | 2001-03-30 | 2002-11-06 | 华邦电子股份有限公司 | Cleaning method for reclaimed chip |
| US20050042800A1 (en) * | 2002-02-22 | 2005-02-24 | Mitsui Engineering & Shipping Co Ltd | Production method of sic monitor wafer |
| CN1632910A (en) * | 2003-12-25 | 2005-06-29 | 中芯国际集成电路制造(上海)有限公司 | Control wafer recovery and regenerating method and control wafer structure thereof |
| US20050248004A1 (en) * | 2004-05-10 | 2005-11-10 | Mosel Vitelic, Inc. | Wafer and the manufacturing and reclaiming methods thereof |
| KR20060066390A (en) * | 2004-12-13 | 2006-06-16 | 주식회사 하이닉스반도체 | Method of forming a isolation layer in a semiconductor device |
| US20090042390A1 (en) * | 2007-08-09 | 2009-02-12 | Sakae Koyata | Etchant for silicon wafer surface shape control and method for manufacturing silicon wafers using the same |
| CN201238043Y (en) * | 2008-05-29 | 2009-05-13 | 北大方正集团有限公司 | Control wafer and retaining wafer |
| CN101661869A (en) * | 2008-08-25 | 2010-03-03 | 北京有色金属研究总院 | Method for cleaning polished gallium arsenide chip and laundry drier |
| CN103498196A (en) * | 2008-09-29 | 2014-01-08 | 美格纳半导体有限会社 | Method for fabricating silicon wafer |
| CN102085517A (en) * | 2009-12-03 | 2011-06-08 | 无锡华润上华半导体有限公司 | Method and device for cleaning grid oxygen control wafer |
| CN102456543A (en) * | 2010-10-21 | 2012-05-16 | 上海华虹Nec电子有限公司 | Negative film recycling method applied to batch treatment ion implanter |
| CN102646620A (en) * | 2012-05-08 | 2012-08-22 | 中国科学院半导体研究所 | Uniform axial force applying device for graphical heterogeneous bonding of silicon-based III-V epitaxial material |
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| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150715 |
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| RJ01 | Rejection of invention patent application after publication |